CAPITOLO 3

 Outputs of sequential logic depend on current and prior input values – it has memory.
 Some definitions:
o State: all the information about a circuit necessary to explain its future behavior
o Latches and flip-flops: state elements that store one bit of state
o Synchronous sequential circuits: combinational logic followed by a bank of flip-flops

CIRCUITI SEQUENZIALI

 Sequential logic might explicitly remember certain previous inputs, or it might distill the prior
inputs into a smaller amount of information called the state of the system
 Have memory (short-term)
 Use feedback from output to input to store information

ELEMENTI DI STATO (state elements)

 The state of a circuit influences its future behavior

 State elements store state
o Bistable circuit
o SR Latch
o D Latch
o D Flip-flop

BISTABLE CIRCUIT:

 Fundamental building block (blocco fondamentale)

of other state elements
 Two outputs: Q, Q
 No inputs
Ci serve per modellare qualunque sistema in grado di memorizzare un bit di informazione, perché la
memorizzazione del bit avviene usando questa retrazione.

ANALISI CIRCUITI BISTABILI:

 Consider the two possible cases:

o Q = 0: 
   then Q = 0, Q = 1 (consistent)
 Q = 1: 
   then Q = 1, Q = 0 (consistent)
 Stores 1 bit of state in the state variable, Q (or Q)
But there are no inputs to control the state

Per controllare il bistable circuit, viene usato il set/reset.

SR (Set/Reset) Latch

 SR Latch
 Consider the four possible cases:
 S = 1, R = 0
 S = 0, R = 1
 S = 0, R = 0
 S = 1, R = 1

Simbolo latch, 2
ingressi e due
uscite

Non deve mai capitare il caso S = 1 e R = 1, per evitare proprio questa condizione è stato creato il:

D LATCH, D sta per data

Ha due input: CLK e D

 CLK, controlla quando l’immagine cambia

 D, data

Funzione:

 Quando CLK = 1 -> Passa D, Q=D

 Quando CLK = 0 -> Q memorizza il valore precedente(mantiene il
vecchio valore Q = Q precedente
Disegno D-latch partendo da MUX a 2 ingressi

Disegnare un latch SR partendo da un MUX a 2 ingressi:

D-FLIP FLOP

 Inputs: CLK, D
 Function
o Campiona D sul fronte di salita del CLK
 When CLK passa from 0 to 1, D passes through to Q
 altrimenti, Q holds its previous value
o Q changes only sul fronte di salita of CLK
 Called edge-triggered
 Activated on the clock edge

CIRCUITO INTERNO D-FLIP FLOP

 Two back-to-back latches (L1 and L2) controlled by complementary clocks

 When CLK = 0
 L1 is transparent
 L2 is opaque
 D passes through to N1
 When CLK = 1
 L2 is transparent
 L1 is opaque
 N1 passes through to Q
 Thus, on the edge of the clock (when CLK rises from 0   1)
 D passes through to Q