dw30 Cp-Dis 09288 RSA 0903 1

5 4 3 2 1
D D
DW30 Winery CALPELLA DIS N11M-GE1 Schematics

uFCPGA Mobile Arrandale
C
Intel Ibex Peak-M C
2009-09-01
REV : SA
B B
DY : Nopop Component
UMA : Pop when schematic is UMA
DIS : Pop when schematic is DIS
A A
1st Samsung
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
www.vinafix.vn
Size Document Number Rev
Custom
Vostro Calpella SA
Date: Thursday, September 03, 2009 Sheet 1 of 88
5 4 3 2 1
5 4 3 2 1
CPU DC/DC
PCB LAYER
Winery CALPELLA Block Diagram INPUTS
ISL62883
OUTPUTS
47,48
L1: Top Project code : 91.4EX01.001 +PWR_SRC +VCC_CORE
L2: GND Part Number : 48.4EX11.0SA

L3: Signal SYSTEM DC/DC
46
TPS51125
D
L4: Signal PCB P/N : 09288 D
L5: VCC INPUTS OUTPUTS

L6: Signal Clock Generator
Revision : SA +15V_ALW
+3.3V_RTC_LDO
+PWR_SRC +5V_ALW
L7: GND SLG8SP585 7 +3.3V_ALW
L8: Bottom
DDRIII 1066 Channel A
DDRIII Slot 0 SYSTEM DC/DC
1066 18 50
Intel CPU TPS51116
100MHz/ 800/1066MHz Power SW
INPUTS OUTPUTS
2.5Gbps TPS2231R 34
Nvidia DDR III 1066 Channel B DDRIII Slot 1 +PWR_SRC
+1.5V_SUS
+0.75V_DDR_VTT
VRAM(gDDR3) 19 +V_DDR_REF
VRAM
N11M-GE1(40nm) PCIe x 16 800/1066MHz 1066
64Mbx16x4 (512MB)484,85 Arrandale
Bandwidth New Card SYSTEM DC/DC
PCIE x 1 & USB 2.0 x 1
80,81,82,83 :8GB 34 53
(FPC Cable to Connect) ADP3211
INPUTS OUTPUTS
LVDS RGB CRT 10/100/1000LOM RJ45
8,9,10,11,12,13,14 PCIE x 1 +PWR_SRC +CPU_GFXCORE
C C
RTL8111DL 35 CONN
CRT 55
RGB CRT RGB CRT
USB 2.0 x 2 PCIE x 1 Mini-Card SYSTEM DC/DC
86
Switchable WWAN/ WiMAX? TPS51218
DMIx4 FDI(UMA)
LCD LVDS LVDS 2.5 GT/s 2.7 GT/s 100MHz Left Side: INPUTS OUTPUTS
(Single Chanel) 54 74 USB 2.0 x 1
USB x 1
2.5Gbps +PWR_SRC +VCC_GFX_CORE
RGB CRT PCIE (On daughter board)
CHARGER
LVDS
Intel BQ24745 45
USB 2.0 USB 2.0 x 1 PCIE x 1 Mini-Card

PCH WLAN 802.11a/b/g/n 64 INPUTS OUTPUTS
480Mbps
CardReader +DC_IN
+PBATT
+PWR_SRC
(3 in 1) 14 USB 2.0/1.1 ports Right Side:

USB 2.0 x 1
SD/MMC/MMC+ USB x 1 63
33
REALTEK
ETHERNET (10/100/1000Mb) SYSTEM DC/DC
49
USB 2.0 High Definition Audio TPS51218
B
RTS5138 B
480Mbps SATA ports (6) Free fall sensor USB 2.0 x 1

SM Bus
40 Bluetooth 73 INPUTS OUTPUTS
32
PCIE ports (8)
400KHz +PWR_SRC +1.05V_VTT
LPC I/F
CAMERA ACPI 1.1
USB2.0 x 1 USB 2.0 x 1 Biometric
73 78
PCI/PCI BRIDGE LPC Bus TPM 36 LDO
51
33MHz APL5930
Digital Mic Array AZALIA 20,21,22,23,24,25,26,27,28
INPUTS OUTPUTS
Azalia 24MHz
+3.3V_ALW +1.8V_RUN
CODEC KBC
MIC IN SPI NUVOTON SM Bus Thermal & Fan LDO
OP AMP
SATA,USB
37 39,58 51
NPCE781BA0DX EMC2102 RT9025
SPI
SATA
3Gbps
HP OUT INPUTS OUTPUTS

IDT
Capacity Board
92HD81UA30 78
+3.3V_ALW +1.8V_RUN_GPU
A A
1st Samsung
Flash ROM Touch Int.
256kB 62 PAD 68
KB 68 Wistron Corporation
USB,ESATA ODD Flash ROM Taipei Hsien 221, Taiwan, R.O.C.
1CH SPEAKER Multi-Port x1
63 HDD59 4MB 62 Title
60
Block Diagram
www.vinafix.vn
Custom
Vostro Calpella SA
Date: Wednesday, September 02, 2009 Sheet 2 of 88
5 4 3 2 1
5 4 3 2 1
D D
+PWR_SRC TPS51116PWPRG4
Adapter 50
ISL62883 ADP3211 TPS51218 TPS51218DSCR

AO4407A 47、48 53 86 49 +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
45 Charger
BQ24745
+VCC_CORE +CPU_GFXCORE +VCC_GFX_CORE +1.05V_VTT FDS8880
Battery +PBATT 87
45 For Intel GPU For NVIDIA GPU Arrandale : 1.05V
FDS8880
+1.5V_RUN_GPU
87
TPS51125
46
+1.05V_GFX_PCIE
C
AO3420 C
52 AO4468
+5V_ALW +5V_ALW2 +3.3V_ALW_2
42
+5V_ALW +3.3V_ALW +1.5V_CPU
+15V_ALW +3.3V_RTC_LDO
+1.5V_RUN
TPS2062AD AO4468 TPS2062AD AO3403 TPS2231R AO4468 APL5930 RT9025 AO3434 TPS2231R
I/O BD 42 63 I/O BD 34 42 51 51 87 34
+5V_USB2 +5V_RUN +5V_USB1 +3.3V_LAN +3.3V_CARDAUX +3.3V_RUN +1.8V_RUN +1.8V_RUN_GPU

+3.3V_RUN_GPU +1.5V_CARD
B
For USB2 For USB1 & ESATA1 B
RTL8111DL
I/O BD
SI3456BDV TPS2231R
54 34
+1.2V_LOM
+LCDVDD +3.3V_CARD
Power Shape
Regulator LDO Switch

A A
1st Samsung
Wistron Corporation
Title
Size
Power Block Diagram
Document Number Rev
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN

Switchable Graphic SMBus Block Diagram
+3.3V_RUN+3.3V_RUN
‧ ‧
+3.3V_RUN
PCH ‧ ‧
SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP
‧
PCH DIMM 1 +3.3V_RUN
+3.3V_RUN
D
SMBCLK SMB_CLK
‧ ‧PCH_SMBCLK SCL L_DDC_CLK
D
L_DDC_CLK ‧ B1
VCC
‧
SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA SDA 18 LDDC_CLK
‧ B0 A
23 SMBus Address:A0 L_DDC_DATA GND S
2N7002SPT DIMM 2 NC7SB3157P6X-1GP

SRN2K2J-1-GP
‧PCH_SMBCLK SCL
‧ PCH_SMBDATA SDA 19
SMBus Address:A2 LDDC_CLK_CON
‧
LCD Conn.
Clock LDDC_DATA_CON
‧ 54
Generator
‧ PCH_SMBCLK SMBCLK +3.3V_RUN
‧ PCH_SMBDATA SMBDATA 07
SMBus address:D2
Express Minicard
L_DDC_DATA
LDDC_DATA
‧
‧
B1
B0
VCC
Card WLAN GND S
SMB_CLK ‧ PCH_SMBCLK SMB_CLK

64 CRT_DDC_CLK
NC7SB3157P6X-1GP
SMB_CLK ‧ PCH_SMBDATA SMB_DATA
SMB_DATA CRT_DDC_DATA +3.3V_RUN
SMB_DATA
34 Minicard +3.3V_RUN +3.3V_RUN
PCH_SMBCLK
WWAN ‧ ‧ ‧
‧ SMB_CLK
I/O BD
‧ PCH_SMBDATA SMB_DATA
SRN2K2J-1-GP
SRN2K2J-1-GP
Free fall +3.3V_RUN DY +5V_CRT_RUN

C C
sensor GMCH_DDCCLK
‧
‧
PCH_SMBCLK SCL/SPC CRT_CLK_DDC ‧ B1 VCC
‧ PCH_SMBDATA SDA/SDI/SDO 40
‧ B0 A
DDC_CLK_CON2
‧ +3.3V_RUN_GPU
GND S
SRN2K2J-1-GP
NC7SB3157P6X-1GP
‧
DDC_CLK_CON
‧
‧ CRT CONN
55
KBC SMBus Block Diagram N11M-GE1 +3.3V_RUN

2N7002DW-1-GP
DDC_DATA_CON
+5V_RUN I2CC_SCL
GMCH_DDCDATA
I2CC_SDA CRT_DAT_DDC‧ B1 VCC
DDC_DATA_CON2
‧ B0 A ‧
‧ GND S
NC7SB3157P6X-1GP
SRN10KJ-5-GP
TouchPad Conn.
PSDAT1
TPDATA
‧ TPDATA TPDATA
68
B PSCLK1
TPCLK
‧ TPCLK TPCLK
I2CA_SCL B
+3.3V_RTC_LDO
I2CA_SDA
BQ24745
‧ SCL
SDA
45
SMBus address:12
SRN4K7J-8-GP
Battery Conn.
SCL1 BAT_SCL
‧ ‧ PBAT_SMBCLK1 CLK_SMB
SDA1 BAT_SDA
‧ ‧ PBAT_SMBDAT1 DAT_SMB 44
Remove HDMI
SRN100J-3-GP SMBus address:16
KBC ‧
NPCE781 +3.3V_RTC_LDO
+3.3V_RUN
IFPC_AUX_I2CW_SCL
SRN4K7J-8-GP IFPC_AUX_I2CW_SDA#
+3.3V_RUN
‧ ‧ Thermal
SRN4K7J-8-GP
‧ THERM_SCL SMCLK
A THERM_SDA 39 A
‧ SMDATA
SMBus address:7A
GPIO73/SCL2 KBC_SCL1
‧ 2N7002DW-1-GP
1st Samsung
KBC_SDA1
GPIO74/SDA2 ‧ Capacity Wistron Corporation
THERM_SCL Board 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SCL
THERM_SDA SDA
(On daughter board) Title
www.vinafix.vn
SMBus address:0A SMBUS Block Diagram
C SA
Vostro Calpella
5 4 3 2 1
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPEAKER
SPKR_PORT_D_L- AUD_SPK_L- AUD_SPK_L-_C
AUD_SPK_L+ AUD_SPK_L+_C
SPKR_PORT_D_L+
0R3-0-U-V-GP
DP1 EMC2102_DP1 60
MMBT3904-3-GP
SC470P50V3JN-2GP
2 Q3905 2
DN1 EMC2102_DN1
HP1_PORT_B_L AUD_HP1_JACK_L
HP
Close to PCH HP1_PORT_B_R AUD_HP1_JACK_R
Thermal OUT
EMC2102 Codec 60
DP2 VGA_THERMDA DPLUS

92HD81
SC470P50V3JN-2GP GPU
DN2 VGA_THERMDC DMINUS
54 DIS HP0_PORT_A_L
HP0_PORT_A_R
AUD_EXT_MIC_L
AUD_EXT_MIC_R
MIC
VREFOUT_A_OR_F AUD_VREFOUT_B
IN
60
3 3
DP3 T8_THERMDC
MMBT3904-3-GP
DMIC_CLK/GPIO1 AUD_DMIC_CLK
33R2J-2-GP
AUD_DMIC_CLK_G Digital
DN3 T8_THERMDA
SC470P50V3JN-2GP
Q3901
DMIC0/GPIO2
AUD_DMIC_IN0
MIC
33R2J-2-GP AUD_DMIC_IN0_R
Array 73
39
HW T8 sensor
30
4 4
1st Samsung
Wistron Corporation
Title
Thermal/Audio Block Diagram
www.vinafix.vn
Custom
Vostro Calpella SA
A B C D E
A B C D E
PCH Strapping Calpella Schematic Checklist Rev1.6 Processor Strapping Calpella Schematic Checklist Rev1.6
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
1 unless specified otherwise) Value
Reboot option at power-up
SPKR Default Mode: Internal weak Pull-down. CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ DisplayPort Embedded DisplayPort.
- 10-kΩ weak pull-up resistor. Intel suggest 1K resistor (Fonseca) Presence 0: Enabled - An external Display Port device is
connected to the Embedded Display Port.
INIT3_3V# Internal pull-up. Leave as "No Connect"
4 CFG[3] PCI-Express Static 1: Normal Operation. 1 4
Default Mode: Internal pull-up. Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
GNT3#/ Low (0) = Top Block Swap Mode
GPIO55 Note: Connect to ground with 4.7-kΩ weak pull-down resistor. CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
CRB uses a 1 kΩ; do not stuff resistor.
Configuration 0: Bifurcation enabled
Select
INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Note: CRB uses a 330-kΩ resistor.
Default (SPI): Leave both GNT0# and GNT1# floating. No pull up

GNT0#, required.
GNT1#
Boot from PCI:
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ
pull-down resistor. Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floating.
GNT2#/ Default - Internal pull-up.
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).
Enable Intel Anti-Theft Technology:Connect to Vcc3_3

3 SPI_MOSI 3
with 8.2-kΩ weak pull-up resistor.
Disable Intel Anti-Theft Technology:Left floating, no pull-down PCIE Routing
required.
LANE1 Card reader
NV_ALE Enable Intel Anti-Theft Technology:Connect to +NVRAM_Vccq with
8.2-kΩ weak pull-up resistor.[CRB has it pulled up with 1-kΩ
no-stuff resistor]
LANE2 MiniCard WLAN
Disable Intel Anti-Theft Technology:Leave floating (internal pull-down)
LANE3 LAN
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
LANE4 MiniCard WWAN
Low (0)- Flash Descriptor Security will be overridden. Also, when
HAD_DOCK_EN#
/GPIO[33]
this signals is sampled on the rising edge of PWROK then it will also
disable Intel ME and its features.
LANE5 New Card
High (1)-:Security measure defined in the Flash Descriptor
will be enabled.
Platform design should provide appropriate pull-up or pull-down

USB Table
depending on the desired settings. If a jumper option is used to USB
tie this signal to GND as required by the functional strap, Pair Device
the signal should be pulled low through a weak pull-down in order
to avoid asserting HDA_DOCK_EN# inadvertently. 0 USB1
Note:CRB recommends 1-kΩ pull-down for FD Override.
1 USB for ESATA
2 There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only
enabled at boot/reset for strapping functions.
2
2 USB2
3 RESERVE
4 WLAN
HDA_SDO Weak internal pull-down. Do not pull high. 5 WWAN
Sampled at rising edge of RSMRST#.
6 RESERVED
(Not available for HM55)
HDA_SYNC Weak internal pull-down. Do not pull high. 7 RESERVED
Sampled at rising edge of RSMRST#. (Not available for HM55)
8 BlUETOOTH
GPIO15 Low (0)-Intel ME Crypto Transport Layer Security (TLS) cipher suite 9 Card Reader
with no confidentiality
High (1)-:Intel ME Crypto Transport Layer Security (TLS) cipher suite 10 Biometric
with confidentiality 11 CAMERA
Note:
This is an unmuxed signal. 12 New Card
This signal has a weak internal pull-down of 20 KΩ which is enabled
when PWROK is low. 13 RESERVED
CRB has a 1-kΩ pull-up on this signal to +3.3VA rail.
1 GPIO8 Weak internal pull-up. Do not pull low.

1st Samsung 1
Wistron Corporation
GPIO27 Default = Do not connect (floating). Internal pull-up. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit. Title
Low (0) = Disables the VccVRM. Need to use on-board filter
Table of Content
www.vinafix.vn
circuits for analog rails.
Custom
Vostro Calpella SA
5 4 3 2 1
D D
68.00119.131 0603
+3.3V_RUN +3.3V_RUN_SL585
68.00084.521 0805 +1.05V_VTT
68.00119.131 +1.05V_RUN_SL585_IO
R708 1 2 0R3J-0-U-GP R709 1 2 0R3J-0-U-GP
1
1
C709 C710 C711 C712
C708
DY DY SCD1U10V2KX-4GP DYDo Not Stuff SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
C701 C702 C704 C707
Do Not Stuff Do Not Stuff SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C703 C705
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
C C
24
17
29
15
18
1
5
U701 VGA 27M R706 R710
VDD_27
VDD_SRC_IO
VDD_CPU_IO
VDD_CPU
VDD_SRC
VDD_REF
VDD_DOT
SS DY Mount
NON-SS Mount DY +3.3V_RUN_SL585
VR_CLKEN# [47]
2
RN701 CLK_MCH_DREFCLK1# CLK_27M R706 2 1 Do Not Stuff
[23] DREFCLK#
2
SRN0J-6-GP 1
3
CLK_MCH_DREFCLK1
4 DOT_96# 27MHZ 6
CLK_27M_SS R710 2 DY 1 Do Not Stuff
CLK_VGA_27M [81]
R705
4 3 7
DY
G
[23] DREFCLK DOT_96 27MHZ_SS 10KR2J-3-GP
RN702 2 3 CLK_IN_DMI# 14 +3.3V_RUN
[23] CLKIN_DMI# SRC_2#
[23] CLKIN_DMI SRN0J-6-GP 1 4 CLK_IN_DMI 13 16 CPU_STOP# R701 2 1 2K2R2J-2-GP
1
SRC_2 CPU_STOP# CK_PWRGD CK_PWRGD
CKPWRGD/PD# 25 D S
[23] CLK_PCIE_SATA# RN703 2 3 CLK_PCIE_SATA1# 11 30 FSC R703 2 1 33R2J-2-GP CLK_PCH_14M [23]
SRC_1/SATA# REF_0/CPU_SEL
1
[23] CLK_PCIE_SATA SRN0J-6-GP 1 4 CLK_PCIE_SATA1 10 SRC_1/SATA EC701
[23] CLK_CPU_BCLK# RN704 1 4 CLK_CPU_BCLK1# 22 28 CLK_XTAL_IN DY Do Not Stuff Q701
2
SRN0J-6-GP 2 CLK_CPU_BCLK1 CPU_0# XTAL_IN CLK_XTAL_OUT 2N7002A-7-GP
[23] CLK_CPU_BCLK 3 23 CPU_0 XTAL_OUT 27
Do Not Stuff TP701 1 TP_CPU_1# 19 31

CPU_1# SDA PCH_SMBDATA [18,19,23,40,64,76]
Do Not Stuff TP702 1 TP_CPU_1 20 32
CPU_1 SCL PCH_SMBCLK [18,19,23,40,64,76]
VSS_SATA
VSS_CPU
VSS_SRC
VSS_DOT
VSS_REF
VSS_27
GND
CLK_XTAL_IN
B SLG8SP585VTR-GP B
X701
33
26
21
12
1 2 CLK_XTAL_OUT
X-14D31818M-37GP DW
1
CLK_VGA_27M
2
C714 C715 07/07 Added
1st Silego 71.08585.003 SC12P50V2JN-3GP SC12P50V2JN-3GP 1.Added R,C For CLK_VGA_27M EMI
2
2nd ICS 71.93197.003 DY R749
Do Not Stuff
+1.05V_VTT
1 CLK_VGA_27M_RC
2
R704 FSC 0 1
Do Not Stuff
DY
133MHz
2 1
FSC SPEED 100MHz
2
(Default)
R707
10KR2J-3-GP
DY C718
Do Not Stuff
1
1
A 1st Samsung A
Wistron Corporation
Title
Clock Generator SLG8SP585

5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
Wednesday, September 02, 2009 Sheet
1
7 of 88
X00
5 4 3 2 1
D D
CPU1A 1 OF 9
B26 PEG_IRCOMP_R R801 1 2 49D9R2F-GP
PEG_ICOMPI R802 1
PEG_ICOMPO A26 2 750R2F-GP
[22] DMI_PTX_CRXN0 A24 DMI_RX#0 PEG_RCOMPO B27
[22] DMI_PTX_CRXN1 C23 A25 EXP_RBIAS
DMI_RX#1 PEG_RBIAS PCIE_MRX_GTX_N[0..15]
[22] DMI_PTX_CRXN2 B22 DMI_RX#2 PCIE_MRX_GTX_N[0..15] [80]
A21 K35 PCIE_MRX_GTX_N15
CLARKSFIELD
[22] DMI_PTX_CRXN3 DMI_RX#3 PEG_RX#0
J34 PCIE_MRX_GTX_N14
PEG_RX#1 PCIE_MRX_GTX_N13
[22] DMI_PTX_CRXP0 B24 DMI_RX0 PEG_RX#2 J33
[22] DMI_PTX_CRXP1 D23 G35 PCIE_MRX_GTX_N12
DMI_RX1 PEG_RX#3
DMI
[22] DMI_PTX_CRXP2 B23 G32 PCIE_MRX_GTX_N11
DMI_RX2 PEG_RX#4 PCIE_MRX_GTX_N10
[22] DMI_PTX_CRXP3 A22 DMI_RX3 PEG_RX#5 F34
F31 PCIE_MRX_GTX_N9
PEG_RX#6 PCIE_MRX_GTX_N8
[22] DMI_CTX_PRXN0 D24 DMI_TX#0 PEG_RX#7 D35
[22] DMI_CTX_PRXN1 G24 E33 PCIE_MRX_GTX_N7
DMI_TX#1 PEG_RX#8 PCIE_MRX_GTX_N6
[22] DMI_CTX_PRXN2 F23 DMI_TX#2 PEG_RX#9 C33
[22] DMI_CTX_PRXN3 H23 D32 PCIE_MRX_GTX_N5
DMI_TX#3 PEG_RX#10 PCIE_MRX_GTX_N4
PEG_RX#11 B32
[22] DMI_CTX_PRXP0 D25 C31 PCIE_MRX_GTX_N3
DMI_TX0 PEG_RX#12 PCIE_MRX_GTX_N2
[22] DMI_CTX_PRXP1 F24 DMI_TX1 PEG_RX#13 B28
[22] DMI_CTX_PRXP2 E23 B30 PCIE_MRX_GTX_N1
DMI_TX2 PEG_RX#14 PCIE_MRX_GTX_N0
[22] DMI_CTX_PRXP3 G23 DMI_TX3 PEG_RX#15 A31
PCIE_MRX_GTX_P[0..15]
PCIE_MRX_GTX_P[0..15] [80]
J35 PCIE_MRX_GTX_P15
PEG_RX0 PCIE_MRX_GTX_P14
PEG_RX1 H34
C [22] FDI_TXN0 FDI_TXN0 E22
PEG_RX2 H33
F35
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P12 C
FDI_TXN1 FDI_TX#0 PEG_RX3 PCIE_MRX_GTX_P11
[22] FDI_TXN1 D21 FDI_TX#1 PEG_RX4 G33
[22] FDI_TXN2 FDI_TXN2 D19 E34 PCIE_MRX_GTX_P10
[22] FDI_TXN3 D18 FDI_TX#3 PEG_RX6 F32
[22] FDI_TXN4 FDI_TXN4 G21 D34 PCIE_MRX_GTX_P8
[22] FDI_TXN5 E19 FDI_TX#5 PEG_RX8 F33
[22] FDI_TXN6 FDI_TXN6 F21 B33 PCIE_MRX_GTX_P6
FDI_TX#6 PEG_RX9
Intel(R) FDI
[22] FDI_TXN7 FDI_TXN7 G18 D31 PCIE_MRX_GTX_P5
FDI_TX#7 PEG_RX10 PCIE_MRX_GTX_P4
PEG_RX11 A32
PCI EXPRESS -- GRAPHICS

C30 PCIE_MRX_GTX_P3
FDI_TXP0 PEG_RX12 PCIE_MRX_GTX_P2
[22] FDI_TXP0 D22 FDI_TX0 PEG_RX13 A28
[22] FDI_TXP1 FDI_TXP1 C21 B29 PCIE_MRX_GTX_P1
FDI_TXP2 FDI_TX1 PEG_RX14 PCIE_MRX_GTX_P0 PCIE_MTX_GRX_N[0..15]
[22] FDI_TXP2 D20 FDI_TX2 PEG_RX15 A30 PCIE_MTX_GRX_N[0..15] [80]
[22] FDI_TXP3 FDI_TXP3 C18
FDI_TXP4 FDI_TX3 PCIE_MTX_GRX_C_N15 C829 SCD1U10V2KX-5GP PCIE_MTX_GRX_N15
[22] FDI_TXP4 G22 FDI_TX4 PEG_TX#0 L33 1 2
[22] FDI_TXP5 FDI_TXP5 E20 M35 PCIE_MTX_GRX_C_N14 C827 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N14
FDI_TXP6 FDI_TX5 PEG_TX#1 PCIE_MTX_GRX_C_N13 C832 SCD1U10V2KX-5GP PCIE_MTX_GRX_N13
[22] FDI_TXP6 F20 FDI_TX6 PEG_TX#2 M33 1 2
[22] FDI_TXP7 FDI_TXP7 G19 M30 PCIE_MTX_GRX_C_N12 C812 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N12
FDI_TX7 PEG_TX#3 PCIE_MTX_GRX_C_N11 C803 SCD1U10V2KX-5GP PCIE_MTX_GRX_N11
PEG_TX#4 L31 1 2
[22] FDI_FSYNC0 F17 K32 PCIE_MTX_GRX_C_N10 C811 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N10
FDI_FSYNC0 PEG_TX#5 PCIE_MTX_GRX_C_N9 C828 SCD1U10V2KX-5GP PCIE_MTX_GRX_N9
[22] FDI_FSYNC1 E17 FDI_FSYNC1 PEG_TX#6 M29 1 2
J31 PCIE_MTX_GRX_C_N8 C810 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N8
PEG_TX#7 PCIE_MTX_GRX_C_N7 C823 SCD1U10V2KX-5GP PCIE_MTX_GRX_N7
[22] FDI_INT C17 FDI_INT PEG_TX#8 K29 1 2
H30 PCIE_MTX_GRX_C_N6 C804 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N6
[22] FDI_LSYNC0 F18 FDI_LSYNC0 PEG_TX#10 H29 1 2
[22] FDI_LSYNC1 D17 F29 PCIE_MTX_GRX_C_N4 C825 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N4
FDI_LSYNC1 PEG_TX#11 PCIE_MTX_GRX_C_N3 C821 SCD1U10V2KX-5GP PCIE_MTX_GRX_N3
PEG_TX#12 E28 1 2
D29 PCIE_MTX_GRX_C_N2 C813 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N2
B Calpella Platform Design Guide PEG_TX#14 D27
PCIE_MTX_GRX_C_N0 C816
1 2
SCD1U10V2KX-5GP PCIE_MTX_GRX_N0 B
PEG_TX#15 C26 1 2
Revision 1.6 PCIE_MTX_GRX_P[0..15]
Page 89 PCIE_MTX_GRX_C_P15 C826 SCD1U10V2KX-5GP PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P[0..15] [80]
PEG_TX0 L34 1 2
2.4 Arrandale Graphics Disable Guideline M34 PCIE_MTX_GRX_C_P14 C822 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P14
PEG_TX1 PCIE_MTX_GRX_C_P13 C818 SCD1U10V2KX-5GP PCIE_MTX_GRX_P13
PEG_TX2 M32 1 2
It applies to Arrandale and Clarksfield discrete graphic designs. L30 PCIE_MTX_GRX_C_P12 C815 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P12
PEG_TX4 M31 1 2
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, K31 PCIE_MTX_GRX_C_P10 C802 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P10
M28 1 2
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PEG_TX6
H31 PCIE_MTX_GRX_C_P8 C805 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P8
the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors). PEG_TX8 K28 1 2
G30 PCIE_MTX_GRX_C_P6 C801 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P6
PEG_TX10 G29 1 2
F28 PCIE_MTX_GRX_C_P4 C824 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P4
DW PEG_TX12 E27
D28 PCIE_MTX_GRX_C_P2 C809
1
1
2
2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P2
07/02 Added PEG_TX13 PCIE_MTX_GRX_C_P1 C807 SCD1U10V2KX-5GP PCIE_MTX_GRX_P1
PEG_TX14 C27 1 2
1.Added Flexible Display Interface (IntelR FDI) commentariat PCIE_MTX_GRX_C_P0 C819 SCD1U10V2KX-5GP PCIE_MTX_GRX_P0
PEG_TX15 C25 1 2
CLARKUNF
DW
07/10 Reversal
1.PCI-Express Static Lane Reversal
(15 -> 0, 14 -> 1, ...)
A 1st Samsung
A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
www.vinafix.vn
Vostro Calpella X00
5 4 3 SA 2 1
07/01 Check
Processor Compensation Signals 1.assign GPIO EC_GPIO91 ??
+1.05V_VTT CPU1B 2 OF 9
Processor Pullups H_COMP3
DDR_RST_GATE# [25] +3.3V_ALW
1 2 AT23 COMP3
R901 20R2F-GP A16 BCLK_CPU_P_R 2 3 RN901 BCLK_CPU_P [25]
BCLK
1
MISC
R902 1 2 49D9R2F-GP H_CATERR# 1 2 H_COMP2 AT24 B16 BCLK_CPU_N_R 1 4 SRN0J-6-GP C915
R903 20R2F-GP COMP2 BCLK# BCLK_CPU_N [25] DY Do Not Stuff
H_COMP1 +1.5V_SUS
CLOCKS
1 2 G16 AR30
Check
2
R933 1 H_PROCHOT_R# COMP1 BCLK_ITP DDR_RST_GATE# 1
2 68R2-GP R905 49D9R2F-GP
BCLK_ITP# AT30 2
CLARKSFIELD
1 2 H_COMP0 AT26 R937 10KR2J-3-GP
COMP0
1
R906 49D9R2F-GP E16 PEG_CLK_R 1 4 RN903
PEG_CLK CLK_EXP_P [23]
D16 PEG_CLK#_R 2 3 SRN0J-6-GP R934
PEG_CLK# CLK_EXP_N [23] DY
D D
G
Do Not Stuff TP901 1 SKTOCC#_R AH24 Do Not Stuff
SKTOCC# DPLL_REF_SSCLK_R RN904 Q901
DPLL_REF_SSCLK A18 2 3 CLK_DP_P [23]
1
A17 DPLL_REF_SSCLK#_R 1 4 SRN0J-6-GP Do Not Stuff
CLK_DP_N [23]
2
H_CATERR# DPLL_REF_SSCLK#
AK14 CATERR#
THERMAL
D
2 3
+1.05V_VTT
DY DDR3_DRAMRST# [18,19]
F6 SM_DRAMRST# Vgs(th)<=1.5V
SM_DRAMRST# RN905
[25] H_PECI AT15 PECI
AL1 SM_RCOMP_0 4 1
R936 SM_RCOMP0 SM_RCOMP_1 SM_DRAMRST#
AM1 3 2 1 2
Do Not Stuff SM_RCOMP1
AN1 SM_RCOMP_2 R935 DY
H_PROCHOT_R# SM_RCOMP2 SRN10KJ-5-GP R988
1
[47] H_PROCHOT# DY 2 AN26 PROCHOT#
AN15 PM_EXTTS#0_C 1 4 PM_EXTTS#0 [18]
1 2
Do Not Stuff
PM_EXT_TS#0 PM_EXTTS#1_C
PM_EXT_TS#1 AP15 2 3 PM_EXTTS#1 [19] 0R2J-2-GP
0611
RN906
DDR3
MISC
[25,37,42] H_THRMTRIP# AK15 THERMTRIP# SRN0J-6-GP
Check
PRDY# AT28 DDR3 Compensation Signals
PREQ# AP27
SM_RCOMP_0 R907 1 2 100R2F-L1-GP-U
TCK AN28 R923
Do Not Stuff TP902 1 TP_RESET_OBS# AP26 RESET_OBS# TMS AP28 SM_RCOMP_1 R910 1 2 24D9R2F-L-GP
PWR MANAGEMENT
AT27 XDP_TRST# 1 2
TRST# SM_RCOMP_2 R911 1 2 130R2F-1-GP
JTAG & BPM

[22] H_PM_SYNC AL15 PM_SYNC TDI AT29
XDP_TDO_R 51R2J-2-GP
TDO AR27
AR29 TDI_M 1 R908 2
TDI_M TDO_M 0R2J-2-GP
AN14 VCCPWRGOOD_1 TDO_M AP29
C DBR# AN25 H_DBR#_R 1
R909
2 XDP_DBRESET# [22]
Calpella Platform S3 Power Reduction Platform C
[25,42] H_PWRGOOD
H_PWRGOOD AN27 S3 Power Reduction CRB Implementation
VCCPWRGOOD_0 0R2J-2-GP Design Details
BPM#0 AJ22 Revision 0.1
[22] PM_DRAM_PWRGD AK13 SM_DRAMPWROK BPM#1 AK22
BPM#2 AK24
BPM#3 AJ24
[49] H_VTTPWRGD AM15 VTTPWRGOOD BPM#4 AJ25
AH22
DW
BPM#5 07/07 Added
BPM#6 AK23
1.Added discharge circuit
Do Not Stuff TP903 1 TP_TAPPWRGOOD AM26 TAPPWRGOOD BPM#7 AH23
R913
1 2 PLT_RST#_R AL14 +1.05V_VTT
[21,34,36,37,64,70,76,80] PLT_RST# RSTIN#
1
1K6R2F-GP
R915
R928
750R2F-GP CLARKUNF
XDP_TDO_R
Check 2 1
2
+3.3V_ALW
51R2J-2-GP
+1.5V_CPU
R989 1 2 10KR2J-3-GP
1
R919
U927 1K27R2F-L-GP
U927_B 1
B Remove XDP function for layout concern B
5 R977 B
2
VCC Do Not Stuff
[37,49,52] VTT_PWRGD 2 A
4 VTT_PWRGD_R3 2 1 PM_DRAM_PWRGD
3
Y DY
GND
1
R920
74LVC1G08GW-1-GP 3KR2F-GP
2
A 1st Samsung
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
Vostro Calpella X00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
CPU1D 4 OF 9
CPU1C 3 OF 9
SB_CK0 W8 M_CLK_DDR2 [19]

M_B_DQ[63..0] W9
[19] M_B_DQ[63..0] M_CLK_DDR#2 [19]
CLARKSFIELD
M_B_DQ0 SB_CK#0
SA_CK0 AA6 M_CLK_DDR0 [18] B5 SB_DQ0 SB_CKE0 M3 M_CKE2 [19]
AA7 M_CLK_DDR#0 [18] M_B_DQ1 A5
SA_CK#0 SB_DQ1
CLARKSFIELD
M_A_DQ[63..0] P7 M_B_DQ2 C3
[18] M_A_DQ[63..0] SA_CKE0 M_CKE0 [18] SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7 M_CLK_DDR3 [19]
M_A_DQ1 SA_DQ0 M_B_DQ4 SB_DQ3 SB_CK1
D C10 SA_DQ1 E4 SB_DQ4 SB_CK#1 V6 M_CLK_DDR#3 [19] D
M_A_DQ2 C7 M_B_DQ5 A6 M2 M_CKE3 [19]
M_A_DQ3 SA_DQ2 M_B_DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 [18] A4 SB_DQ6
M_A_DQ4 B10 Y5 M_CLK_DDR#1 [18] M_B_DQ7 C4
M_A_DQ5 SA_DQ4 SA_CK#1 M_B_DQ8 SB_DQ7
D10 SA_DQ5 SA_CKE1 P6 M_CKE1 [18] D1 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 SA_DQ7 F2 SB_DQ10 SB_CS#0 AB8 M_CS2# [19]
M_A_DQ8 D8 M_B_DQ11 F1 AD6 M_CS3# [19]
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS#1
F10 SA_DQ9 SA_CS#0 AE2 M_CS0# [18] C2 SB_DQ12
M_A_DQ10 E6 AE8 M_CS1# [18] M_B_DQ13 F5
M_A_DQ11 SA_DQ10 SA_CS#1 M_B_DQ14 SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M_A_DQ12 E9 M_B_DQ15 G4 AC7 M_ODT2 [19]
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 SA_DQ13 H6 SB_DQ16 SB_ODT1 AD1 M_ODT3 [19]
M_A_DQ14 E7 AD8 M_ODT0 [18] M_B_DQ17 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 SA_DQ15 SA_ODT1 AF9 M_ODT1 [18] J6 SB_DQ18
M_A_DQ16 H10 M_B_DQ19 J3
G8 SA_DQ17 G1 SB_DQ20
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 SA_DQ19 J2 SB_DQ22 SB_DM1 E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 SA_DQ21 J5 SB_DQ24 SB_DM3 K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0] [19]
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0] [19]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 SA_DQ27 SA_DM5 AM7 M_A_DM[7..0] [18] M4 SB_DQ30
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ31 N5 M_B_DQS[7..0] [19]
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 SA_DQ29 SA_DM7 AN13 M_A_DQS#[7..0] [18] AF3 SB_DQ32
C M_A_DQ30 N8 M_B_DQ33 AG1 M_B_A[15..0] [19]
C
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 SA_DQ31 AJ3 SB_DQ34 SB_DQS#0 D5
M_A_DQ32 AH5 M_A_DQS[7..0] [18] M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ33 SA_DQ32 M_B_DQ36 SB_DQ35 SB_DQS#1 M_B_DQS#2
AF5 SA_DQ33 AG4 SB_DQ36 SB_DQS#2 J4
M_A_DQ34 AK6 C9 M_A_DQS#0 M_A_A[15..0] [18] M_B_DQ37 AG3 L4 M_B_DQS#3
M_A_DQ35 SA_DQ34 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#3 M_B_DQS#4
AK7 SA_DQ35 SA_DQS#1 F8 AJ4 SB_DQ38 SB_DQS#4 AH2
M_A_DQ36 AF6 J9 M_A_DQS#2 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ36 SA_DQS#2 SB_DQ39 SB_DQS#5
DDR SYSTEM MEMORY A
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

SA_DQ37 SA_DQS#3 SB_DQ40 SB_DQS#6
DDR SYSTEM MEMORY - B

M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ41 AK4 AR8 M_B_DQS#7
M_A_DQ39 SA_DQ38 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#7
AJ6 SA_DQ39 SA_DQS#5 AK9 AM6 SB_DQ42
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 SA_DQ41 SA_DQS#7 AT13 AK5 SB_DQ44
M_A_DQ42 AL10 M_B_DQ45 AK2
AK12 SA_DQ43 AM4 SB_DQ46
M_A_DQ44 AK8 M_B_DQ47 AM3
M_A_DQ45 SA_DQ44 M_B_DQ48 SB_DQ47 M_B_DQS0
AL7 SA_DQ45 AP3 SB_DQ48 SB_DQS0 C5
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ49 AN5 E3 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 SA_DQ47 SA_DQS1 F9 AT4 SB_DQ50 SB_DQS2 H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
AM10 SA_DQ49 SA_DQS3 M9 AN4 SB_DQ52 SB_DQS4 AG2
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ53 AN3 AL5 M_B_DQS5
AL11 SA_DQ51 SA_DQS5 AK10 AT5 SB_DQ54 SB_DQS6 AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M_A_DQ54 AT11 M_B_DQ57 AP6
AP12 SA_DQ55 AP8 SB_DQ58
M_A_DQ56 AM12 M_B_DQ59 AT9
AN12 SA_DQ57 AT7 SB_DQ60
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ61 AP9
B M_A_DQ59 SA_DQ58 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 B
AT14 SA_DQ59 SA_MA1 W1 AR10 SB_DQ62
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 SA_DQ61 SA_MA3 AA3 SB_MA1 V2
M_A_DQ62 AR14 V1 M_A_A4 T5 M_B_A2
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 SA_DQ63 SA_MA5 AA9 SB_MA3 V3
V8 M_A_A6 R1 M_B_A4
SA_MA6 M_A_A7 SB_MA4 M_B_A5
SA_MA7 T1 [19] M_B_BS0 AB1 SB_BS0 SB_MA5 T8
Y9 M_A_A8 [19] M_B_BS1 W5 R2 M_B_A6
SA_MA8 M_A_A9 SB_BS1 SB_MA6 M_B_A7
[18] M_A_BS0 AC3 SA_BS0 SA_MA9 U6 [19] M_B_BS2 R7 SB_BS2 SB_MA7 R6
[18] M_A_BS1 AB2 AD4 M_A_A10 R4 M_B_A8
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
[18] M_A_BS2 U7 SA_BS2 SA_MA11 T2 SB_MA9 R5
U3 M_A_A12 [19] M_B_CAS# AC5 AB5 M_B_A10
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
SA_MA13 AG8 [19] M_B_RAS# Y7 SB_RAS# SB_MA11 P3
T3 M_A_A14 [19] M_B_WE# AC6 R3 M_B_A12
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
[18] M_A_CAS# AE1 SA_CAS# SA_MA15 V9 SB_MA13 AF7
[18] M_A_RAS# AB3 P5 M_B_A14
SA_RAS# SB_MA14 M_B_A15
[18] M_A_WE# AE9 SA_WE# SB_MA15 N1
CLARKUNF
A CLARKUNF 1st Samsung A
Wistron Corporation
Title
CPU (DDR)
5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
10 of 88
X00
5 4 3 2 1
CPU1E 5 OF 9
AJ13
RSVD#AJ13
D AJ12 D
RSVD#AJ12
AP25
RSVD#AP25
CLARKSFIELD
AL25 AH25
RSVD#AL25 RSVD#AH25
AL24 AK26
RSVD#AL24 RSVD#AK26
AL22
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF_37
M27
CFG0 RSVD#M27
L28 AJ26
TP1116 SA_DIMM_VREF# RSVD#L28 RSVD#AJ26
PCI-Express Configuration Select 1 J17
SA_DIMM_VREF RSVD#AJ27
AJ27
1
TP1117 1 SB_DIMM_VREF# H17

R1101 SB_DIMM_VREF
G25
Do Not Stuff RSVD#G25
DY 1:Single PEG G17
RSVD#G17
CFG0 0:Bifurcation enabled E31
RSVD#E31
E30
2
RSVD#E30
AL28
CFG0 RSVD#AL28
AM30 AL29
CFG0 RSVD#AL29
改5%
DIS改 AM28
AP31
CFG1 RSVD#AP30
AP30
AP32
CFG3 CFG2 RSVD#AP32
AL32 AL27
CFG3 CFG4 CFG3 RSVD#AL27
AL30 AT31
CFG4 RSVD#AT31
CFG3 - PCI-Express Static Lane Reversal AM31
CFG5 RSVD#AT32
AT32
1
AN29 AP33
R1102 CFG6 RSVD#AP33
AM32 AR33
3KR2F-GP CFG7 RSVD#AR33
1 :Normal Operation AK32
CFG8
CFG3 AK31
RESERVED
0 :Lane Numbers Reversed AK28
CFG9
C C
2
15 -> 0, 14 -> 1, ... CFG10

AJ28
CFG11
AN30 AR32
CFG12 RSVD#AR32
AN32
CFG13
AJ32
CFG14
DW AJ29
AJ30
CFG15 RSVD_TP#E15
E15
F15
07/10 Reversal CFG16 RSVD_TP#F15
AK30 A2
1.PCI-Express Static Lane Reversal CFG17 KEY
H16 D15
RSVD_TP_86 RSVD#D15
C15
RSVD#C15 TP_RSVD64_R TP1121 Do Not Stuff
AJ15 1
RSVD#AJ15 TP_RSVD65_R TP1122 Do Not Stuff
AH15 1
CFG4 RSVD#AH15
CFG4 - Display Port Presence B19
1
RSVD#B19
A19
R1103 RSVD#A19
Do Not Stuff 1:Disabled; No Physical Display Port Do Not Stuff TP1119 TP_H_RSVD17_R A20
DY CFG4 Do Not Stuff TP1120
1
1 TP_H_RSVD18_R B20 RSVD#A20
attached to Embedded Display Port RSVD#B20
AA5
2
0:Enabled; An external Display Port SA_CK2

U9 AA4
RSVD#U9 SA_CK#2
device is connected to the Embedded T9
RSVD#T9 SA_CKE2
R8
AD3
Display Port AC9
SA_CS#2
AD2
RSVD#AC9 SA_ODT2
AB9 AA2
RSVD#AB9 SA_CK3
AA1
SA_CK#3
R9
SA_CKE3
AG7
SA_CS#3
AE3
SA_ODT3
Calpella Platform Design Guide
Revision 1.6 V4
SB_CK2
V5
SB_CK#2
4.8.3.1 LVDS Switching SB_CKE2
N2
B J29 AD5 B
RSVD#J29 SB_CS#2
Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the J28
RSVD#J28 SB_ODT2
AD7
W3
OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap SB_CK3
W2
SB_CK#3
(CFG[4]) to disabled (not pulled down). SB_CKE3
N3
AE5
SB_CS#3
4.8.3.2 eDP Switching SB_ODT3
AD9
eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for
AP34
embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail VSS
through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP
strap CFG[4] as no connect. Page 482,486
CLARKUNF
DW
07/02 Added
CFG7(Reserved) - Temporarily used for early 1.Added display Switchable strap commentariat
Clarksfield samples.
CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample

(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
DW30 Only support Arrandale, the pull-down resistor shouble be used. Does
A
CFG7 no need pull down not impact AUB functionality. A
1st Samsung
Wistron Corporation
Title
CPU (RESERVED)
www.vinafix.vn
Vostro Calpella X00

5 4 3 2 1
5 4 3 2 1
CPU1F 6 OF 9
+VCC_CORE
18A
CLARKSFIELD
+1.05V_VTT
PROCESSOR CORE POWER
AG35 AH14
VCC VTT0
AG34 AH12
1
VCC VTT0 C1216 C1201 C1202 C1217 C1218 C1203 C1219 C1204 C1205
AG33 AH11
+VCC_CORE 48A (Arburdale) AG32
VCC
VCC
VTT0
VTT0
AH10
DY DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Do Not Stuff
Do Not Stuff
AG31 J14
2
VCC VTT0
D AG30 J13 D
VCC VTT0
AG29 H14
C1206 C1207 C1208 C1209 C1220 C1210 VCC VTT0
AG28 H12
VCC VTT0
1
1
AG27 G14
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AG26 G13
VCC VTT0
AF35 G12
2
2
VCC VTT0
AF34 G11
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0 +1.05V_VTT
AF31 F12
VCC VTT0
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14
C1211 C1221 C1222
The decoupling capacitors, filter
AF28 E12
VCC VTT0 recommendations and sense resistors on the
1
AF27 D14
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AF26
VCC VTT0
D13 CPU/PCH Rails are specific to the CRB
1.1V RAIL POWER

C1212 C1213 C1214 C1215 C1223 C1224 AD35 D12
2
VCC VTT0 Implementation. Customers need to follow the
1
1 AD34 D11
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AD33
VCC VTT0
C14 recommendations in the Calpella Platform
AD32 C13
2
AD31
VCC VTT0
C12 Design Guide.
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
VCC VTT0
AD26 A13
VCC VTT0
AC35 A12
VCC VTT0
AC34 A11
VCC VTT0
AC33
C1225 C1226 C1227 C1228 C1229 C1230 C1231 C1232 VCC +1.05V_VTT
AC32
VCC
1
AC31
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AC30 AF10
VCC VTT0
AC29 AE10
2
VCC VTT0 C1233 C1234

AC28 AC10
VCC VTT0
1
CPU CORE SUPPLY
C AC27 AB10 C
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AC26 Y10
VCC VTT0
AA35 W10
2
VCC VTT0
AA34 U10
VCC VTT0
AA33 T10
VCC VTT0
AA32 J12
VCC VTT0
AA31 J11
VCC VTT0
AA30 J16
C1235 C1236 C1237 C1238 C1239 C1240 C1241 C1242 VCC VTT0
AA29 J15
1
VCC VTT0
AA28
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AA27
VCC
AA26
2
VCC
Y35
Y34
VCC Please note that the VTT Rail
VCC
Y33
Y32
VCC Values are
VCC
Y31
VCC Arrandale VTT=1.05V;
Y30
VCC
Y29
VCC Clarksfield VTT=1.1V
Y28
VCC
Y27
C1243 VCC
Y26
1
VCC
V35 AN33 PSI# [47]
VCC PSI#
Do Not Stuff
DY V34
V33
VCC
CPU_VID[6..0] [47]
2
VCC CPU_VID0
V32 AK35
VCC VID
V31
V30
V29
VCC
VCC
POWER VID
VID
AK33
AK34
AL35
CPU_VID1
CPU_VID2
CPU_VID3
VCC VID
V28
VCC CPU VIDS VID
AL33 CPU_VID4
SA
V27 AM33 CPU_VID5
VCC VID CPU_VID6 07/01 Check
V26 AM35
VCC VID 1.DPRSLPVR ??
U35 AM34 PM_DPRSLPVR [47]
VCC PROC_DPRSLPVR
B U34 B
VCC
U33
VCC
U32
VCC TP_H_VTTVID1
U31 G15 1
VCC VTT_SELECT TP1203 Do Not Stuff
U30
VCC
U29
VCC H_VTTVID1 = Low, 1.1V
U28
U27
VCC H_VTTVID1 = High, 1.05V
VCC +VCC_CORE
U26
VCC
R35
VCC
R34
1
VCC
R33
VCC R1201
R32 AN35 IMVP_IMON [47]
VCC ISENSE 100R2F-L1-GP-U
R31
VCC
R30
VCC
R29
2
VCC VCC_SENSE
SENSE LINES
R28 AJ34 VCC_SENSE [47]

VCC VCC_SENSE VSS_SENSE
R27 AJ35 VSS_SENSE [47]
VCC VSS_SENSE
R26
1
VCC
P35
VCC R1204
P34 B15 VTT_SENSE [49]
VCC VTT_SENSE TP_VSS_SENSE_VTT 1 100R2F-L1-GP-U
P33 A15
VCC VSS_SENSE_VTT TP1202
P32
VCC Do Not Stuff
P31
2
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
A A
1st Samsung
CLARKUNF
Wistron Corporation
Title
CPU (VCC_CORE)
www.vinafix.vn
Vostro Calpella X00

5 4 3 2 1
5 4 3 2 1
+1.5V_CPU +1.5V_CPU +1.5V_CPU +1.5V_CPU
1
DYC1376 DYC1377 DYC1378 DYC1379
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
2
+CPU_GFXCORE
+1.5V_SUS +1.5V_SUS +1.5V_SUS +1.5V_SUS
22A CPU1G 7 OF 9
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.pdf"
AT21 document.
VAXG
D AT19 VAXG VAXG_SENSE AR22 VCC_AXG_SENSE [53] D
SENSE
LINES
AT18 VAXG VSSAXG_SENSE AT22 VSS_AXG_SENSE [53]
TC1303 C1324 C1327 C1326 C1329 C1328 C1325 C1323 C1330 AT16 VAXG
CLARKSFIELD
1
1
AR21 VAXG
Do Not Stuff
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
Do Not Stuff
Do Not Stuff
SC10U6D3V5MX-3GP
Do Not Stuff
SC10U6D3V5MX-3GP
Do Not Stuff
DY DY DY DY DY AR19
AR18
VAXG
2
VAXG
AR16 VAXG GFX_VID AM22 GFX_VID0 [53]
AP21 VAXG GFX_VID AP22 GFX_VID1 [53]
GRAPHICS VIDs
AP19 VAXG GFX_VID AN22 GFX_VID2 [53]
AP18 VAXG GFX_VID AP23 GFX_VID3 [53]
AP16 VAXG GFX_VID AM23 GFX_VID4 [53]
AN21 VAXG GFX_VID AP24 GFX_VID5 [53]
GRAPHICS
AN19 VAXG GFX_VID AN24 GFX_VID6 [53]
AN18 VAXG
AN16 VAXG
AM21 VAXG GFX_VR_EN AR25 GFX_VR_EN [53]
AM19 AT25 TP_GFX_DPRSLPVR 1 TP1303Do Not Stuff
VAXG GFX_DPRSLPVR
AM18 VAXG GFX_IMON AM24 GFX_IMON [53]
AM16 VAXG
AL21 VAXG For no use switch graphic function
AL19 VAXG
AL18 +1.5V_CPU
AL16
AK21
VAXG
VAXG
AJ1
3A
VAXG VDDQ
AK19 VAXG VDDQ AF1
1
AK18 AE7 C1301 C1302 C1303 C1304 C1305 C1306 C1307
- 1.5V RAILS
VAXG VDDQ
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AK16 AE4 TC1301
VAXG VDDQ SE330U2D5VDM-2GP
AJ21 AC1
2
VAXG VDDQ
AJ19 VAXG VDDQ AB7
C AJ18 AB4 C
VAXG VDDQ
AJ16 VAXG VDDQ Y1
AH21 VAXG VDDQ W7
AH19 VAXG VDDQ W4
AH18 VAXG VDDQ U1
AH16 T7
POWER
VAXG VDDQ
VDDQ T4
VDDQ P1
VDDQ N7
+1.05V_VTT N4
VDDQ
DDR3
VDDQ L1
J24 VTT1 VDDQ H1
FDI
J23 VTT1
H25 VTT1
1
C1308 C1309 +1.05V_VTT

SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
P10
2
VTT0
VTT0 N10
1
L10 C1310 C1311
VTT0 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
VTT0 K10
2
+1.05V_VTT
+1.05V_VTT
18A
1.1V
VTT1 J22
K26 VTT1 VTT1 J20
1
J27 J18 C1316 C1317
VTT1 VTT1
PEG & DMI

J26 H21 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
VTT1 VTT1
1
C1312 C1313 C1314 C1315 J25 H20
2
B VTT1 VTT1 B
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
H27 VTT1 VTT1 H19

G28
2
VTT1
G27 VTT1
G26 +1.8V_RUN
F26
E26
VTT1
VTT1
L26
1.35A
VTT1 VCCPLL
1.8V
E25 VTT1 VCCPLL L27
1
M26 C1318 C1319 C1320 C1321 C1322
VCCPLL
SC1U25V5KX-1GP
SC1U25V5KX-1GP
SC4D7U6D3V5KX-3GP
SC2D2U10V3KX-1GP
SC10U6D3V5MX-3GP
2
CLARKUNF
A 1st Samsung A
Wistron Corporation
Title
Size Document Number

CPU (VCC_GFXCORE) Rev
5 4
www.vinafix.vn 3 2
Date: Wednesday, September 02, 2009
Vostro Calpella
Sheet
1
13 of 88
X00
5 4 3 2 1
CPU1H 8 OF 9 CPU1I 9 OF 9
AT20 VSS VSS AE34

AT17 VSS VSS AE33
AR31 VSS VSS AE32 K27 VSS
CLARKSFIELD
CLARKSFIELD
D AR23 VSS VSS AE28 J32 VSS D
AR20 VSS VSS AE27 J30 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AP20 VSS VSS AB35 H24 VSS
AN34 VSS VSS AB28 H5 VSS
AN31 VSS VSS AB27 H2 VSS
AN23 VSS VSS AB26 G34 VSS
AN20 VSS VSS AB6 G31 VSS
AN17 VSS VSS AA10 G20 VSS
AM29 VSS VSS Y8 G9 VSS
AM20 VSS VSS W35 F30 VSS
C AM2 W29 E35 C
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS
AK27 VSS VSS T33 D33 VSS
AK25 VSS VSS T32 D30 VSS VSS_NCTF AR34
AK20 VSS VSS T31 D26 VSS VSS_NCTF B34
AK17 T30 D9 B2
NCTF
VSS VSS VSS VSS_NCTF
AJ31 VSS VSS T29 D6 VSS
AJ23 T28 D3
VSS VSS VSS For layout request
A35,AT1,AT35,B1,A3,A33,A34,
AJ20 T27 C34 A35
AP1,AP35,AR1,AR35,AT2,AT3,
VSS VSS VSS VSS_NCTF#A35
AJ17 VSS VSS T26 C32 VSS VSS_NCTF#AT1 AT1
AJ14 VSS VSS T6 C29 VSS VSS_NCTF#AT35 AT35
AJ11 VSS VSS R10 C28 VSS VSS_NCTF#B1 B1
AJ8 P8 C24 A3 TP_MCP_VSS_NCTF4 1 TP1405
AT33,AT34,C1,C35,B35
VSS VSS VSS RSVD_NCTF#A3
AJ5 VSS VSS P4 C22 VSS RSVD_NCTF#A33 A33
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#A34 A34
AH35 VSS VSS N35 C19 VSS RSVD_NCTF#AP1 AP1
AH34 VSS VSS N34 C16 VSS RSVD_NCTF#AP35 AP35
NCYF TEST PIN:

AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AR1 AR1
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#AR35 AR35
AH31 VSS VSS N31 B21 VSS RSVD_NCTF#AT2 AT2
B TP_MCP_VSS_NCTF1 TP1401 B
AH30 VSS VSS N30 B18 VSS RSVD_NCTF#AT3 AT3 1
AH29 N29 B17 AT33 TP_MCP_VSS_NCTF3 1 TP1406
VSS VSS VSS RSVD_NCTF#AT33
AH28 VSS VSS N28 B13 VSS RSVD_NCTF#AT34 AT34
AH27 VSS VSS N27 B11 VSS RSVD_NCTF#C1 C1
AH26 VSS VSS N26 B8 VSS RSVD_NCTF#C35 C35
AH20 N6 B6 B35 TP_MCP_VSS_NCTF2 1 TP1402
VSS VSS VSS RSVD_NCTF#B35
AH17 VSS VSS M10 B4 VSS
AH13 VSS VSS L35 A29 VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 VSS VSS K34
AF2 VSS VSS K33
AE35 VSS VSS K30
CLARKUNF CLARKUNF
A 1st Samsung A
Wistron Corporation
Title
CPU (VSS)
5 4
www.vinafix.vn 3 2
Vostro Calpella
Sheet
1
14 of 88
X00
5 4 3 2 1
D D
C C
(Blanking)
B B
A 1st Samsung A
Wistron Corporation
Title
Reserved
www.vinafix.vn
A3
Vostro Calpella X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A 1st Samsung A
Wistron Corporation
Title
Reserved
www.vinafix.vn
A3
Vostro Calpella X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
DM1
D SSID = MEMORY M_A_A0

M_A_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
D
M_A_A2 96
M_A_A3 A2
95 110 M_A_RAS# [10]
M_A_A4 A3 RAS#
92 A4 WE# 113 M_A_WE# [10]
M_A_A5 91 115 M_A_CAS# [10]
M_A_A6 A5 CAS#
90
M_A_A7 A6
86 A7 CS0# 114 M_CS0# [10]
M_A_A8 89 121 M_CS1# [10]
[10] M_A_DQS#[7..0] A8 CS1#
M_A_A9 85
M_A_A10 A9
[10] M_A_DQ[63..0] 107 A10/AP CKE0 73 M_CKE0 [10]
M_A_A11 84 74 M_CKE1 [10]
M_A_A12 A11 CKE1
[10] M_A_DM[7..0] 83
M_A_A13 A12 M_CLK_DDR0
119 A13 CK0 101 M_CLK_DDR0 [10]
M_A_A14 80 103 M_CLK_DDR#0 M_CLK_DDR#0 [10] SA0_DM1
[10] M_A_DQS[7..0] A14 CK0#
M_A_A15 78 SA1_DM1
M_A_BS2 A15 M_CLK_DDR1
[10] M_A_A[15..0] 79 102 M_CLK_DDR1 [10]
[10] M_A_BS2 A16/BA2 CK1 M_CLK_DDR#1
104 M_CLK_DDR#1 [10]
CK1#
1
M_A_BS0 109
[10] M_A_BS0 M_A_BS1 BA0 M_A_DM0 R1802 R1801
108 11
[10] M_A_BS1 BA1 DM0 M_A_DM1 10KR2J-3-GP 10KR2J-3-GP
28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
2
15 136
17 153
4 170
M_A_DQ6
6
16
DQ5
DQ6
DM7 187
SMBUS address:A0
M_A_DQ7 18 200 PCH_SMBDATA
DQ7 SDA PCH_SMBDATA [7,19,23,40,64,76]
M_A_DQ8 PCH_SMBCLK
M_A_DQ9
21
23
DQ8 SCL 202 PCH_SMBCLK [7,19,23,40,64,76] DW
M_A_DQ10 DQ9 07/02 Reserve
33 198 PM_EXTTS#0 [9]
M_A_DQ11 DQ10 EVENT# +3.3V_RUN 1.Added SA0_DM1 pull-up resistor
35 DQ11
M_A_DQ12 07/07
Layout Note: 22
DQ12 VDDSPD
199 2.Reserve pull-hi,lo resistor
M_A_DQ13 24
+1.5V_SUS Place near DM1 M_A_DQ14 34
DQ13
197 SA0_DM1
DQ14 SA0
1
M_A_DQ15 36 201 SA1_DM1
M_A_DQ16 DQ15 SA1
39
C
DQ16 DY C
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
ST330U2D5VBM-1-GP M_A_DQ17 41 77
2
DQ17 NC#1
1
M_A_DQ18 51 122
DQ18 NC#2
1
+1.5V_SUS
TC1803
C1803
C1804
C1812
C1802
C1811
C1816
M_A_DQ19 53 125
M_A_DQ20 DQ19 NC#/TEST
40
2
M_A_DQ21 DQ20
42 75
2
M_A_DQ22 DQ21 VDD1

50 76
M_A_DQ23 DQ22 VDD2 C1806 C1807
52 DQ23 VDD3 81
M_A_DQ24 57 82 SCD1U16V2KX-3GP Do Not Stuff
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
67 DQ26 VDD6 88
M_A_DQ27 69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_A_DQ30 68 100
M_A_DQ31 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111
DQ33 VDD13
Height 5.2mm
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD14
143 117
M_A_DQ36 DQ35 VDD15
Layout Note: Layout Note: 130
DQ36 VDD16
118
M_A_DQ37 132 123
Put close to VTT1,VTT2. Put between two SO-DIMM M_A_DQ38 140
DQ37 VDD17
124
+0.75V_DDR_VTT M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
DQ41 VSS
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
M_A_DQ42 157 8
DQ42 VSS
1
M_A_DQ43 159 9
DQ43 VSS
C1814
C1813
C1815
C1801
C1823
M_A_DQ44 146 13
M_A_DQ45 DQ44 VSS
148 14
2
M_A_DQ46 DQ45 VSS

158
DQ46 VSS
19 put near connector
M_A_DQ47 160 20
M_A_DQ48 DQ47 VSS M_CLK_DDR0
163 DQ48 VSS 25
M_A_DQ49 165 26 M_CLK_DDR#0
M_A_DQ50 DQ49 VSS M_CLK_DDR1
175 31
M_A_DQ51 DQ50 VSS M_CLK_DDR#1
DG: 177 DQ51 VSS 32
M_A_DQ52 164 37
B 1uF*4 (per SO-DIMM) M_A_DQ53 166
DQ52 VSS
38 B
M_A_DQ54 DQ53 VSS
10uF*3 (two close to VR and one between the two SO-DIMM) 174 DQ54 VSS 43
M_A_DQ55 176 44
DQ55 VSS
1
M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
183 49
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DQ57 VSS
C1821
C1819
C1820
C1818
M_A_DQ58 191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 DQ60 VSS 60
+1.5V_SUS M_A_DQ61 182 61
2
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 DQ63 VSS 66
71
M_A_DQS#0 VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10 72
M_A_DQS#1 DQS0# VSS
SCD1U10V2KX-4GP
27 DQS1# VSS 127

1
M_A_DQS#2 45 128
DQS2# VSS
C1872
C1873
C1874
C1875
M_A_DQS#3 62 133
M_A_DQS#4 DQS3# VSS
135 134
2
M_A_DQS#5 DQS4# VSS

152 138
M_A_DQS#6 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_A_DQS0 VSS
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_A_DQS1
12
DQS0 VSS
150
29 151
pdf" document. M_A_DQS2 DQS1 VSS
47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 DQS5 VSS 162
M_A_DQS6 171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
VSS 172
[10] M_ODT0 M_ODT0 116 173
+V_DDR_REF M_ODT1 ODT0 VSS
[10] M_ODT1 120 178
ODT1 VSS
VSS 179
126 184
VREF_CA VSS
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 185
Do Not Stuff
VREF_DQ VSS
1
VSS 189
C1810
C1817
C1809
30 190
A DY +0.75V_DDR_VTT [9,19] DDR3_DRAMRST# RESET# VSS
195 A
2
VSS
VSS 196
203 205
VTT1 VSS
204 206
VTT2 VSS
1st Samsung
DDR3-204P-47-GP
Wistron Corporation
62.10017.P31 Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn Size Document Number

DDRIII-SODIMM SLOT1 Rev
Custom SA
Vostro Calpella
5 4 3 2 1
5 4 3 2 1
DM2
Change CONN
SSID = MEMORY M_B_A0
M_B_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
2009/06/01
M_B_A2 96
M_B_A3 A2
95 110 M_B_RAS# [10]
M_B_A4 A3 RAS#
92 113 M_B_WE# [10]
M_B_A5 A4 WE#
91 115 M_B_CAS# [10]
M_B_A6 A5 CAS# +3.3V_RUN +3.3V_RUN
90
M_B_A7 A6
86 114 M_CS2# [10]
A7 CS0#
1
M_B_A8 89 121 M_CS3# [10]
A8 CS1#
1
M_B_A9 EC1901
D
[10] M_B_DQS#[7..0]
M_B_A10
85
107
A9
73 M_CKE2 [10] R1903 R1904 DY Do Not Stuff D
2
M_B_A11 A10/AP CKE0 Do Not Stuff 10KR2J-3-GP
[10] M_B_DQ[63..0]
M_B_A12
84
A11 CKE1
74 M_CKE3 [10] DY
83
M_B_A13 A12 M_CLK_DDR2
[10] M_B_DM[7..0] 119 101 M_CLK_DDR2 [10]
2
M_B_A14 A13 CK0 M_CLK_DDR#2 SA1_DM2
80 103 M_CLK_DDR#2 [10]
M_B_A15 A14 CK0# SA0_DM2
[10] M_B_DQS[7..0] 78
M_B_BS2 A15 M_CLK_DDR3
[10] M_B_BS2 79 102 M_CLK_DDR3 [10]
A16/BA2 CK1 M_CLK_DDR#3
[10] M_B_A[15..0] 104 M_CLK_DDR#3 [10]
CK1#
1
M_B_BS0 109
[10] M_B_BS0 BA0 R1901 R1902
M_B_BS1 108 11 M_B_DM0
[10] M_B_BS1 BA1 DM0 M_B_DM1 10KR2J-3-GP
M_B_DQ0 DM1
28
M_B_DM2
DY Do Not Stuff
5 46
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
2
15 136
17 153
4 170
6 187
M_B_DQ6 DQ5 DM7
M_B_DQ7
16
18
DQ6
DQ7 SDA
200 PCH_SMBDATA
PCH_SMBDATA [7,18,23,40,64,76]
SMBUS address:A2
M_B_DQ8 21 202 PCH_SMBCLK
DQ8 SCL PCH_SMBCLK [7,18,23,40,64,76]
Layout Note: M_B_DQ9 23
DQ9 DW
M_B_DQ10 33 198 +3.3V_RUN
+1.5V_SUS Place near DM2 M_B_DQ11 DQ10 EVENT# PM_EXTTS#1 [9]
07/02 Reserve
35
M_B_DQ12 DQ11 1.Added SA1_DM2 pull-down resistor
22 199
M_B_DQ13 DQ12 VDDSPD 07/07
24
M_B_DQ14 DQ13 SA0_DM2 2.Reserve pull-hi,lo resistor
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
ST330U2D5VBM-1-GP
34 197
DQ14 SA0
1
M_B_DQ15 36 201 SA1_DM2
1
1
M_B_DQ16 DQ15 SA1
39
DQ16 DY
C1919
C1905
C1911
C1916
C1913
C1920
TC1903
M_B_DQ17 41 77
2
M_B_DQ18 DQ17 NC#1
51 122
2
2
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1
C 50 76 C
M_B_DQ23 DQ22 VDD2 C1906 C1921
52 81
M_B_DQ24 DQ23 VDD3 SCD1U16V2KX-3GP Do Not Stuff
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
DQ35 VDD15
Layout Note: M_B_DQ36 130
DQ36 VDD16
118
M_B_DQ37 132 123
+0.75V_DDR_VTT Put close to VTT1,VTT2. M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
DQ40 VSS
Height 9.2mm
M_B_DQ41
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
149 3
DQ41 VSS
1
M_B_DQ42 157
DQ42 VSS
8 put near connector
C1908
C1917
C1918
C1909
M_B_DQ43 159 9
M_B_DQ44 DQ43 VSS M_CLK_DDR2
146 13
2
M_B_DQ45 DQ44 VSS M_CLK_DDR#2

148 14
M_B_DQ46 DQ45 VSS M_CLK_DDR3
158 19
M_B_DQ47 DQ46 VSS M_CLK_DDR#3
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
DQ49 VSS
DG: M_B_DQ50 175
DQ50 VSS
31
M_B_DQ51 177 32
1uF*4 (per SO-DIMM) DQ51 VSS
1
M_B_DQ52 164 37
DQ52 VSS
10uF*3 (two close to VR and one between the two SO-DIMM) M_B_DQ53 166 38
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DQ53 VSS
C1901
C1904
C1902
C1903
M_B_DQ54 174 43
M_B_DQ55 DQ54 VSS
B 176 44 B
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
2
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
+1.5V_SUS M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
62 133
M_B_DQS#4 DQS3# VSS
SCD1U10V2KX-4GP
135 134
DQS4# VSS
1
M_B_DQS#5 152 138

DQS5# VSS
C1976
C1977
C1978
C1979
M_B_DQS#6 169 139

M_B_DQS#7 DQS6# VSS
186 144
2
DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_B_DQS4
64
DQS3 VSS
156
137 161
pdf" document. M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
M_ODT2 VSS
[10] M_ODT2 116 173
+V_DDR_REF M_ODT3 ODT0 VSS
[10] M_ODT3 120 178
ODT1 VSS
179
VSS
126 184
VREF_CA VSS
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 185
Do Not Stuff
VREF_DQ VSS
A 189 A
1
VSS
[9,18] DDR3_DRAMRST# 30 190
RESET# VSS
C1907
C1910
C1914
DY +0.75V_DDR_VTT VSS
195
196
1st Samsung
2
VSS
203 205
VTT1 VSS
204
VTT2 VSS
206
Wistron Corporation
DDR3-204P-55-GP
Title
62.10017.Q31
DDRIII-SODIMM SLOT2
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
DW
07/05 LCDVDD_EN_PCH
1. LCD brightness control are separated by GPU,PCH,EC
1
DY 2
2. LCD Power Enable control are separated by GPU,PCH,EC
R2003
3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
07/07 Do Not Stuff
4. Dummy R2003 R2011
0R2J-2-GP
U2001D 4 OF 10
[37] PANEL_BKEN_PCH 1 2PANEL_BKEN_PCHR
T48 L_BKLTEN SDVO_TVCLKINN BJ46
[54] LCDVDD_EN_PCH LCDVDD_EN_PCH T47 BG46
L_VDD_EN SDVO_TVCLKINP
D D
[54] LBKLT_CTL_PCH Y48 L_BKLTCTL SDVO_STALLN BJ48
SDVO_STALLP BG48
[54] L_DDC_CLK AB48 L_DDC_CLK
[54] L_DDC_DATA Y45 L_DDC_DATA SDVO_INTN BF45
RN2001 BH45
LCTLA_CLK SDVO_INTP
+3.3V_RUN 1 4 AB46 L_CTRL_CLK
2 3 LCTLB_DATA V48 L_CTRL_DATA
SRN10KJ-5-GP LIBG AP39 T51
Do Not Stuff TP2001 TP_LVDS_VBG AP41 LVD_IBG SDVO_CTRLCLK
1 LVD_VBG SDVO_CTRLDATA T53
Place near PCH
1
AT43 LVD_VREFH
R2002 AT42 BG44
2K37R2F-GP LVD_VREFL DDPB_AUXN
DDPB_AUXP BJ44
DDPB_HPD AU38
LVDS
[74] MCH_LVDSA_CLK# AV53
2
LVDSA_CLK#
[74] MCH_LVDSA_CLK AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
[74] MCH_LVDSA_DAT0# BB47 LVDSA_DATA#0 DDPB_1N BJ42
[74] MCH_LVDSA_DAT1# BA52 BG42
Digital Display Interface

LVDSA_DATA#1 DDPB_1P
[74] MCH_LVDSA_DAT2# AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
[74] MCH_LVDSA_DAT0 BB48 LVDSA_DATA0 DDPB_3P BA38
[74] MCH_LVDSA_DAT1 BA50 LVDSA_DATA1
[74] MCH_LVDSA_DAT2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49
C C
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
50 ohm trace to filter
37.5 ohm trace to 150R resistor
[74] MCH_BLUE MCH_BLUE AA52 U50
MCH_GREEN CRT_BLUE DDPD_CTRLCLK
[74] MCH_GREEN AB53 CRT_GREEN DDPD_CTRLDATA U52
[74] MCH_RED MCH_RED AD53 CRT_RED
DDPD_AUXN BC46
2
[55] GMCH_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46

R2007 R2006 R2005 [55] GMCH_DDCDATA V53 AT38
150R2F-1-GP CRT_DDC_DATA DDPD_HPD
150R2F-1-GP 150R2F-1-GP
DDPD_0N BJ40
[74] GMCH_HSYNC Y53 BG40
1
CRT_HSYNC DDPD_0P
[74] GMCH_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38
CRT
DDPD_2N BF37
B B
Place near PCH 1 2 CRT_IREF AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
R2004 BD36
1KR2D-1-GP DDPD_3P
IBEXPEAK-M-GP-NF
A 1st Samsung A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
20 of 88
X00
5 4 3 2 1
RN2101
DW
PCI_DEVSEL# 1 10 07/02 Added U2001E 5 OF 10
+3.3V_RUN 1. using the single buffers for 4 device with
PCI_IRDY# 2 9 DGPU_SEL_BUF_# H40 AY9
PCI_SERR# INT_PIRQD# equivalent capability. AD0 NV_CE#0
3 8 2.Rename PCI_PLTRST# N34 AD1 NV_CE#1 BD1
INT_PIRQC# 4 7 PCI_STOP# C44 AP15
INT_PIRQA# AD2 NV_CE#2
+3.3V_RUN 5 6 A38 AD3 NV_CE#3 BD8
C36 AD4
SRN8K2J-2-GP-U +3.3V_RUN J34 AV9
AD5 NV_DQS0
A40 AD6 NV_DQS1 BG8
1
C2101 D45
SCD1U10V2KX-4GP AD7
E36 AD8 NV_DQ0/NV_IO0 AP7
RN2102 U2101 H48 AP6
2
PCI_PERR# AD9 NV_DQ1/NV_IO1
1 10 +3.3V_RUN B 1 E40 AD10 NV_DQ2/NV_IO2 AT6
D PCI_REQ0# 2 9 INT_PIRQB# 5 C40 AT9 D
PCI_REQ3# PCI_PLOCK# VCC PLTRST#_PCH AD11 NV_DQ3/NV_IO3
3 8 A 2 M48 AD12 NV_DQ4/NV_IO4 BB1
PCI_FRAME# 4 7 PCI_REQ1# [9,34,36,37,64,70,76,80] PLT_RST# 4 Y M45 AD13 NV_DQ5/NV_IO5 AV6 DMI Termination Voltage
+3.3V_RUN 5 6 PCI_TRDY# 3 F53 BB3
GND AD14 NV_DQ6/NV_IO6
M40 AD15 NV_DQ7/NV_IO7 BA4 NV_CLE Set to Vss when low.
SRN8K2J-2-GP-U 74LVC1G08GW-1-GP
NVRAM
M43 AD16 NV_DQ8/NV_IO8 BE4 Set to Vcc when high.
J36 AD17 NV_DQ9/NV_IO9 BB6 Low = Default
1
+3.3V_RUN R2104 DY 2
Do Not Stuff
K48 AD18 NV_DQ10/NV_IO10 BD6
DW F40
C42
AD19 NV_DQ11/NV_IO11 BB7
BC8 unused NV_SLE strap
DGPU_PWM_SELECT# 07/23 SWAP AD20 NV_DQ12/NV_IO12
1 8 K46 AD21 NV_DQ13/NV_IO13 BJ8
PCH_GPIO5 1. Swapped the capacitors from signal to power decoupling
2 7 M51 AD22 NV_DQ14/NV_IO14 BJ6
3 6 PCH_GPIO4 J52 BG6
INT_PIRQE# AD23 NV_DQ15/NV_IO15
4 5 K51 AD24
L34 BD3 TP_NV_ALE 1 TP2124 Do Not Stuff
+3.3V_RUN AD25 NV_ALE TP_NV_CLE TP2125 Do Not Stuff
F42 AD26 NV_CLE AY6 1
RN2103 J40
SRN10KJ-7GP AD27
G46 AD28
1
C2113 F44 AU2 TP_NV_RCOMP 1 TP2130 Do Not Stuff
SCD1U10V2KX-4GP U2103 AD29 NV_RCOMP
M47 AD30
PCI
1 H36 AV7
2
B AD31 NV_RB#
5 VCC
2 DGPU_SEL_BUF_# J50 AY8
A C/BE0# NV_WR#0_RE#
[54,74] DGPU_SELECT# 4 Y G42 C/BE1# NV_WR#1_RE# AY5
GND 3 H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
74LVC1G08GW-1-GP BF5
NV_WE#_CK1
INT_PIRQA# G38 PIRQA# Port 0 for debug port
INT_PIRQB#
C
1
R2107 DY 2
Do Not Stuff INT_PIRQC#
H51
B37
PIRQB#
H18 C
PIRQC# USBP0N USB_PN0 [63]
INT_PIRQD# A44 J18
PIRQD# USBP0P USB_PP0 [63]
USBP1N A18 USB_PN1 [63] USB
PCI_REQ0# F51 C18
REQ0# USBP1P USB_PP1 [63]
PCI_REQ1# A46 REQ1#/GPIO50 USBP2N N20 USB_PN2 [76] Pair Device
DGPU_SEL_BUF_# B45 P20
REQ2#/GPIO52 USBP2P USB_PP2 [76]
PCI_REQ3# M53 REQ3#/GPIO54 USBP3N J20 TP_USB_PN3
TP2122 0 USB1
BOOT BIOS Strap USBP3P L20 TP_USB_PP3
TP2123
Do Not Stuff TP2116 1 PCI_GNT0# F48 GNT0# USBP4N F20 USB_PN4 [64] 1 USB for ESATA
PCI_GNT#0 PCI_GNT#1 BOOT BIOS Location K45 G20 USB_PP4 [64]
GNT1#/GPIO51 USBP4P
[54] DGPU_PWM_SELECT# DGPU_PWM_SELECT# F36 GNT2#/GPIO53 USBP5N A20 USB_PN5 [76] 2 USB2
0 0 LPC R2121 PCI_GNT3# H53 GNT3#/GPIO55 USBP5P C20 USB_PP5 [76]
0R2J-2-GP
USBP6N M22 TP_USB_PN6
TP2118 3 RESERVE
0 1 Reserved [40] HDD_FALL_INT1 1 2 INT_PIRQE# B41 PIRQE#/GPIO2 USBP6P N22 TP_USB_PP6
TP2119
[76] WWAN_RF_EN WWAN_RF_EN K53 PIRQF#/GPIO3 USBP7N B21 TP_USB_PN7
TP2120 4 WLAN
1 0 PCI PCH_GPIO4 A36 PIRQG#/GPIO4 USBP7P D21 TP_USB_PP7
TP2121
PCH_GPIO5 A48 PIRQH#/GPIO5 USBP8N H22 USB_PN8 [73] 5 WWAN
1 1 SPI(Default) USBP8P J22 USB_PP8 [73]
USB
Do Not Stuff TP2108 1 PCIRST# K6 PCIRST# USBP9N E22 USB_PN9 [32] 6 RESERVED
F22 USB_PP9 [32]
USBP9P
PCI_SERR# E44 SERR# USBP10N A22 USB_PN10 [78] 7 RESERVED
PCI_PERR# E50 PERR# USBP10P C22 USB_PP10 [78]
USBP11N G24 USB_PN11 [73] 8 BlUETOOTH
USBP11P H24 USB_PP11 [73]
PCI_IRDY# A42 IRDY# USBP12N L24 USB_PN12 [34] 9 Card Reader
H44 PAR USBP12P M24 USB_PP12 [34]
PCI_DEVSEL# F46 DEVSEL# USBP13N A24 TP_USB_PN13
TP2128 10 Biometric
PCI_FRAME# C46 C24 TP_USB_PP13
FRAME# USBP13P TP2129
B
11 CAMERA B
PCI_PLOCK# D49 PLOCK#
USBRBIAS# B25 USB_RBIAS_PN 1 2 12 New Card
PCI_STOP# D41 STOP#
PCI_TRDY# C48 TRDY# USBRBIAS D25 R2106 13 RESERVED
22D6R2F-L1-GP
Do Not Stuff TP2115 1 PCH_PME# M7 PME# USB_OC#0_1
OC0#/GPIO59 N16 USB_OC#0_1 [22,63]
PLTRST#_PCH D5 J16 USB_OC#2_3 USB_OC#2_3 [76]
PLTRST# OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 F16
R2110 1 Do Not Stuff PCLK_FWH_R USB_OC#6_7
[70]
[23]
PCLK_FWH
CLK_PCI_FB R2108 1
DY 2
2 22R2J-2-GP CLK_PCI_FB_R
N52
P53
CLKOUT_PCI0 OC3#/GPIO42 L16
E14 USB_OC#8_9 Pull up in page 22
R2111 22R2J-2-GP PCLK_KBC_R CLKOUT_PCI1 OC4#/GPIO43 USB_OC#10_11
[37] PCLK_KBC 1 2 P46 G16
R2112 1 2 22R2J-2-GP PCLK_TPM_R P51
CLKOUT_PCI2 OC5#/GPIO9
F12 USB_OC#12_13 for layout convenience
[36] PCLK_TPM CLKOUT_PCI3 OC6#/GPIO10 USB_OC#12_13 [23]
P48 T15 PCH_OC7#
CLKOUT_PCI4 OC7#/GPIO14
IBEXPEAK-M-GP-NF
Calpella Platform Design Guide
A16 swap override Strap/Top-Block Pull up in page 23 for layout convenience
Swap Override jumper Revision 1.6
Table 111. Overcurrent Pin Example Configuration Page 233
PCI_GNT#3 Low = A16 swap
override/Top-Block These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs.
Swap Override enabled The unused USB ports can be left as no connect.
High = Default
A RP2101 1st Samsung A

PCH_OC7# 1 10 +3.3V_ALW
USB_OC#2_3 2 9 PM_RI# PM_RI# [22]
USB_OC#6_7 USB_OC#8_9
R2109 USB_OC#4_5
3
4
8
7 PEG_B_CLKRQ# PEG_B_CLKRQ# [23]
Wistron Corporation
PCI_GNT3# USB_OC#10_11 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
DY 2 +3.3V_ALW 5 6
Do Not Stuff SRN10KJ-L3-GP
Title
PCH (PCI/USB/NVRAM)
5 4
www.vinafix.vn 3 2
Vostro Calpella
Sheet
1
21 of 88
X00
5 4 3 2 1
U2001C 3 OF 10
BA18 FDI_TXN0 FDI_TXN0 [8]
FDI_RXN0 FDI_TXN1 +3.3V_ALW
[8] DMI_CTX_PRXN0 BC24 DMI0RXN FDI_RXN1 BH17 FDI_TXN1 [8]
[8] DMI_CTX_PRXN1 BJ22 BD16 FDI_TXN2 FDI_TXN2 [8]
DMI1RXN FDI_RXN2 FDI_TXN3 RN2201
[8] DMI_CTX_PRXN2 AW20 DMI2RXN FDI_RXN3 BJ16 FDI_TXN3 [8]
[8] DMI_CTX_PRXN3 BJ20 BA16 FDI_TXN4 FDI_TXN4 [8] [21,63] USB_OC#0_1 USB_OC#0_1 3 2
DMI3RXN FDI_RXN4 FDI_TXN5 SUS_PWR_ACK
FDI_RXN5 BE14 FDI_TXN5 [8] 4 1
[8] DMI_CTX_PRXP0 BD24 BA14 FDI_TXN6 FDI_TXN6 [8]
DMI0RXP FDI_RXN6 FDI_TXN7 SRN10KJ-5-GP
[8] DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_TXN7 [8]
D [8] DMI_CTX_PRXP2 BA20 DMI2RXP D
[8] DMI_CTX_PRXP3 BG20 BB18 FDI_TXP0 FDI_TXP0 [8] PM_BATLOW#_R 1 2
DMI3RXP FDI_RXP0 FDI_TXP1 R2201 10KR2J-3-GP
FDI_RXP1 BF17 FDI_TXP1 [8]
[8] DMI_PTX_CRXN0 BE22 BC16 FDI_TXP2 FDI_TXP2 [8] PCIE_WAKE# 1 2
DMI0TXN FDI_RXP2 FDI_TXP3 R2202 1KR2J-1-GP
[8] DMI_PTX_CRXN1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_TXP3 [8]
[8] DMI_PTX_CRXN2 BD20 AW16 FDI_TXP4 FDI_TXP4 [8]
DMI2TXN FDI_RXP4 FDI_TXP5
[8] DMI_PTX_CRXN3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 [8]
BB14 FDI_TXP6 FDI_TXP6 [8] AC_PRESENT_EC 1 2
FDI_RXP6 FDI_TXP7 R2217 10KR2J-3-GP
[8] DMI_PTX_CRXP0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_TXP7 [8]
[8] DMI_PTX_CRXP1 BH21 DMI1TXP
[8] DMI_PTX_CRXP2 BC20 DMI2TXP
[8] DMI_PTX_CRXP3 BD18 BJ14 FDI_INT FDI_INT [8]
DMI3TXP FDI_INT
DMI
FDI
BF13 FDI_FSYNC0 FDI_FSYNC0 [8]
+1.05V_VTT FDI_FSYNC0
BH25 DMI_ZCOMP
R2204 BH13 FDI_FSYNC1 FDI_FSYNC1 [8]
DMI_IRCOMP_R FDI_FSYNC1 R2203
1 2 BF25 DMI_IRCOMP
BJ12 FDI_LSYNC0 FDI_LSYNC0 [8] PM_RSMRST#_R 1 2
49D9R2F-GP FDI_LSYNC0
+3.3V_RUN BG14 FDI_LSYNC1 10KR2J-3-GP
FDI_LSYNC1 FDI_LSYNC1 [8]
1
R2205
Remove XDP 10KR2J-3-GP
DW
pull-up ? 07/02 Modified
1.Modified PM_RSMRST#_R signal to on pull-down resistor connect
[9] XDP_DBRESET# 2 XDP_DBRESET# T6 SYS_RESET# WAKE# J12 PCIE_WAKE# [34,76]

C C
M6 Y1 PM_CLKRUN#
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# [37]
System Power Management

[37] PM_PWROK R2207 1 2 0R2J-2-GP PM_PWRGD B17 PWROK
R2208 1 2 10KR2J-3-GP
TP_SUS_STAT#
K5 MEPWROK SUS_STAT#/GPIO61 P8 1
TP2205Do Not Stuff
Close to PCH
R2209 1 2 10KR2J-3-GP LAN_RST#1 A10 F3 PCH_SUSCLK 1 2 PCH_SUSCLK_2102 [39]
LAN_RST# SUSCLK/GPIO62 R2219 0R2J-2-GP
[9] PM_DRAM_PWRGD PM_DRAM_PWRGD D9 E4 PCH_SLP_S5# 1 1 2 PCH_SUSCLK_KBC [37]

R2210 DRAMPWROK SLP_S5#/GPIO63 TP2202Do Not Stuff R2220 0R2J-2-GP
0R2J-2-GP
[37] RSMRST#_KBC 1 2 PM_RSMRST#_R C16 H7 PM_SLP_S4#_R 1 2 PM_SLP_S4# [34,37,50]
R2218 RSMRST# SLP_S4# R2211 0R2J-2-GP
0R2J-2-GP
[37] SUS_PWR_DN_ACK 1 2 SUS_PWR_ACK M1 P12 PM_SLP_S3#_R 1 2 PM_SLP_S3# [34,37,42,50,51,86]
SUS_PWR_DN_ACK/GPIO30 SLP_S3# R2212 0R2J-2-GP
[37] PM_PWRBTN# 1 2 PM_PWRBTN#_R P5 K8 SIO_SLP_M#_R 1

R2213 0R2J-2-GP PWRBTN# SLP_M# TP2203Do Not Stuff
[37] AC_PRESENT_EC AC_PRESENT_EC 1 2 AC_PRESENT P7 N2 PM_SLP_DSW# 1

R2216 0R2J-2-GP ACPRESENT/GPIO31 TP23 TP2204Do Not Stuff
PM_BATLOW#_R A6 BJ10 H_PM_SYNC

B BATLOW#/GPIO72 PMSYNCH H_PM_SYNC [9] B
[21] PM_RI# PM_RI# F14 F6

RI# SLP_LAN#/GPIO29
IBEXPEAK-M-GP-NF
Pull up in page 23 for layout convenience

DW
07/08 Del
1. Not reserve PCH_GPIO29
2. Not reserve PM_SUS_STAT#
+3.3V_RUN
R2214
PM_CLKRUN# 1 2
1
10KR2J-3-GP
A Option to " Disable " clkrun. R2215
DY 1st Samsung A
Do Not Stuff
Pulling it down will keep the clks running.
Wistron Corporation
2

Title
PCH (DM I/FDI/PM)

5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
22 of 88
X00
5 4 3 2 1
+3.3V_ALW
+3.3V_ALW +3.3V_ALW
R2301
U2001B 2 OF 10 10KR2J-3-GP
1
2
2
1
1
2
BG30 B9 SMBALERT# 2 1 +3.3V_ALW RN2313
PERN1 SMBALERT#/GPIO11 RN2302 RN2306
BJ30 PERP1 SRN2K2J-1-GP
BF29 H14 PCH_SMB_CLK SRN2K2J-1-GP SRN2K2J-1-GP
PETN1 SMBCLK PCH_SMB_CLK [34]
BH29 PETP1
C8 PCH_SMB_DATA
PCH_SMB_DATA [34]
4
3
SMBDATA
D [64] PCIE_IRXN2_MTXN2 AW30 PERN2 R2302 D
3
4
4
3
[64] PCIE_IRXP2_MTXP2 BA30 PERP2
C2318 2 1 SCD1U16V2KX-3GP PCIE_ITXN2_MRXN2_C SML0ALERT# SML0_CLK
[64] PCIE_ITXN2_MRXN2
C2310 2 1 SCD1U16V2KX-3GP
BC30 PETN2
PCIE_ITXP2_MRXP2_C
BD30 PETP2
WLAN SML0ALERT#/GPIO60 J14 2 1 +3.3V_ALW
PCH_SMB_CLK SML1CLK
[64] PCIE_ITXP2_MRXP2
SML0_CLK 10KR2J-3-GP SML0_DATA
AU30 PERN3
SML0CLK C6 Remove XDP PCH_SMB_DATA SML1DAT
SMBus
[76] PCIE_IRXN3_LRTXN3
[76] PCIE_IRXP3_LRTXP3
C2303 2
AT30 PERP3
PCIE_ITXN3_LRXN3_C SML0DATA G8 SML0_DATA pull-up
[76] PCIE_ITXN3_LRXN3 1 SCD1U16V2KX-3GP AU32 PETN3 LAN
[76] PCIE_ITXP3_LRXP3 C2309 2 1 SCD1U16V2KX-3GP PCIE_ITXP3_LRXP3_C
AV32 PETP3 R2303
M14 SML1ALERT# 2 1 +3.3V_ALW
SML1ALERT#/GPIO74
[76] PCIE_IRXN4_MTXN4 BA32 PERN4
[76] PCIE_IRXP4_MTXP4 BB32 PERP4 E10 SML1CLK 10KR2J-3-GP
SML1CLK/GPIO58 SML1CLK [37]
C2302 2 1 SCD1U16V2KX-3GP PCIE_ITXN4_MRXN4_C
[76] PCIE_ITXN4_MRXN4
BD32 PETN4
PCIE_ITXP4_MRXP4_C
BE32 PETP4
WWAN G12 SML1DAT +3.3V_RUN
[76] PCIE_ITXP4_MRXP4 SML1DATA/GPIO75 SML1DAT [37]
PCI-E*
[34] PCIE_IRXN5_NTXN5 BF33 PERN5
CL_CLK +3.3V_ALW RN2303
[34] PCIE_IRXP5_NTXP5
BH33 PERP5
PCIE_ITXN5_NRXN5_C
New CL_CLK1 T13 1
TP2301Do Not Stuff
Controller
[34] PCIE_ITXN5_NRXN5 BG32 PETN5 WD 2 3
1
[34] PCIE_ITXP5_NRXP5 C2304 2 1 SCD1U16V2KX-3GP PCIE_ITXP5_NRXP5_C
BJ32 PETP5 Card CL_DATA1 T11 CL_DATA 1
TP2302Do Not Stuff R2304 07/05 GPIO
1 4
Link
CL_RST# 1.assign GPIO PEG_CLKREQ# ?? SRN2K2J-1-GP
BA34 PERN6 CL_RST1# T9 1 10KR2J-3-GP 2.add circuit for PEG_CLKREQ#.
AW34 TP2303Do Not Stuff
PERP6
BC34
2
PETN6
BD34 PETP6
H1 PEG_CLKREQ# PCH_SMB_DATA 6 1
PEG_A_CLKRQ#/GPIO47
AT34 PERN7
AU34 PERP7 5 2 PCH_SMBDATA [7,18,19,40,64,76]
AU36 AD43 CLK_PCIE_VGA1# RN2327 1 4 CLK_PCIE_VGA# [80]
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA1 SRN0J-6-GP 2
AV36 PETP7 CLKOUT_PEG_A_P AD45 3 CLK_PCIE_VGA [80] 4 3
BG34 AN4 CLK_EXP_N CLK_EXP_N [9]

PERN8 CLKOUT_DMI_N
PEG
C BJ34 AN2 CLK_EXP_P CLK_EXP_P [9] Q2301 C
PERP8 CLKOUT_DMI_P DMN66D0LDW-7-GP
BG36 PETN8 PCH_SMBCLK [7,18,19,40,64,76]
BJ36 PETP8
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. AT1 CLK_DP_N CLK_DP_N [9] PCH_SMB_CLK
CLKOUT_DP_N/CLKOUT_BCLK1_N CLK_DP_P
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN CLKOUT_DP_P/CLKOUT_BCLK1_P AT3 CLK_DP_P [9]
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
From CLK BUFFER

AW24 CLKIN_DMI# CLKIN_DMI# [7]
CLKIN_DMI_N CLKIN_DMI
P9 PCIECLKRQ0#/GPIO73 CLKIN_DMI_P BA24 CLKIN_DMI [7]
[34] CLK_PCIE_NEW# RN2311 1 4 CLK_PCIE_NEW1# AM43 AP3 CLK_CPU_BCLK# CLK_CPU_BCLK# [7]

SRN0J-6-GP CLK_PCIE_NEW1 CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK
[34] CLK_PCIE_NEW 2 3 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_CPU_BCLK [7]
[34] NEWCARD_CLKREQ# NEWCARD_CLKREQ# U4 PEG_CLKREQ#

PCIECLKRQ1#/GPIO18 DREFCLK#
CLKIN_DOT_96N F18 DREFCLK# [7]
E18 DREFCLK DREFCLK [7]
RN2305 CLK_PCIE_MINI1_1# CLKIN_DOT_96P
[64] CLK_PCIE_MINI1# 1 4 AM47
D
SRN0J-6-GP CLK_PCIE_MINI1_1 CLKOUT_PCIE2N
[64] CLK_PCIE_MINI1 2 3 AM48 CLKOUT_PCIE2P
AH13 CLK_PCIE_SATA# CLK_PCIE_SATA# [7]
MINI1_CLKREQ# CLKIN_SATA_N/CKSSCD_N CLK_PCIE_SATA Q2305
[64] MINI1_CLKREQ# N4 PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P AH12 CLK_PCIE_SATA [7]
[25,51] DGPU_1D8V_PGOOD G 2N7002A-7-GP
[76] CLK_PCIE_LAN# RN2304 1 4 CLK_PCIE_LAN1# AH42 P41 CLK_PCH_14M CLK_PCH_14M [7]

SRN0J-6-GP CLK_PCIE_LAN1 CLKOUT_PCIE3N REFCLK14IN
[76] CLK_PCIE_LAN 2 3 AH41
S
CLKOUT_PCIE3P
[76] CLKREQ#_LAN CLKREQ#_LAN A8 J42 CLK_PCI_FB CLK_PCI_FB [21]

PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK
[76] CLK_PCIE_MINI2# RN2309 2 3 CLK_PCIE_MINI2_1# AM51 AH51 XTAL25_IN

SRN0J-6-GP CLK_PCIE_MINI2_1 CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
[76] CLK_PCIE_MINI2 1 4 AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
B B
MINI2_CLKREQ# M9 AF38 XCLK_RCOMP R2306 1 2 90D9R2F-1-GP +1.05V_VTT un-stuff 25M X'tal without HDMI/eDP/DP
PCIECLKRQ4#/GPIO26 XCLK_RCOMP
AJ50 T45 TP_CLK_OUTFLEX0 1 TP2307 C2313 BOM control stuff C or 0R

CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64 Do Not Stuff
AJ52 CLKOUT_PCIE5P
PCIECLKRQ5# H6 P43 TP_CLK_PCI_LPC 1 TP2305
Clock Flex
PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65 Do Not Stuff C2313

XTAL25_IN
AK53 T42 EDID_SEL_R R2310 1 2 0R2J-2-GP EDID_SELECT_R#
2
DY 1
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66
Do Not Stuff
1
AK51 Do Not Stuff
CLKOUT_PEG_B_P
Do Not Stuff
1
R2380
X2301
PEG_B_CLKRQ# CLK48M/EDID_SEL R2307 1 2 0R2J-2-GP
[21] PEG_B_CLKRQ# P13 PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 N50 CLK_PCH_48M [32] DY DY
2
IBEXPEAK-M-GP-NF
XTAL25_OUT
+3.3V_RUN
2
DY1
Pull up in page 21 for layout convenience 1 2 EDID_SELECT_R#
C2307
+3.3V_RUN R2314 +3.3V_RUN Do Not Stuff
10KR2J-3-GP
+3.3V_ALW
1
R2333 RN2307 U2302

10KR2J-3-GP 8 1 PCIECLKRQ5# 1
USB_OC#12_13 B
7 2 USB_OC#12_13 [21] VCC 5
6 3 CLKREQ#_LAN EDID_SELECT_R# 2
2
Q2306_1 Q2306 MINI2_CLKREQ# A

5 4 Y 4 EDID_SELECT# [54,55]
MMBT3904-7-F-GP 3 GND
1
A SRN10KJ-7GP A
74LVC1G08GW-1-GP 1st Samsung
[76] MINI2_CLKREQ_R# 2 3 MINI2_CLKREQ#
+3.3V_RUN
RN2308
2
Do Not Stuff DY R2305
1
Wistron Corporation
1
R2309 1 2 Do Not Stuff NEWCARD_CLKREQ#
DY 2 3
MINI1_CLKREQ# C2312 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 4
Do Not Stuff DY Taipei Hsien 221, Taiwan, R.O.C.
2
SRN10KJ-5-GP
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
www.vinafix.vn
Vostro Calpella X00
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1 +RTC_CELL
R2402
1 2 PCH_RTCX2 20KR2J-L2-GP
R2401 1 2
10MR2J-L-GP INTVRMEN- Integrated SUS
1.1V VRM Enable
1
X2401 C2401
SC1U6D3V3KX-2GP High - Enable internal VRs
1 4
2
C2402 C2403
SC18P50V2JN-1-GP SC18P50V2JN-1-GP
1
1
D U2001A 1 OF 10 LPC_LAD[0..3] D
LPC_LAD[0..3] [36,37,70]
2 3
PCH_RTCX1 B13 D33 LPC_LAD0
2
2
+RTC_CELL PCH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
D13 RTCX2 FWH1/LAD1 B33
X-32D768KHZ-38GPU R2403 C32 LPC_LAD2
20KR2J-L2-GP FWH2/LAD2 LPC_LAD3
FWH3/LAD3 A32
1 2 PCH_RTCRST# C14 RTCRST#
FWH4/LFRAME# C34 LPC_LFRAME# [36,37,70]
2
SRTCRST# D17 SRTCRST#
1
C2404 G2401
DW A34
RTC
LPC
SM_INTRUDER# LDRQ0#
SC1U6D3V3KX-2GP Do Not Stuff 1 2 A16 INTRUDER# LDRQ1#/GPIO23 F34
07/23 Added R2406 1MR2J-1-GP
2
1.Added "ME in Manufacturing Mode" strap PCH_INTVRMEN
+RTC_CELL 1 2 A14 AB9 INT_SERIRQ [36,37]
1
2.Added CardReader_Wake# to sent Card detect signal for PCH . ( Only For JMB380 )
R2404 330KR2F-L-GP INTVRMEN SERIRQ
[30] PCH_AZ_CODEC_BITCLK
R2405 1 2 33R2J-2-GP ACZ_BIT_CLK A30 HDA_BCLK
HDD
Flash Descriptor Security SATA0RXN AK7 SATA_IRXN0_HTXN0_C [59]
R2407 1 2 33R2J-2-GP ACZ_SYNC_R D29 AK6
Override/ ME Debug Mode [30] PCH_AZ_CODEC_SYNC HDA_SYNC SATA0RXP SATA_ITXN0_HRXN0_C C2405 1
SATA_IRXP0_HTXP0_C [59]
SATA0TXN AK11 2 SCD01U50V2KX-1GP SATA_ITXN0_HRXN0 [59]
P1 AK9 SATA_ITXP0_HRXP0_C C2406 1 2 SCD01U50V2KX-1GP SATA_ITXP0_HRXP0 [59]
[30] SB_SPKR SPKR SATA0TXP
ME_UNLOCK# [30] PCH_AZ_CODEC_RST#
R2408 1 2 33R2J-2-GP ACZ_RST#_R C30 HDA_RST#
ODD
This strap should only be asserted low via SATA1RXN AH6 SATA_IRXN1_OTXN1_C [59]
external pull down in manufacturing/debug SATA1RXP AH5 SATA_IRXP1_OTXP1_C [59]
[30] PCH_SDIN_CODEC G30 AH9 SATA_ITXN1_ORXN1_C C2407 1 2 SCD01U50V2KX-1GP SATA_ITXN1_ORXN1 [59]
environments ONLY. HDA_SDIN0 SATA1TXN SATA_ITXP1_ORXP1_C C2408 1
SATA1TXP AH8 2 SCD01U50V2KX-1GP SATA_ITXP1_ORXP1 [59]
F30 HDA_SDIN1
SATA2RXN AF11
C E32 AF9 C
IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
ME_UNLOCK_R#
1
DY
R2419
2
Do Not Stuff
F32 HDA_SDIN3 SATA2TXP AF6
SATA3RXN AH3
R2409 1 2 33R2J-2-GP ACZ_SDATAOUT_R B29 AH1
[30] PCH_SDOUT_CODEC HDA_SDO SATA3RXP
SATA3TXN AF3
R2417 1 2 0R2J-2-GP ME_UNLOCK_R# H32

SATA3TXP AF1
ESATA
SATA
[37] ME_UNLOCK# HDA_DOCK_EN#/GPIO33
SATA4RXN AD9 ESATA_IRX_DTX_N4_C [63]
J30 HDA_DOCK_RST#/GPIO13 SATA4RXP AD8 ESATA_IRX_DTX_P4_C [63]
SATA4TXN AD6 ESATA_ITX_DRX_N4 [63]
SATA4TXP AD5 ESATA_ITX_DRX_P4 [63]
TP2404 1 PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
NO REBOOT STRAP TP2405 1 PCH_JTAG_TMS K3 AB3
+3.3V_RUN JTAG_TMS SATA5TXN
SATA5TXP AB1
No Reboot Strap R23 TP2406 1 PCH_JTAG_TDI K1 JTAG_TDI
JTAG
2 SB_SPKR Low = Default TP2407 PCH_JTAG_TDO
1
R2410 DY Do Not Stuff HDA_SPKR High = No Reboot
1 J2 JTAG_TDO SATAICOMPO AF16
+1.05V_VTT
TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI R2412 37D4R2F-GP
1 2 INT_SERIRQ
R2411 10KR2J-3-GP
[62] PCH_SPI_CLK R2413 1 2 15R2J-GP SPI_CLK_R BA2 SPI_CLK
[62] PCH_SPI_CS0# R2414 1 2 15R2J-GP SPI_CS#0_R AV3
B SPI_CS0# B
AY3 SPI_CS1# SATALED# T3 SATA_LED# [66]

DW
07/02 Change R2415 1 2 15R2J-GP SPI_MOSI_R AY1 Y9 GPO_DSM +3.3V_RUN
1.Change R2410 to dummy [62] PCH_SPI_DO SPI_MOSI SATA0GP/GPIO21 GPO_DSM [76]
R2416
SPI
[62] PCH_SPI_DI AV1 V1 PCH_GPIO19 10KR2J-3-GP
SPI_MISO SATA1GP/GPIO19 GPO_DSM 1 2
R2418
IBEXPEAK-M-GP-NF 10KR2J-3-GP
PCH_GPIO19
DW 1 2
07/10 assign GPIO
1.assign GPIO GPIO_DSM,Felic_DETECT#
A 1st Samsung A
Wistron Corporation
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
5 4
www.vinafix.vn 3 2
Vostro Calpella
Sheet
1
24 of 88
X00
5 4 3 2 1
+3.3V_RUN_GPU +3.3V_RUN_GPU +3.3V_RUN
1
2
R2555 R2503
R2552 2K2R2J-2-GP 10KR2J-3-GP
10KR2J-3-GP U2001F 6 OF 10
Q2515_1
1 2
2
DEEP_IDLE# Y3 AH45
1
Q2515 BMBUSY#/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
MMBT3904-7-F-GP [37] ECSCI# ECSCI# C38 TACH1/GPIO1
[81] DEEPIDLE_WAKE_INT_R# 2 3
[78] BIO_DET# BIO_DET# D37 TACH2/GPIO6
D
CLKOUT_PCIE7N AF48 D
MISC
ECSWI# J32 AF47
[37] ECSWI# TACH3/GPIO7 CLKOUT_PCIE7P
ECSMI# F10
[37] ECSMI# GPIO8
1
C2501
Do Not Stuff DY K9 LAN_PHY_PWR_CTRL/GPIO12 A20GATE U2 KA20GATE [37]
2
PCH_GPIO15 T7 GPIO15
DGPU_HOLD_RST# AA2 +1.05V_VTT
[80] DGPU_HOLD_RST# SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N AM3 BCLK_CPU_N [9]
[86] GFX_CORE_PGOOD 1 2
R2505 1 2 0R2J-2-GP DGPU_PWROK F38
[23,51] DGPU_1D8V_PGOOD TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P AM1 BCLK_CPU_P [9]
2
R2506 0R2J-2-GP
[54] LCD_CBL_DET# 1 2 LCD_CBL_DET_R# Y7 BG10 R2509
SCLOCK/GPIO22 PECI H_PECI [9]
GPIO
R3749 100R2J-2-GP 56R2J-4-GP
H10 GPIO24 RCIN# T1 KBRCIN# [37]
+3.3V_RUN
1
PCH_GPIO27 AB12 BE10 H_PWRGOOD [9,42]
GPIO27 PROCPWRGD
CPU
DW Do Not Stuff TP2508 1 PCH_GPIO28 V13 BD10 PCH_THERMTRIP_R 1 2
07/02 Change GPIO28 THRMTRIP# H_THRMTRIP# [9,37,42]
R2507 R2511
10KR2J-3-GP 1.Change CLK_SATA_OE# to pull-down STP_PCI# 56R2J-4-GP
M11 STP_PCI#/GPIO34
1 2DGPU_PWROK Placed Within 2" from PCH
PCH_GPIO35 V6
R2512 SATACLKREQ#/GPIO35
10KR2J-3-GP [37] DGPU_PWR_EN# DGPU_PWR_EN# AB7 BA22
SATA2GP/GPIO36 TP1
2
1 2 ECSCI#
DGPU_PRSNT# AB13 AW22
R2525 SATA3GP/GPIO37 TP2
C R2526 10KR2J-3-GP PCH_GPIO38 V3 BB22 C
Do Not Stuff SLOAD/GPIO38 TP3
1
2 PCH_GPIO27 R2548 2100R2J-2-GP KB_DET_R#

1
DY [68] KB_DET# 1 P3 SDATAOUT0/GPIO39 TP4 AY45
PCIECLKRQ6# H3 AY46
PCIECLKRQ6#/GPIO45 TP5
[9] DDR_RST_GATE# DDR_RST_GATE# F1 AV43
PCIECLKRQ7#/GPIO46 TP6
[40] FFS_INT2_R FFS_INT2_R AB6 AV45

SDATAOUT1/GPIO48 TP7
[37] TURBO_BOOST_ALERT# TURBO_BOOST_ALERT# AA4 AF13

SATA5GP/GPIO49 TP8
PCH_GPIO57 F8 M18
GPIO57 TP9
07/10 Added N18
1.Changed PCH GPIO DDR_RST_GATE from GPIO57 to GPIO46 , Bason on design guide TP10
07/23 Added
1.Added Finger Printer Detect Pin, control by PCH For layout request A4
A49
VSS_NCTF_1 TP11 AJ24
2.Change KB_DET signal from EC to PCH control
NCTF
VSS_NCTF_2
RSVD
3.Change LCD_CBL_DET signal from EC to PCH control A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
B53 VSS_NCTF_10
+3.3V_ALW BE1 M30
VSS_NCTF_11 TP16
BE53 VSS_NCTF_12
PCH_GPIO28 1 2 Do Not Stuff TP2511 1 PCH_NCTF_2 BF1 N30
B R2530 10KR2J-3-GP VSS_NCTF_13 TP17 B
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
PCH_GPIO57 1 2 BH2
R2523 10KR2J-3-GP VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
PCH_GPIO15 1 2 BJ1 AB45
R2532 1KR2J-1-GP VSS_NCTF_19 NC_1
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
PCIECLKRQ6# 1 2 Do Not Stuff TP2512 1 PCH_NCTF_3 BJ49
R2521 10KR2J-3-GP VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
ECSMI# 1 2 BJ52 AB41
R2531 10KR2J-3-GP VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
+3.3V_RUN Do Not Stuff TP2510 1 PCH_NCTF_1 E1 P6 INIT3_3V# 1 TP2506Do Not Stuff
Do Not Stuff TP2509 PCH_NCTF_4 VSS_NCTF_30 INIT3_3V#
1 E53 VSS_NCTF_31
TP24 C10
IBEXPEAK-M-GP-NF
ECSWI# R2504 1 2 10KR2J-3-GP
DGPU_HOLD_RST# R2516 1 2 Do Not Stuff +3.3V_RUN

DY
STP_PCI# R2517 1 2 10KR2J-3-GP
1
PCH_GPIO38 R2519 1 2 10KR2J-3-GP

A
DYR2527
Do Not Stuff 1st Samsung A
DGPU_PWR_EN# R2529 1 2 10KR2J-3-GP
2
KB_DET_R# R2533 1 2 10KR2J-3-GP DGPU_PRSNT#

Wistron Corporation
1
BIO_DET# R2534 1 2 10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R2528 Taipei Hsien 221, Taiwan, R.O.C.
FFS_INT2_R R2520 2 1 Do Not Stuff
DY 10KR2J-3-GP
Title
LCD_CBL_DET_R# R2522 2 1 10KR2J-3-GP
PCH (GPIO/CPU)
2
5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
25 of 88
X00
5 4 3 2 1
+1.05V_VTT +3.3V_CRT_LDO
69mA
U2001G POWER 7 OF 10 L2603 R2602
1.432A AB24
AB26
VCCCORE VCCADAC AE50 +VCCA_DAC_1_2 1 2
BLM18PG181SN1D-GP
1 2 +3.3V_RUN
VCCCORE
1
C2601 AB28 AE52 C2604 C2605 C2603 0R2J-2-GP
VCCCORE VCCADAC
SCD01U16V2KX-3GP
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP C2602 AD26 SC10U6D3V5MX-3GP
SC1U10V2KX-1GP VCCCORE
CRT
D AD28 1.432A AF53 D
2
VCCCORE VSSA_DAC
AF26 VCCCORE
VCC CORE
AF28 VCCCORE VSSA_DAC AF51
AF30 VCCCORE
AF31 VCCCORE
AH26 VCCCORE
AH28 +3VS_VCCA_LVD +3.3V_RUN
VCCCORE
AH30
AH31
AJ30
VCCCORE
VCCCORE <1mA VCCALVDS AH38
C2623
2
R2609
1 <1mA
0R3J-0-U-GP
VCCCORE
AJ31 VCCCORE VSSA_LVDS AH39 1
DY2 +1.8V_RUN
Do Not Stuff
+1.05V_VTT
VCCTX_LVDS AP43 +1.8VS_VCCTX_LVDS 1 2 59mA
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
AP45 L2604
VCCTX_LVDS
1
59mA VCCTX_LVDS AT46 C2625 C2624 C2626 IND-D1UH-21-GP
LVDS
Do Not Stuff
+1.05V_VTT
AK24 VCCIO VCCTX_LVDS AT45
DY
2
40mA 1
L2601 DY 2 +1.05VS_VCCAPLL_EXP BJ24 VCCAPLLEXP
AB34
+3.3V_CRT_LDO +5V_RUN
VCC3_3
1
Do Not Stuff C2606 U2601
Do Not Stuff +3.3V_RUN
DY AN20 VCCIO 357mA VCC3_3 AB35
AN22 5 1
357mA
HVCMOS
2
VCCIO OUT IN
AN23 VCCIO VCC3_3 AD35
AN24 VCCIO DY GND 2
1
C2607 C2628
+1.05V_VTT
AN26 VCCIO
3.062A SCD1U10V2KX-5GP Do Not Stuff C2629 DY
AN28
BJ26
VCCIO DY 4 NC#4 SHDN# 3
Do Not Stuff
3.062A
2
C VCCIO C
BJ28 VCCIO
AT26 Do Not Stuff
VCCIO
1
1
C2608 C2609 C2610 C2611 C2612 AT28 +VCC_VRM
VCCIO
AU26 VCCIO
SC10U6D3V5MX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
AU28
2
2
VCCIO
AV26
AV28
AW26
VCCIO
VCCIO VCCVRM AT24 35mA +1.05VS_VCC_DMI +1.05V_VTT
VCCIO
AW28 VCCIO
58mA
DMI
BA26 VCCIO VCCDMI AT16 1 R2601 2
BA28 VCCIO
1
BB26 AU16 C2613 0R2J-2-GP
VCCIO VCCDMI SC1U10V3KX-3GP
BB28 VCCIO
BC26
2
VCCIO
PCI E*
BC28 VCCIO
BD26 +3.3V_RUN
+3.3V_RUN VCCIO
BD28 VCCIO
BE26 VCCIO VCCPNAND AM16
BE28 AK16
BG26
VCCIO
VCCIO
VCCPNAND
VCCPNAND AK20 156mA
1
C2614 BG28 156mA AK19

VCCIO VCCPNAND
1
SCD1U10V2KX-4GP BH27 AK15 C2615
VCCIO VCCPNAND SCD1U10V2KX-5GP
AK13
2
+1.05V_VTT VCCPNAND
AN30 AM12
2
+1.05VS_VCCAPLL_FDI VCCIO VCCPNAND
NAND / SPI
AN31 VCCIO VCCPNAND AM13
1
L2602 DY 2
+1.8V_RUN VCCPNAND AM15
357mA
1
Do Not Stuff C2616 AN35 VCC3_3 +3.3V_RUN

B DYDo Not Stuff R2606 B
2
1
2 1 +VCC_VRM AT22 VCCVRM[1]
0R2J-2-GP R2605
+1.05V_VTT BJ18 VCCFDIPLL VCCME3_3 AM8
AM9
85mA 0R2J-2-GP
VCCME3_3
FDI
AM23 85mA AP11
2
VCCIO VCCME3_3 PCH_VCCME3_3
VCCME3_3 AP9
1
C2622
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF
A 1st Samsung A
Wistron Corporation
Title
PCH (POWER1)
5 4
www.vinafix.vn 3 2
Vostro Calpella
Sheet
1
26 of 88
X00
5 4 3 2 1
+1.05V_VTT
L2701
Do Not Stuff
52mA 1
DY 2 +1.05VS_VCCA_CLK U2001J POWER 10 OF 10 +1.05V_VTT
Do Not Stuff
1
Do Not Stuff C2701 C2702 AP51 V24
VCCACLK VCCIO
DY DY 52mA VCCIO V26
1
AP53 Y24 C2706
2
VCCACLK VCCIO SC1U10V2KX-1GP
VCCIO Y26
2
AF23 VCCLAN VCCSUS3_3 V28
+3.3V_ALW
320mA VCCSUS3_3 U28
1 R2708 2 PCH_VCC_LAN AF24 VCCLAN VCCSUS3_3 U26
D 0R2J-2-GP U24 D
VCCSUS3_3
VCCSUS3_3 P28
1
DCPSUSBYP Y20 P26
DCPSUSBYP VCCSUS3_3 C2703
VCCSUS3_3 N28
1
C2707 N26 SCD1U10V2KX-4GP
2
SCD1U10V2KX-4GP VCCSUS3_3
AD38 VCCME VCCSUS3_3 M28
M26
2
VCCSUS3_3
AD39 L28
USB
VCCME VCCSUS3_3
VCCSUS3_3 L26
+1.05V_VTT AD41 J28
VCCME VCCSUS3_3
J26
1.849A AF43 VCCME
VCCSUS3_3
VCCSUS3_3 H28
163mA VCCSUS3_3 H26
AF41 VCCME 1.849A VCCSUS3_3 G28
1
C2705 C2708 G26
SC10U6D3V5MX-3GP SC1U10V2KX-1GP VCCSUS3_3 +3.3V_ALW
AF42 VCCME VCCSUS3_3 F28
F26 DW
2
VCCSUS3_3 +3.3V_ALW
V39 VCCME VCCSUS3_3 E28
E26 07/10 Change resistor Value
Clock and Miscellaneous

VCCSUS3_3
2
1.R2701,R2702 value corrected to 100 Ohms following PDG doc
V41 VCCME VCCSUS3_3 C28
C26 D2701
VCCSUS3_3
1
V42 B27 CH751H-40PT-GP +5V_ALW
VCCME VCCSUS3_3
1
C2704 C2710 A28 C2709
SC10U6D3V5MX-3GP Do Not Stuff VCCSUS3_3 SCD1U10V2KX-4GP
DY Y39 A26
1
L2702 VCCME VCCSUS3_3 +3.3V_RUN
2
+1.05V_VTT IND-10UH-203-GP Y41 U23 +1.05V_VTT 1 2
VCCME VCCSUS3_3
1 2 +1.05VS_VCCA_A_DPL Y42 V23 R2701
VCCME VCCIO
2
100R2J-2-GP
1
1
C C2711 +5VALW_PCH_VCC5REFSUS D2702 +5V_RUN C
C2734 SC1U10V2KX-1GP
<1mA V5REF_SUS F24
C2712 CH751H-40PT-GP
Do Not Stuff +VCCRTCEXT SC1U10V2KX-1GP
DY V9
2
2
DCPRTC
1
1
C2713 +VCC_VRM
SCD1U10V2KX-4GP <1mA K49 +5VS_PCH_VCC5REF 1 2
V5REF
AU24
2
VCCVRM
PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL R2702
1
L2703 J38 +3.3V_RUN 100R2J-2-GP
VCC3_3
1
C2714 BB51 C2715

IND-10UH-203-GP C2735
DY SC1U10V2KX-1GP 68mA +1.05VS_VCCA_A_DPL BB53
VCCADPLLA
68mA L38 SC1U10V2KX-1GP
2
Do Not Stuff VCCADPLLA VCC3_3
2
1
M36
69mA +1.05VS_VCCA_B_DPL BD51 VCCADPLLB
VCC3_3 C2716
SCD1U10V2KX-4GP
+3.3V_RUN
BD53 69mA N36
2
VCCADPLLB VCC3_3
+1.05V_VTT AH23 P36
VCCIO VCC3_3
1
AJ35 VCCIO
AH35 U35 C2717
VCCIO VCC3_3
SCD1U10V2KX-4GP
2
1
C2718 C2719 C2720 AF34

SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VCCIO
VCC3_3 AD13
AH34
2
VCCIO +1.05VS_VCCAPLL +1.05V_VTT

L2704
AF32
+VCCSST V12
VCCIO
VCCSATAPLL AK3
AK1
1
DY 2 31mA
DCPSST VCCSATAPLL
1
C2721 C2722 Do Not Stuff
Do Not Stuff
DY DYDo Not Stuff
1
B +1.05V_VTT B
2
C2723 +1.05VALW_INT_VCCSUS Y22
SCD1U10V2KX-4GP DCPSUS
AH22
2
VCCIO
1
C2724 +VCC_VRM
1
SCD1U10V2KX-4GP C2725
P18 196mA AT20 SC1U10V2KX-1GP
2
VCCSUS3_3 VCCVRM
2
+3.3V_ALW U19
SATA
VCCSUS3_3
PCI/GPIO/LPC
AH19
163mA U20 VCCSUS3_3
VCCIO
AD20
VCCIO
1
U22 VCCSUS3_3
C2726 AF22
SCD1U10V2KX-4GP +3.3V_RUN VCCIO
2
VCCIO AD19
V15 VCC3_3 VCCIO AF20
VCCIO AF19
1
V16 VCC3_3 VCCIO AH20

C2727
SCD1U10V2KX-4GP Y16 AB19
2
VCC3_3 VCCIO
VCCIO AB20
+1.05V_VTT AB22
VCCIO +1.05V_VTT
AD22
<1mA AT18 V_CPU_IO
VCCIO
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AA34
CPU
VCCME
1
C2728 C2729 C2730 <1mA Y34

SC4D7U6D3V5KX-3GP VCCME
AU18 V_CPU_IO VCCME Y35
AA35
2
VCCME
A 1st Samsung A
+RTC_CELL 6mA
RTC
A12 VCCRTC 2mA 6mA VCCSUSHDA L30 1 2 +3.3V_ALW

HDA
R2707 0R2J-2-GP
2mA Wistron Corporation
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
IBEXPEAK-M-GP-NF C2731 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1
C2732 C2733 SC1U10V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C.

2
Title
2
+3VS_+1.5VS_HDA_IO PCH (POWER2)

5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
27 of 88
X00
5 4 3 2 1
U2001I 9 OF 10
AY7 VSS VSS H49
B11 VSS VSS H5
B15 VSS VSS J24
B19 VSS VSS K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 VSS VSS K7
B39 VSS VSS L14
B43 VSS VSS L18
B47 VSS VSS L2
D B7 VSS VSS L22 D
U2001H 8 OF 10 BG12 L32
VSS VSS
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
AD12 VSS VSS AM32 BE20 VSS VSS T12
C AD16 AM34 BE24 T41 C
VSS VSS VSS VSS
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 VSS VSS AV22 BE50 VSS VSS U32
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 VSS VSS AN32 BF51 VSS VSS V19
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 VSS VSS AP46 BH11 VSS VSS V32
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 VSS VSS AR52 BH35 VSS VSS V45
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 VSS VSS AT41 C50 VSS VSS V8
B B
AH16 VSS VSS AT47 D51 VSS VSS W2
AH24 VSS VSS AT7 E12 VSS VSS W52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 VSS VSS AV16 E20 VSS VSS Y12
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW14 F5 VSS VSS P49
AJ34 VSS VSS AW18 G10 VSS VSS Y5
AT5 VSS VSS AW2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 VSS VSS AW32 G2 VSS VSS P24
AM41 VSS VSS AW36 G22 VSS VSS T43
AN19 VSS VSS AW40 G32 VSS VSS AD51
AK26 VSS VSS AW52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 VSS VSS AY43 G44 VSS VSS Y47
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
A H30 VSS VSS AK45 1st Samsung A
H34 VSS VSS AK39
H38 VSS VSS AV14
H42 VSS Wistron Corporation
IBEXPEAK-M-GP-NF Title
PCH (VSS)
5 4
www.vinafix.vn 3 2
Date:
Vostro Calpella
1
28 of 88
X00
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
+AVDD
+3.3V_RUN +5V_RUN
+3.3V_RUN
Close to codec L3004
0R2J-2-GP
1 2
Close to codec
R3011
SC1U10V3KX-3GP
SCD1U10V2KX-4GP
AUD_DVDDCORE 0R5J-5-GP +5V_RUN
D
+PVDD D
1
C3015
C3022
C3016 L3005
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
1
1
C3009
C3019
SC10U6D3V5MX-3GP 1 2
SCD1U10V2KX-4GP
2
U3001 0R5J-5-GP
SC1U10V3KX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
2
2
2
1
C3027
C3014
C3017
C3011
1 27 L3003
DVDD_CORE AVDD
38 1 2
1
AVDD
9
2
DVDD 0R5J-5-GP
PVDD 39
DVDDIO 3 45
DVDD_IO PVDD
13 AUD_SENSE_A
PCH_AZ_CODEC_BITCLK SENSE_A
PCH_AZ_CODEC_BITCLK 6 14 AUD_SENSE_B
[24] PCH_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
R3013 1 2 33R2J-2-GP PCH_SDIN_CODEC_C0 8
[24] PCH_SDIN_CODEC HDA_SDI AUD_EXT_MIC_L
1
HP0_PORT_A_L 28 AUD_EXT_MIC_L [60]

PCH_SDOUT_CODEC 5 29 AUD_EXT_MIC_R
C3012 [24] PCH_SDOUT_CODEC HDA_SDO HP0_PORT_A_R AUD_EXT_MIC_R [60]
DY Do Not Stuff VREFOUT_A_OR_F 23 AUD_VREFOUT_B AUD_VREFOUT_B [60]
PCH_AZ_CODEC_SYNC
2
[24] PCH_AZ_CODEC_SYNC 10 HDA_SYNC

31 AUD_HP1_JACK_L_C R3023 1 2 60D4R2F-GP AUD_HP1_JACK_L
PCH_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R_C R3019 AUD_HP1_JACK_L [60]
[24] PCH_AZ_CODEC_RST# 11 HDA_RST# HP1_PORT_B_R 32 1 2 60D4R2F-GP AUD_HP1_JACK_R
AUD_HP1_JACK_R [60]
PORT_C_L 19
PORT_C_R 20
+3.3V_RUN VREFOUT_C 24
AUD_DMIC_CLK 2 DMIC_CLK/GPIO1
[73] AUD_DMIC_IN0
AUD_DMIC_IN0 4 DMIC0/GPIO2 SPKR_PORT_D_L+ 40 AUD_SPK_L+
AUD_SPK_L+ [60] From SB
41 AUD_SPK_L- C3010
SPKR_PORT_D_L- AUD_SPK_L- [60] R3016
C SB_SPKR_R C
1
46 DMIC1/GPIO0/SPDIF_OUT_1 2 1 1 2 SB_SPKR [24]

43 SCD1U10V2KX-4GP 499KR2F-1-GP
R3020 SPKR_PORT_D_R-
48 44 2 1 KBC_BEEP_R 1 2 KBC_BEEP [37]
10KR2J-3-GP SPDIF_OUT_0 SPKR_PORT_D_R+ SCD1U10V2KX-4GP
R3024
[37] AMP_MUTE#
AMP_MUTE# 47 EAPD PORT_E_L 15 C3018
499KR2F-1-GP From EC
2
PORT_E_R 16
AMP_MUTE#
PUMP_CAPN 17
PORT_F_L AUD_PC_BEEP
35 CAP- PORT_F_R 18
1
C3024
SC2D2U25V5KX-1GP PC_BEEP 12 AUD_PC_BEEP
Internal pull up 60K 2
36 CAP+
PUMP_CAPP
MONO_OUT 25 Trace width>15 mils
check external pull up??
7 DVSS
+3.3V_RUN 33 22 AUD_CAP2
U3002 AVSS CAP2
30 AVSS
5 1 26 21 AUD_VREFFLT
VCC OE# AVSS VREFFILT
AUD_DMIC_CLK_Y 4
DY A 2
3 42 34 AUD_V_B
Y GND PVSS V-
Do Not Stuff 49 37 AUD_VREG
GND VREG
1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
Do Not Stuff
C3023
C3013
92HD81B1A5NLGXUAX8-GP
DY
1
R3017
C3025
C3021
2
R3014
2
B B
[73] AUD_DMIC_CLK_G 1 2 33R2J-2-GP AUD_DMIC_CLK
1
EC3001
Do Not Stuff DY
2
Close to codec
+AVDD
Azalia I/F EMI
Place this block
1
PCH_SDOUT_CODEC
R3018 close to Audio Codec Pin13 +AVDD
2K49R2F-GP
1
1
R3012
2
Do Not Stuff AUD_SENSE_A R3015

DY 100KR2J-1-GP
1
2
C3026
2
SC1KP50V2KX-1GP AUD_SENSE_B
PCH_AZ_CODEC_SDOUT1
A R3022 R3021 1st Samsung A

20KR2F-L-GP 39K2R2F-L-GP
Wistron Corporation
2

EXT_MIC_JD# [60] Close to Pin14
1
C3020 Title
DY Do Not Stuff
AUD_HP1_JD# [60] AUDIO CODEC_92HD81
2
www.vinafix.vn
Revised HP/MIC detect circuit A3
Vostro Calpella SA
2009/06/03 Date: Wednesday, September 02, 2009 Sheet 30 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN_CARD
[23] CLK_PCH_48M +3.3V_RUN_CARD trace = 40mil

SD_D2 SD_D2 [33]
PCH GPIO67(48M) confirm with SW SD_D3
1
SD_D3 [33]
C3206 C3207
SCD1U10V2KX-4GP SC10U6D3V5MX-3GP
2
RREF trace =15mils
C3201
RREF Close to chip
1
DY 2 U3201
24
23
22
21
20
19
+3.3V_RUN Do Not Stuff RTS5138-GR-GP
090721-1
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
1 R3201 2
6K2R2F-GP 1 18 SD_CMD SD_CMD [33]
RREF SP10
090721-1 [21] USB_PN9 2 DM GPIO0 17
[21] USB_PP9 3 DP SP9 16
4 15 SD_CLK SD_CLK [33]
3V3_IN SP8
+3.3V_RUN_CARD 5 CARD_3V3 SP7 14
V18 6 13 SD_CD# SD_CD# [33]
V18 SP6
2
XD_CD#
DY
1
C C3203 C3204 C
SP1
SP2
SP3
SP4
SP5
C3202 25
1
GND
SCD1U10V2KX-4GP
Do Not Stuff
SC1U10V2KX-1GP
7
8
9
10
11
12
V18 trace =15mils
SD_D0 SD_D0 [33]

SD_D1 SD_D1 [33]
SD_WP SD_WP [33]
B B
A 1st Samsung A
Wistron Corporation
Title
CardReader/RTS5138
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = SDIO SD/MMC/MMC+ Card Reader

D D
+3.3V_RUN_CARD +3.3V_RUN_CARD
CARD1
Close to +3.3V_RUN_CARD
4 10
SC10U6D3V5MX-3GP
SCD01U16V2KX-3GP
SC2D2U10V3KX-1GP
VDD CD SD_CD# [32]
Do Not Stuff
Do Not Stuff
C3301
C3302
C3303
C3304
C3305
1 SD_D3_R
CD/DAT3
1
CD/WP/GND 11
SD_D0_R
SD_D1_R
7
8
DAT0 WP 12
5 SD_CLK_R
SD_WP [32] DY DY
2
SD_D2_R DAT1 CLK SD_CMD_R
9 DAT2 CMD 2
EMPTY 14
VSS1 3
NP1 NP1 VSS2 6
NP2 NP2 GND 13
CARD-PUSH-9P-1-GP-U
20.I0045.001
C
Close to CARD1 C
[32] SD_D0 SD_D0 R3301 1 2 0R2J-2-GP SD_D0_R

SD_WP
[32] SD_CLK SD_CLK R3305 1 2 0R2J-2-GP SD_CLK_R
SD_CD#
[32] SD_CMD SD_CMD R3306 1 2SD_CMD_R
0R2J-2-GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
1
1
EC3301
EC3302
EC3303
EC3304
EC3305
EC3306
EC3307
EC3308
DY DY DY DY DY DY DY DY
2
SSID = 1394
B B
Remove 1394
A 1st Samsung A
Wistron Corporation
Title
CARD READER CONN

www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D
SSID = ExpressCard +1.5V_CARD Max. 650mA, Average 500mA. D
+3.3V_CARD Max. 1300mA, Average 1000mA

+3.3V_CARDAUX Max. 275mA
NEW1
27
USB12_N 2
USB12_P 3
NEWCARD_OC# CPUSB# 4
TP3401
PM_SLP_S3# [22,37,42,50,51,86] 5
6
PCH_SMB_CLK 7
[23] PCH_SMB_CLK
PCH_SMB_DATA
21
19
18 [23] PCH_SMB_DATA 8
7
U3401 1 +1.5V_CARD 9
10
OC#
STBY#
GND
THERMAL_PAD
RCLKEN
[22,76] PCIE_WAKE# PCIE_WAKE# 11

+3.3V_CARDAUX 12
For 2nd Source 74.05538.073 PERST# 13
+3.3V_CARD 14
C 16 20 15 C
NC#16 SHDN# PM_SLP_S4# [22,37,50]
14 8 PERST# RN3401 [23] NEWCARD_CLKREQ# NEWCARD_CLKREQ# 16
+1.5V_RUN NC#14 PERST#
13 9 CPUSB# 4 1 CPPE# 17
+1.5V_CARD NC#13 CPUSB# +3.3V_ALW
CPPE# CLK_PCIE_NEW#
+3.3V_CARD 5
4
NC#5 CPPE# 10
6 NRST
3
DY 2 [23] CLK_PCIE_NEW#
[23] CLK_PCIE_NEW CLK_PCIE_NEW
18
19
+3.3V_RUN NC#4 SYSRST# Do Not Stuff 20
[23] PCIE_IRXN5_NTXN5 PCIE_IRXN5_NTXN5 21
AUXOUT
1.5VOUT
3.3VOUT
R3401 2 1 0R2J-2-GP PLT_RST# [9,21,36,37,64,70,76,80] [23] PCIE_IRXP5_NTXP5 PCIE_IRXP5_NTXP5 22

AUXIN
1.5VIN
3.3VIN
23
C3410 2 Do Not Stuff PCIE_ITXN5_NRXN5
DY1 [23] PCIE_ITXN5_NRXN5
[23] PCIE_ITXP5_NRXP5 PCIE_ITXP5_NRXP5
24
25
TPS2231RGP-GP-U 26
15
17
11
12
3
2
28
+3.3V_CARDAUX +3.3V_RUN
+3.3V_ALW +3.3V_CARD ACES-CON26-11-GP
+1.5V_CARD +1.5V_RUN
20.K0315.026
+1.5V_CARD Max. 650mA, Average 500mA.
+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA
R3402
1 2
0R3J-0-U-GP
B [21] USB_PN12 USB12_N B
Lay out close to Chip
+3.3V_ALW +1.5V_RUN +3.3V_RUN +3.3V_CARD +1.5V_CARD +3.3V_CARDAUX
2
SC4D7U6D3V5KX-3GP
L3401
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Do Not Stuff
1
DY
C3401
C3402
C3403
C3404
C3405
C3406
C3407
C3408
C3409
2
3
[21] USB_PP12 USB12_P
R3403
1 2
0R3J-0-U-GP
0715 Add commom choke
A 1st Samsung A
Wistron Corporation
Title
ExpressCard
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
A3 SA
Vostro Calpella
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
Remove TPM EEPROM
C C
TPM board CONN
TPM1
+3.3V_RUN 11
1
B LPC_LAD0 2 B
[24,37,70] LPC_LAD0
LPC_LAD1 3
[24,37,70] LPC_LAD1
LPC_LAD2 4
[24,37,70] LPC_LAD2
LPC_LAD3 5
[24,37,70] LPC_LAD3
[24,37,70] LPC_LFRAME# LPC_LFRAME# 6
PLT_RST# 7
[9,21,34,37,64,70,76,80] PLT_RST# INT_SERIRQ
[24,37] INT_SERIRQ 8
PCLK_TPM 9
[21] PCLK_TPM
1 10
AFTP3601 12
ACES-CON10-4-GP
20.K0238.010
AFTP3602 1 LPC_LAD0
AFTP3603 1 LPC_LAD1
AFTP3604 1 LPC_LAD2
AFTP3605 1 LPC_LAD3
AFTP3606 1 LPC_LFRAME#
AFTP3607 1 PLT_RST#
AFTP3608 1 INT_SERIRQ
AFTP3609 1 PCLK_TPM
AFTP36010 1 +3.3V_RUN
A A
1st Samsung
Wistron Corporation
Title
TPM
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 Added 10mW circuit 1
+3.3V_RUN_GPU +3.3V_RUN_GPU KBC_PWR +3.3V_RTC_LDO +3.3V_RTC_LDO
2009/06/04 +3.3V_RUN
Check~ SSID = KBC
1
+3.3V_RTC_LDO
1
R3748
+3.3V_RTC_LDO U3703
2K2R2J-2-GP R3745
DY DY R3733
1
Do Not Stuff Do Not Stuff 4 3 KBC_SDA1
[23] SML1DAT
2
R3744
2
+3.3V_RTC_LDO R3721 Q3714_1 R3722 D3704 5 2
DY Do Not Stuff
2
10KR2J-3-GP Q3714 10KR2J-3-GP EC_PWR_SHDN 1
S
1
MMBT3904-7-F-GP KBC_SCL1 6 1 SML1CLK [23]
2
KBC_ON#
D3705 DY 3 G
1
2
2 3 THERMTRIP_VGA_R# Q3704
DY
1
R3747 [81] THERMTRIP_VGA# KBC_PWRBTN_EC# Do Not Stuff DMN66D0LDW-7-GP
[78] KBC_PWRBTN# K A 2
0R5J-5-GP
DY Do Not Stuff +3.3V_RUN
D
D Do Not Stuff
D
1
DW 1 2 KBC_PWR
KBC_PWR
07/10 Added +3.3V_RUN U3702

L3701 R3746 0R2J-2-GP
BLM18AG601SN-3GP Put 0.1uf close to VCC-GND pin pair. 1.Added circuit ,
4 3 KBC_SDA1
KBC_PWR For prevent electric leakage [39,78] THERM_SDA
VBAT
1 2 DW 5 2
2
07/02 ADD KBC_SCL1 6 1
1.ADD KA20GATE,SIO_RCIN# pull up resistor THERM_SCL [39,78]
C3703 C3714
DYDo Not Stuff 07/05
SC2D2U10V3KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Do Not Stuff
2. LCD Backlight On/Off Status are D3712
1
DMN66D0LDW-7-GP
C3702
C3706
separated by GPU,PCH,EC
1
1
C3712
C3711
C3713
C3708
C3701
C3715
2 PANEL_BKEN_GPU [81] +3.3V_RUN
DY PANEL_BKEN 3
2
115
102
88
76
46
19
80
4
U3701A 1 OF 2 1
BAT_IN# [44] PANEL_BKEN_PCH [20]
E51_RxD 1
DY 2 DW
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
GPIO41
R3725 Do Not Stuff
BAT54C-7-F-GP 07/07 Change
AGND KBC_PWR 1.Change Power rail
104 124 CAP_LOCK_LED# CAP_LOCK_LED# [66] RN3702
VREF GPIO10/LPCPD# PLT_RST1#_1 KBC_SCL1
7 3 2
AD_IA_KBC LRESET# +1.05V_VTT
[45] AD_IA_KBC
1.8_GFX_ON
97
98
GPI90/AD0 A/D LCLK
2
3
PCLK_KBC [21] KBC_SDA1 4 1
[51] 1.8_GFX_ON GPI91/AD1 LFRAME# LPC_LFRAME# [24,36,70]
THERMTRIP_VGA_R# 99 126 LPC_LAD0 SRN4K7J-8-GP
GPI92/AD2 LAD0
1
LPC_LAD1
WD [43] PS_ID_EC 100
TURBO_BOOST_ALERT#108 GPI93/AD3 LAD1
127
128 LPC_LAD2
LPC_LAD[0..3] [24,36,70]
R3737 KBC_PWR
[25] TURBO_BOOST_ALERT# GPIO05 LAD2
07/23 KBC_THERMTRIP# 2K2R2J-2-GP RN3701
1. Added R3712 100 Ohm damping resistor
96
GPIO04 LPC LAD3
1
125
LPC_LAD3
BAT_SDA 3 2
2. Added R3713 100 Ohm damping resistor SERIRQ INT_SERIRQ [24,36]
8 PM_CLKRUN# [22] C3716 BAT_SCL 4 1
Do Not Stuff
3. Added R3751 100 Ohm damping resistor
2
GPIO11/CLKRUN# THERMTRIP_GATE
122 KBRCIN# [25] 2 1
KBRST#
EC3701
[22] SUS_PWR_DN_ACK SUS_PWR_DN_ACK 101 121 KA20GATE [25] SRN4K7J-8-GP
B
R3712 1 100R2J-2-GP KB_BL_DET_R#105 GPI94 GA20 ECSCI#_KBC SCD1U16V2KX-3GP
[68] KB_BL_DET#
DGPU_PWR_EN#
2
GPI95 ECSCI#/GPIO54
29
PANEL_BKEN KBC_PWRBTN# DY
CKBC_PWR [25] DGPU_PWR_EN# 106 D/A 9 1 2
C
2
CAPA2_INT_R# GPI96 GPIO65/SMI# ECSWI#_KBC R3734 100KR2J-1-GP
107 123 [9,25,42] H_THRMTRIP# E C KBC_THERMTRIP#
GPI97 GPIO67/PWUREQ#
Pull High : Discrete KBC_THERMTRIP# 1 2
internal Pull Low for UMA Q3701 R3709 100KR2J-1-GP
1
CH3904PT-GP CAPA_RST_R# 1 2
DIS R3716
2K2R2J-2-GP
[22,34,42,50,51,86] PM_SLP_S3#
KBC_PWRBTN_EC#
64
GPIO01/TB2 GPIO74/SDA2
68 KBC_SDA1 D3702
BAS16XV2T1G-GP-U
R3718 100KR2J-1-GP
100R2J-2-GP
2 R3751 1
AC_IN_R#
95
93
GPIO03 SMB GPIO73/SCL2
67
69
KBC_SCL1
[45] AC_IN# GPIO06 GPIO22/SDA1 BAT_SDA [44,45]
[69] LID_CLOSE# LID_CLOSE# 94 70 [25] ECSWI# A K ECSWI#_KBC
BAT_SCL [44,45]
2
PCB_VER0 GPIO07 GPIO17/SCL1 +3.3V_RUN

119
SW_UMA_ID GPIO23
6
1D5V_VGA_ON GPIO24 D3703 TURBO_BOOST_ALERT#1
[87] 1D5V_VGA_ON 109 2
PCB_VER1 GPIO30 BATT_WHITE_LED BAS16XV2T1G-GP-U R3752 10KR2J-3-GP
120
GPIO31 SP GPIO66/G_PWM
81 BATT_WHITE_LED [66]
1
PWRLED# 65 WIRELESS_ON#/OFF 1 2
[66] PWRLED# GPIO32/D_PWM
R3729 [66] PWR_BTN_LED# PWR_BTN_LED# 66 [25] ECSCI# A K ECSCI#_KBC R3740 100KR2J-1-GP
Do Not Stuff KB_BL_CTRL GPIO33/H_PWM KB_BL_DET#
16 1 2
UMA [68] KB_BL_CTRL
[43] AD_OFF AD_OFF 17
GPIO40/F_PWM
84 ECSMI#_KBC R3750 10KR2J-3-GP
RSMRST#_KBC GPIO42/TCK GPIO77 D3701 KA20GATE
[22] RSMRST#_KBC 20 SPI 83 BLUETOOTH_EN [73] 1 2
2
PM_SLP_S4# GPIO43/TMS GPIO76/SHBM BAS16XV2T1G-GP-U R3743 10KR2J-3-GP

[22,34,50] PM_SLP_S4#
NUM_LOCK_LED#
21
22
GPIO44/TDI GPIO GPIO75
82
91
WIFI_RF_EN [64]
KBRCIN# 1 2
[66] NUM_LOCK_LED# GPIO45/E_PWM GPIO81 WIRELESS_ON#/OFF [64]
[46] 3V_5V_POK 3V_5V_POK 23 [25] ECSMI# A K ECSMI#_KBC R3742 10KR2J-3-GP
R3706 1 GPIO46/TRST#
[22] PM_PWROK 2 0R2J-2-GP PM_PWROK_R 24
GPIO47
Remove [62] EC_SPI_WP#_R EC_SPI_WP#_R 25
GPIO50/TDO
HDD_FALL_INT1 EC_PWR_SHDN 26 111 E51_TxD E51_TxD [64] S5_ENABLE 1 2
BLON_OUT GPIO51 GPO83/SOUT_CR/BADDR1 E51_RxD D3706 R3728 10KR2J-3-GP
[54] BLON_OUT 27 113 E51_RxD [64]
R3719 1 0R2J-2-GP IMVP_VR_ON_R GPIO52/RDY# GPIO87/SIN_CR BAS16XV2T1G-GP-U KCOL0
2 28 112 1 2
[47]
[43]
IMVP_VR_ON
PSID_DISABLE# PSID_DISABLE# 73
GPIO53 GPO84/BADDR0 AC_PRESENT_EC [22]
[78] CAPA_RST# A K CAPA_RST_R# R3714 DY Do Not Stuff
GFX_CORE_EN GPIO70 SHBM_LCDTST_EN 1
74 114 2
[86]
[24]
GFX_CORE_EN
ME_UNLOCK# ME_UNLOCK# 75
GPIO71 GPIO16
14 VTT_PWRGD_G34
PM_LAN_ENABLE [76]
1 2 VTT_PWRGD [9,49,52] R3717 DY Do Not Stuff
USB_PWR_EN# GPIO72 GPIO34 BLUETOOTH_EN
[63,76] USB_PWR_EN# 110 15 S5_ENABLE [42] 1 2
GPO82/TRIS# GPIO36 R3731 10KR2J-3-GP
SER/IR R3723 R3741
DW 0R2J-2-GP 10R2J-2-GP
PANEL_BKEN
R3739
1 2
100KR2J-1-GP
07/10 assign GPIO 44 KBC_VCORF
1.assign GPIO TUCHPANEL_STP# VCORF U3701B 2 OF 2
[22] PCH_SUSCLK_KBC 1 2
B KCOL[0..16] [68]
B
1
AGND
+3.3V_RUN
GND
GND
GND
GND
GND
GND
C3710 KBC_XI 77 53 KCOL0

SC1U10V3KX-3GP 32KX1/32KCLKIN KBSOUT0/JENK# KCOL1
52
2
NPCE781BA0DX-GP KBSOUT1/TCK KCOL2
C3710 need place near pin 44. 51
116
89
78
45
18
5
2AGND103
R3710 KBSOUT2/TMS KCOL3

50
KBSOUT3/TDI
1
Do Not Stuff
CAPA_RST_R# 2100R2J-2-GP
1 CAPA_RST_L# 79 49 KCOL4
AMP_MUTE# 32KX2 KBSOUT4/JEN0# KCOL5
[30] AMP_MUTE# 30 48
GPIO55/CLKOUT KBSOUT5/TDO
R3732
R3701 47 KCOL6
Do Not Stuff DY DY MB VERSION [47] IMVP_VR_PWRGD 63
KBSOUT6/RDY#
43 KCOL7
R3730 GPIO14/TB1 KBSOUT7 KCOL8
WD [22] PM_PWRBTN# 117 KBC 42
2
GPIO20/TA2 KBSOUT8
ID VER1 VER0 0R2J-2-GP
07/23
[54] SHBM_LCDTST_EN SHBM_LCDTST_EN31
GPIO56/TA1 KBSOUT9
41 KCOL9
PCB_VER0 [30] KBC_BEEP 32 40 KCOL10
PCB_VER1 1. Added LCD brightness control by EC GPIO15/A_PWM KBSOUT10 KCOL11
[66] BATT_ORANGE_LED 118 39
SA 0 0
1
2.Changed 1.05V_GFX_ON from GPIO72 to GPIO25 GPIO21/B_PWM KBSOUT11 KCOL12

3.Removed AMP_MUTE# [54] LBKLT_CTL_EC 62 38
GPIO13/C_PWM KBSOUT12/GPIO64 KCOL13
37
SB 0 1 KBSOUT13/GPIO63
1
36 KCOL14
KBSOUT14/GPIO62
10KR2J-3-GP
35 KCOL15
SC 1 0 KBSOUT15/GPIO61/XOR_OUT
R3711
R3708 [87] 3.3V_RUN_GPU_EN 3.3V_RUN_GPU_EN 13 34 KCOL16

10KR2J-3-GP 1.05V_GFX_ON GPIO12/PSDAT3 GPIO60/KBSOUT16 TP_KCOL17 TP3701
[87] 1.05V_GFX_ON 12 33 1
-1 1 1 [66] SCR_LOCK_LED# SCR_LOCK_LED# 11
GPIO25/PSCLK3 GPIO57/KBSOUT17
KROW[0..7] [68]
2
R3707 2 GPIO27/PSDAT2
[54] LCD_TST 1 0R2J-2-GPLCD_TST_R 10
R3720 TPDATA GPIO26/PSCLK2 KROW0
[68] TPDATA 71 54
PLT_RST1#_1 TPCLK GPIO35/PSDAT1 KBSIN0 KROW1
2 1 PLT_RST# [9,21,34,36,64,70,76,80] [68] TPCLK 72
GPIO37/PSCLK1 PS/2 KBSIN1
55
56 KROW2
0R2J-2-GP KBSIN2 KROW3
57
KBSIN3
1
58 KROW4
C3717 EC_SPI_DI KBSIN4 KROW5
86 59
DY Do Not Stuff
[62] EC_SPI_DI
R3753 1 2 0R2J-2-GP EC_SPI_DO 87
F_SDI KBSIN5
60 KROW6
KBC CLK [62] SPI_DIO
2
EC_SPI_CS# F_SDO KBSIN6

[62] EC_SPI_CS#
EC_SPI_CLK R3735 1 2 0R2J-2-GP
90
EC_SPI_CLK_C 92 F_CS0# FIU KBSIN7
61 KROW7
DW EMI PCLK_KBC
[62] EC_SPI_CLK F_SCK
2
07/07 Dummy +3.3V_RUN 85 ECRST#

1.Dummy R3736 KBC_PWR VCC_POR#
R3726
DW 07/02 Added
DY
1
Do Not Stuff 1. using the PCH 32K clk , dummy X'trail

A R3738 NPCE781BA0DX-GP A
1
2K2R2J-2-GP ECRST#
PCLK_KBC_RC
E51_TxD R3727 1st Samsung

4K7R2J-2-GP
2
2
KBC_PWR R3724
Q3709 Q3709_1 10KR2J-3-GP Wistron Corporation
1
1
1
DYR3736 MMBT3904-7-F-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
E
Do Not Stuff 1 2 C3707 Taipei Hsien 221, Taiwan, R.O.C.
[78] CAPA_INT# 2 3 CAPA2_INT_R# [39,42] PURE_HW_SHUTDOWN# 1 2 ECRST#_C B SC1U10V3KX-3GP
1
2
2
Title
www.vinafix.vn
DY C3704 R3702 Q3702
KBC Nuvoton NPCE781BA0DX
C
Do Not Stuff 0R2J-2-GP CH3906PT-GP

1

Custom
Vostro Calpella SA
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN +5V_RUN

SSID = Thermal 25mil R3912
Do Not Stuff
1
1
1
R3907 1 2
C3910 C3909 10KR2J-3-GP DY R3901
SC4D7U6D3V5KX-3GP SCD1U16V2KX-3GP DY Do Not Stuff
2
D3901
2
B0530WS-7-F-GP
EMC2102_FAN_TACH A K EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 [58]

D D
EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE [58]

25mil
RN3901
3 2 +3.3V_RUN
4 1
SRN4K7J-8-GP
DW
07/10 Del THERM_SCL [37,78]
1. Not reserve S5 power source rail for EMC2102 ?? THERM_SDA [37,78]
1. WWAN
1 EMC2102_VDD_3D3
29
28
27
26
25
24
23
22
+3.3V_RUN 2
Q3905 must be near WWAN R3908 U3901
49D9R2F-GP
GND
TACH
VDD_5Va
FANa
FANb
VDD_5Vb
SMCLK
SMDATA
2
C3912 must be near Q3905
C3905
SCD1U16V2KX-3GP
E
1
1
C3912
CH3904PT-GP B Do Not Stuff C3914
Q3905 DY SC470P50V2JN-GP 1 21
2
VDD_3V NC#21
C3914 must be
C
near EMC2102 EMC2102_DN1 2 20

DN1 GND
EMC2102_DP1 3 19 TP_ALERT# 1 TP3903 Do Not Stuff
DP1 ALERT#
Layout notice: EMC2102
VGA_THERMDC 4 18 CLK_32K
C H_THERMDA, H_THERMDC routing together, DN2 CLK_IN R3906 +3.3V_RUN
GND = Internal Oscillator Selected
C
Trace width / Spacing = 10 / 10 mil VGA_THERMDA 5 17 EMC2102_CLK_SEL 1 2

DP2 CLK_SEL +3.3V = External 32.768kHz Clock Selected
2. GPU Sensor T8_THERMDC 6 DN3 RESET# 16 TP_EM2102_RESET# 1 10KR2J-3-GP
T8_THERMDA 7 15 TP3904 Do Not Stuff

DP3 NC#15
THERMTRIP#
POWER_OK#
SYS_SHDN#
FAN_MODE
[81] VGA_THERMDC
SHDN_SEL
TRIP_SET
1
C3906
SC470P50V2JN-GP
NC#8
2
GND = Channel 1
EMC2102-DZK-GP
OPEN = Channel 3
10
11
12
13
14
[81] VGA_THERMDA
+3.3V = Disabled RN3902
EMC2102_PWROK 3 2 +3.3V_RUN
C3906 must be R3903 EMC2102_THERMTRIP# 4 1
2 EMC2102_SHDN
near EMC2102 DY 1 +3.3V_RUN SRN10KJ-5-GP
DW Do Not Stuff KBC_PWR
07/23 Removed
1
1.Removed SYSTEM Sensor Critical +3.3V_RUN
R3916 R3910
2 1 EMC2102_FAN_mode 10KR2J-3-GP +3.3V_RUN
3. CPU Sensor DY
Do Not Stuff
1
SYS_SHDN#
SHDN#_G
Layout notice : R3917
2
Both VGA_THERMDA and THERMDC routing 10KR2J-3-GP
B 10 mil trace width and 10 mil spacing. B
1
1 R3914 2
1
C3901 must be near Q3901 10KR2J-3-GP C3902 R3902
SCD1U16V2KX-3GP 10KR2F-2-GP
G
Q3903
2
2N7002A-7-GP
E
2
2
CH3904PT-GP
S D PURE_HW_SHUTDOWN# [37,42] TRIP_SET Pin Voltage
Q3901
B
DY C3901 C3903 GND = Fan is OFF V_DEGREE=(((Degree-75)/21)
Do Not Stuff SC470P50V2JN-GP V_DEGREE
OPEN = Fan is at 60% full-scale
1
C3903 must be T8 shutdown is set 88 deg-C.

C
near EMC2102 +3.3V = Fan is at 75% full-scale
1
1
3.HW T8 sensor ( CPU ) C3904 R3904
2K37R2F-GP
SCD1U16V2KX-3GP
2
Layout notice :
2
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.
DW
32K suspend clock output 07/28 Removed
1. Removed U3902 AND gate.
R3913
[22] PCH_SUSCLK_2102 D S CLK_32K_R 1 2 CLK_32K
A A
1st Samsung
Q3902 10R2J-2-GP
1
2N7002A-7-GP
G
DY C3911
Do Not Stuff Wistron Corporation
2

RUN_POWER_ON [42,52]
Title
Thermal/Fan Controllor EMC2102
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
Free Fall Sensor

Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
+3.3V_RUN - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
1
C4001 C4002
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP
2
+3.3V_RUN
C C
SA
1
U4001
1
R4004 06/25 Check
[7,18,19,23,64,76] PCH_SMBCLK 1.HDD_FALL_INT1 [ GPIO Table ]??
DY Do Not Stuff
VDD
VDD_IO
[7,18,19,23,64,76] PCH_SMBDATA
2
PCH_SMBCLK 14 8 HDD_FALL_INT1
SCL/SPC INT1 HDD_FALL_INT1 [21]
+3.3V_RUN PCH_SMBDATA 13 9 FFS_INT2_R
SDA/SDI/SDO INT2 +3.3V_RUN
1
R4001
DY Do2 NotHDD_FALL_SDO
Stuff
12 SDO
1
7 CS
2 R4005
GND
GND 4 100KR2J-1-GP
3 RESERVED#3 GND 5
11 10
2
RESERVED#11 GND
FALL_INT2
DE351DLTR8-GP
1
09/0422 +3.3V_RUN +5V_RUN
Q4002
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild DMN66D0LDW-7-GP
1
(#2) FAE/ DY is ok, chip internal pull-up resistors
6
B R4006 R4008 B
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
100KR2J-1-GP DY Do Not Stuff
Pull GND SAD is 0011100b
2
FFS_INT2_R
FFS_INT2 [59]
1
R4007
DY Do2 Not Stuff
FFS_INT2_R
FFS_INT2_R [25]
A A
1st Samsung
Note
(1) Keep all signals are the same trace width. (included VDD, GND). Wistron Corporation
(2) No VIA under IC bottom. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Free Fall Sensor
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
Remove +3.3V_DELAY power rail 2009/05/25
D D
H_THRMTRIP# [9,25,37]
E
R4214
1 2 H_PWRGD_R B
[9,25] H_PWRGOOD DY DY Q4201
1
Do Not Stuff Do Not Stuff
C
C4208
Do Not Stuff DY
2
D4201
[46] 3V_5V_EN A K
PURE_HW_SHUTDOWN# [37,39]
BAS16XV2T1G-GP-U
1
1 2 S5_ENABLE [37]
R4209
R4203 1KR2J-1-GP
Do Not Stuff
DY
2
C C
+3.3V_RTC_LDO
Peak current:5.3A
1
R4201
100KR2J-1-GP
Design current: 3.7A
+5V_RUN +5V_ALW
2
U4201
1 S D 8
2 S D 7
PS_S3CNTRL R4205 3 S D 6
[52] PS_S3CNTRL
RUN_POWER_ON 1 2 10KR2J-3-GP RUN_ON_5V 4 G D 5
+15V_ALW AO4468-GP
1
11.6A
C4204
SC6800P25V2KX-1GP Rds=14m ohm
2
3
B Q4202 B
DMN66D0LDW-7-GP R4206
100KR2J-1-GP
Peak current: 8191mA
4
Design current: 5734.6mA

+3.3V_RUN +3.3V_ALW
U4202
1 S D 8
2 S D 7
[22,34,37,50,51,86] PM_SLP_S3# RUN_POWER_ON [39,52]
R4211 3 S D 6
1 2 10KR2J-3-GP RUN_ON_3D3V 4 G D 5
FDS8880-NL-GP
1
10.7A
C4203
SCD01U50V2KX-1GP Rds=12m ohm
2
Design current: 1155mA
+1.5V_RUN +1.5V_SUS
U4204
1 S D 8
2 S D 7
R4213 3 S D 6
A G D A
1 214K7R2F-L-GP RUN_ON_1D5VR 4 5 1st Samsung
AO4468-GP
1 Wistron Corporation
11.6A
C4206
SCD01U50V2KX-1GP
2
Rds=14m ohm 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Power Plane Enable
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
+5V_ALW
1
PR4306
1
15KR2J-1-GP
PR4303 DY
E
10KR2J-3-GP PD4302
1
D PSID_PRO CH3904PT-GP Do Not Stuff D
B
3
PQ4304
2
2
PR4301
C
PR4309 PSID_DISABLE#_R 1 2
100KR2J-1-GP DY PSID_DISABLE# [37]
Do Not Stuff
G
1
PQ4303 +3.3V_ALW +3.3V_ALW
FDV301N-NL-GP
1
D S PS_ID
D
PR4304
2K2R2J-2-GP
PD4301
2
BAV99-4-GP
3
PR4310 PR4302
PS_ID_R2 1 2 1 2
[76] PS_ID_R2 DY PS_ID_EC [37]
Do Not Stuff 33R2J-2-GP
+DC_IN +DC_IN_SS
PU4301
1 S D 8
S D
SC1U25V5KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
2 7
1
S D
240KR3-GP
C 3 6 C
1
This cap should be used G D
PC4302
PC4304
PC4306
PC4305
PC4301
PC4303
PR4308
4 5
only as last resort for
DY
2 Do Not Stuff
AO4407A-GP
EMI suppression.
2
2
Id=-12A
PQ4302
PQ4301
R2
E Qg=-25nC
3 OUT AD_OFF_L B Rdson=10~38mohm
1 R1 DY
R1
C AD_OFF_R
[37] AD_OFF
IN DY 2 GND
2
R2 Do Not Stuff
PR4307
Do Not Stuff 47KR3J-L-GP
B B
A A
1st Samsung
Wistron Corporation
Title
DCIN
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D
Batt Connecter D
BATT1
GND 11
GND 10
9 1 PR4401
GND2 AFTP4406
GND1 8 2 1 KBC_PWR
7 PBAT_ALARM# 1
BAT_ALERT AFTP4403
6 470KR2J-2-GP
SYS_PRES# PBAT_PRES1# PR4402 1
BATT_PRS# 5 2 100R2J-2-GP BAT_IN# [37]
4 PBAT_SMBDAT1 4 1
DAT_SMB PBAT_SMBCLK1 PRN4401 BAT_SDA [37,45]
CLK_SMB 3 3 2 SRN100J-3-GP BAT_SCL [37,45]
BATT2+ 2
BATT1+ 1 +PBATT
PG4401
1
2 1 BATT_SENSE [45]
FOX-CON9-5-GP PC4402 PC4401
SCD1U50V3KX-GP SC2200P50V2KX-2GP Do Not Stuff
2
20.80962.009
C C
BAT_IN#
BAT_SDA
BAT_SCL
3
3
PD4401 PD4403 PD4402
BAV99-4-GP BAV99-4-GP BAV99-4-GP
1
2
+3.3V_RTC_LDO
B B
A 1st Samsung A
Wistron Corporation
Title
Batt Connecter
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = Charger
+SDC_IN +PWR_SRC
PU4501 PU4502 +PBATT
+DC_IN_SS 8 D S 1 AO4407A-GP
7 D S 2 1 2 1 S D 8
1
6 D S 3 PR4508 2 S D 7
D G S D
PR4512
D01R2512F-4-GP
100KR2J-1-GP
5 4 3 6
1
+DC_IN_SS 4 G D 5
AO4407A-GP PG4509 PG4501
2
Id=-12A
10KR2J-3-GP
D Do Not Stuff Do Not Stuff D
2
PR4527
PR4513_03
Qg=-25nC
1
Id=-12A
2
Rdson=10~38mohm PR4514
10KR2F-2-GP
+DC_IN_SS Qg=-25nC
PG4503
PG4510
PG4506
PG4512
PR4513
PR4533_02
470KR2J-2-GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
1
DY 1 Rdson=10~38mohm
2
2
PQ4502_03
1
PR4538
PQ4502_05
Do Not Stuff PR4524_03
PQ4502
316KR3F-2-GP
1
0R2J-2-GP
3 4
0R2J-2-GP
1
PR4533
PR4524
PR4520
BQ24745_ACOK 2 5
2
1 6 CHAGER_SRC
Do Not Stuff
2
DMN66D0LDW-7-GP 1 2
PC4519
Do Not Stuff
PC4545
SCD1U50V3KX-GP
Do Not Stuff
2
2 PR4522 1 CHAGER_SRC
Do Not Stuff
1
EC4502
EC4501
PC4521 CHG_AGND
1
0R2J-2-GP PC4520
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
DY
ICREF
1
PR4503
PC4528
PC4532
PC4512
PC4546
SCD1U50V3KX-GP BQ24745_DCIN 22 28 BQ24745_CSSP1 2
DY DY
Do Not Stuff
2
DCIN CSSP
5
6
7
8
2
SI4800BDY-T1-GP
BQ24745_ACIN 2 SCD1U50V3KX-GP
D
D
D
D
DY DY
PR4502 48K7R3F-1-GP
BQ24745_REF ACIN BQ24745_CSSN CHG_AGND

SCD1U10V2KX-4GP
+3.3V_RTC_LDO 27
2
BQ24745_LDO CSSN
PU4503
BQ24745_ICOUT
2 10KR2F-2-GP
11 26
2
VDDSMB ICOUT PR4534
PD4501
Do Not Stuff
1
1
PR4511
PC4513
0R3J-0-U-GP CHG_AGND
SCD01U50V2KX-1GP
1
C PR4515 BQ24745_BOOT_1 2BQ24745_BST1K C

25 1 A 1 2
Charger Current=1.4~3.6A
G
S
S
S
BOOT
1
PC4548
PR4528
0R2J-2-GP 21 BQ24745_LDO PC4531

DY
2
4
3
2
1
BQ24745_ACOK VDDP SD103AWS-1-GP SCD1U50V3KX-GP
2 1 13 ACOK
2
ACAV_IN CHG_AGND BQ24745_CHARGER_UGATE

2
UGATE 24
1
2 1 BAT_SCL_1 10 1 2 PC4517 +VCHGR1 +PBATT
[37,44] BAT_SCL SCL PL4501
PG4505 Do Not Stuff PC4522 Do Not Stuff PR4519
DY
1
23 1 2 SCD1U50V3KX-GP BQ24745_LX1 1 2 1 2
2009/08/04
Do Not Stuff
2
PHASE 0R3J-0-U-GP PR4536 IND-5D6UH-43-GP D01R2512F-3-GP
Do Not Stuff
Do Not Stuff
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2 1 BAT_SDA_1 9 BQ24745_PHASE_GND 1 2
DY [37,44] BAT_SDA DY
Do Not Stuff
SDA
PR4504
CHG_AGND PG4508 Do Not Stuff BQ24745_LGATE_1 PC4536
SCD1U50V3KX-GP
20
Do Not Stuff
LGATE
5
6
7
8
PC4511
PC4524
PC4530
PC4533
PC4523
Do Not Stuff
2
SI4800BDY-T1-GP
1
PG4502
PG4507
PD4502
2009/06/24
D
D
D
D
2 1 14 19
DY
[37] AD_IA_KBC NC#14 PGND DY
PU4505
SCD1U50V3KX-GP
2
PR4530 18 BQ24745_CSOP_1
A
CSOP
PC4514
0R2J-2-GP CHG_AGND
2
17
G
S
S
S
BQ24745_VICM CSON
8
4K7R2J-2-GP
4
3
2
1
BQ24745_FBO VICM BQ24745_PR4505
SC220P50V2JN-3GP
1
1
PR4537
PR4539
200KR2F-L-GP
0R2J-2-GP
SCD1U50V3KX-GP
Do Not Stuff
PR4505
1 2
2
PR4506
6 CHG_AGND 1 PR4532 2 BQ24745_CSOP

FBO
PC4516
BQ24745_EAI 0R2J-2-GP
1BQ24745_FBO1
5 16
2
EAI NC#16
2
PC4540 BQ24745_EAO 4
PR4526 EAO
1
PC4541
1 2SC2200P50V2KX-2GP BQ24745_REF 3 VREF
1
2 2 7K5R2F-1-GP
1PR4526_01 1 1 2 BQ24745_CE 7
1
PC4518 PR4510 CE PR4531 BQ24745_CSON
12 15
DY
GND
SC150P50V2JN-3GP 0R2J-2-GP GND VFB 0R2J-2-GP

1 2
Do Not Stuff
Do Not Stuff
2
2
B B
PC4543
BAT_SENSE 2 1
DY DY BATT_SENSE [44]
2
PC4525 PU4504
DY
29
1
PC4526
SC56P50V2JN-2GP BQ24745RHDR-GP
DY
2
1
PR4509
DY
Do Not Stuff
Do Not Stuff
2
PC4544
PR4521
2 1
PC4515 PC4537 PC4529 PC4534 DY DY
Do Not Stuff Do Not Stuff Do Not Stuff SC1U6D3V2KX-GP 0R2J-2-GP
2
2
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
+3.3V_RTC_LDO
1
PR4523
100KR2J-1-GP
2
[37] AC_IN#
SCD1U25V3KX-GP
PC4527
1
A PQ4504 A
1st Samsung
2N7002A-7-GP
2
ACAV_IN
G
Wistron Corporation
S
2009/6/9 Title
CHARGER BQ24745
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
A B C D E
+3.3V_ALW_2
51125_VCLK
1
PC4602 PC4604
SC1KP50V2KX-1GP
PC4603
PR4601 SCD1U25V3KX-GP SCD1U25V3KX-GP
100KR2J-1-GP
2
2
PD3903_1
PD3904_1
51125_ENTRIP
4 4
PQ4601
D
+PWR_SRC +PWR_SRC_3D3V 2N7002A-7-GP 51125_ENTIP1
3
1
1
PG4603
1 2 [42] 3V_5V_EN G PC4605 DY PR4602 PD4603 PD4604
Do Not Stuff
180KR2F-GP BAT54S-5-GP BAT54S-5-GP
2
Do Not Stuff
4
PG4605
1
+15V_ALW +5V_PWR
1 2 2009/08/18PQ4602 PG4610
DMN66D0LDW-7-GP
PD3903_04
+3.3V_ALW +3D3V_PWR PG4607
3
PG4602 1 2 1 2 PD3903_2
2 1
Do Not Stuff 51125_ENTIP2
1
Do Not Stuff PG4609 PC4609
1
PG4604 1 2 SC1U25V3KX-1-GP PC4607
1
Do Not Stuff
2 1 PR4603 SCD1U25V3KX-GP
2
1
Do Not Stuff 180KR2F-GP
PC4608
DY
Do Not Stuff PG4635 PC4606
2
PG4606 1 2 SCD1U25V3KX-GP
2
2 1
Do Not Stuff
2009/08/18
Do Not Stuff
2
PG4608
1
2009/08/04
+PWR_SRC_3D3V +PWR_SRC
Do Not Stuff +PWR_SRC_5V
PG4611
2 1 DIS(Auburndale) PC4612 PC4613
Do Not Stuff
SCD01U50V2KX-1GP
Design Current =8.08A
1
Do Not Stuff PC4610 PC4627 PC4611 DY
1
1
Do Not Stuff
PG4613 12.69A<OCP<15A +5V_PWR +5V_ALW

SC10U25V6KX-1GP
SC10U25V6KX-1GP
2 1 DY DIS(Auburndale) PG4614
2
D D PC4614 PC4615 PC4616
Design Current =6.58A 1 2
2
D 8
D 7
D 6
D 5
5
6
7
8
1
Do Not Stuff 2009/08/24
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
Do Not Stuff
PG4627 PU4601 PU4602 DY 10.34A<OCP< 12.22A +PWR_SRC +PWR_SRC_5V Do Not Stuff
16
2 1 SIS412DN-T1-GE3-GP SIS412DN-T1-GE3-GP PG4615
2
3 PU4603 1 2 3
Do Not Stuff PR4605 2009/08/24 PG4612
VIN
PG4626 PC4617 PR4604 0R3J-0-U-GP 1 2 Do Not Stuff
G
S
S
S
2 1 SCD1U25V3KX-GP 0R3J-0-U-GP SCD1U25V3KX-GP PG4616
S
S
S
G
PC4618 G S Do Not Stuff 1 2

1
2
3
4
4
3
2
1
Do Not Stuff S G 2 1 51125_VBST2_1 1 251125_VBST2 9
VBST2 VBST1
22 51125_VBST1 1 2 51125_VBST1_1 1 2 PG4624
PG4630
2 1 +3D3V_PWR 2009/08/04
PL4601 51125_DRVH2 10 21 51125_DRVH1
2009/08/04 +5V_PWR
1 2 Do Not Stuff
PG4617
DRVH2 DRVH1 PL4602
Do Not Stuff 1 2
Do Not Stuff 1 2 51125_LL2 11 20 51125_LL1 1 2 PG4625
IND-3D3UH-115-GP LL2 LL1 IND-2D2UH-46-GP-U Do Not Stuff
PG4634 1 2
1
51125_DRVL2 51125_DRVL1
2 1 PTC4603 PTC4601 D 12 19 PG4619
1
1
DRVL2 DRVL1
PC4619
DY D Do Not Stuff 1 2
D 8
D 7
D 6
D 5
5
6
7
8
ST100U6D3VBM-5GP
ST220U6D3VDM-15GP
Do Not Stuff PG4618 PR4606 PG4628

DY DYPR4607
D
D
D
D
Do Not Stuff
Do Not Stuff PU4604 51125_VO2 7 24 51125_VO1 PU4605 PG4620 PC4601 PTC4602 PTC4604 1 2 Do Not Stuff
151125_LL2_R
2
1
VO2 VO1
Do Not Stuff
Do Not Stuff
2009/08/04 Do Not Stuff PG4601
151125_LL1_R
2
SI7716ADN-T1-GE3-GP
SI7716ADN-T1-GE3-GP
Do Not Stuff
ST220U6D3VDM-15GP
ST100U6D3VBM-5GP
51125_FB2 5 2 51125_FB1 Do Not Stuff 1 2
DY
2
VFB2 VFB1
PG4629
2
1 2 Do Not Stuff
2
2
G
S
S
S
DYDo2 Not51125_EN 3V_5V_POK
S
S
S
G
1 13 23 PG4621
EN0 PGOOD
PR4608 Stuff G S Do Not Stuff 1 2
1
2
3
4
4
3
2
1
51125_ENTIP2 6 51125_ENTIP1
Do Not Stuff
PC4620 S G 51125_VREF ENTRIP2 ENTRIP1
1
PC4621 1
PG4631
2 Do Not Stuff
DY
2
3 15 Do Not Stuff PG4622

DY
2
VREF GND Do Not Stuff 1 2
1
SCD22U10V2KX-1GP
PC4622
51125_TONSEL 4 25 PG4633
TONSEL GND Do Not Stuff
1 2
1
PR4611 PG4632
2
1
14 18 51125_VCLK Do Not Stuff Do Not Stuff 1 2
1
PR4610 SKIPSEL VCLK
51125_SKIPSEL DY
PR4609 DY Do Not Stuff PR4612 Do Not Stuff
VREG3
VREG5
6K65R2F-GP 33KR2F-GP
1 2
TPS51125RGER-GP 51125_FB1_R
2
1 2
51125_FB2_R 74.51125.073
2
PC4624 PC4623 DY
3D3V_AUX_S5_5_51125 8
17
DYDo Not Stuff +5V_ALW2 +3.3V_RTC_LDO Do Not Stuff
2
+3.3V_ALW_2
PG4623
2
1
1 2
1
2 PR4616 PR4614 PR4615 2

PR4613 Do Not Stuff 21K5R2F-GP
10KR2F-2-GP
51125_VREF 2
DYDo1Not Stuff 100KR2J-1-GP
PR4617 Close to VFB Pin (pin2)
2
+3.3V_ALW_2 2 1 3V_5V_POK [37]
2
SC22U6D3V5MX-2GP
0R2J-2-GP
PC4625
PC4628
51125_VREF 2 PR4618
1
1
0R2J-2-GP PC4626
SC4D7U10V5KX-4GP
Close to VFB Pin (pin5)

SC10U10V5KX-2GP
2 PR4619
1
+3.3V_ALW_2 DY
2
Do Not Stuff
2 PR4621
1
DY Do Not Stuff I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 20 mohm Isat =14Arms 68.2R210.20B
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L +3.3V_ALW_2 +3.3V_RTC_LDO O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 11.8mohm Isat =16Arms 68.3R310.20C O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
PR4620
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L 1 2
H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37
0R2J-2-GP
H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37
TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND

GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND
Operating
1 enable both 1
Mode enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
turn on switcher channels
switcher 1st Samsung
channels
Wistron Corporation
Title

TPS51125_5V/3D3V Rev
Custom DW Calpella X00
A B C D E
www.vinafix.vn
5 4 3 2 1
PM_DPRSLPVR [12]
+PWR_SRC [7] VR_CLKEN#
IMVP_VR_ON [37]
PR4736 +5V_ALW
0R2J-2-GP +PWR_SRC
1 CPU_VID[6..0] [12] 2 1
1
TC4701 TC4702
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
2
SC1U10V2KX-1GP
+3.3V_RUN
DY Do Not Stuff DY
Do Not Stuff
PC4735
2
2
PC4737 PC4738 PC4733 PC4734
1
BOOT3 1 2 6208_PHASE3
6208_FCCM
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
PR4735
D 2D2R3J-2-GP D
2
2
5
6
7
8
PU4702
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
D
D
D
D
5
1
PC4736
SIS406DN-T1-GE3-GP
SCD22U16V3KX-1-GP
BOOT
VCC
1
2
2
2 7 PHASE3
PWM PHASE
S
S
S
UGATE3
6208_PWM
G
UGATE 8
PR4747 4 LGATE3
4
3
2
1
1K91R2F-1-GP LGATE
6 FCCM
GND
GND
1
62883_DPRSLPVR 1
1
PR4744
PR4745
PR4737
PR4738
PR4746
PR4739
PR4740
PR4741
PR4742
PR4743
UGATE3
2
L4701
+VCC_CORE
62883_CLK_EN#
PU4705 ISL6208CRZ-TGP-U
9
3
62883_VR_ON
PHASE3 1 2
62883_VID6
62883_VID5
62883_VID4
62883_VID3
62883_VID2
62883_VID1
62883_VID0
ST330U2VDM-4-GP
ST330U2VDM-4-GP
1
DY IND-D36UH-24-GP
1
PTC4701
PTC4702
Do Not Stuff
Do Not Stuff
5
6
7
8
PU4703 PR4701
D
D
D
D
+3.3V_RUN Do Not Stuff
2
1
1
SIS402DN-T1-GE3-GP
SNUBBER32
2
PG4713
PG4714
40
39
38
37
36
35
34
33
32
31
1
PU4701 PR4750
PR4749 0R2J-2-GP
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
2
+1.05V_VTT
S
S
S
1K91R2F-1-GP
G
+5V_ALW
4
3
2
1
PR4753 2009/07/29
2
1
1
62883_PGOOD 1 BOOT2 Do Not Stuff
+VCC_CORE_PHASE3
1 2 PGOOD BOOT2 30 BOOT2 [48]
PR4751 [37] IMVP_VR_PWRGD PR4748 0R2J-2-GP LGATE3 PC4701
2 1 DY
PHASE3_R
68R2-GP 1 2 62883_PSI# 2 29 UGATE2 Do Not Stuff
[12] PSI# UGATE2 [48]
2
PSI# UGATE2
1
PR4752 0R2J-2-GP
C 62883_AGND 1 2 62883_RBIAS 3 28 PHASE2 PHASE2 [48] PR4755 DY C
2
RBIAS PHASE2 0R3J-0-U-GP

NTC 470K close to H/S MOSFET of Phase1 PR4754 147KR2F-GP
4 27 ISEN3 1 2
[9] H_PROCHOT# VR_TT# VSSP2 PR4756 51KR2F-L-GP
2
1 6266A_NTC_R 2PR4758 2009/07/29 62883_NTC LGATE2 VSUM+ 2009/07/29
62883_AGND PR4757
2 DY 1
Do Not Stuff DY 5 NTC LGATE2 26 LGATE2 [48] 1
PR4759
2
3K65R3F-GP
Do Not Stuff 1 62883_VW 62883_VCCP VSUM-
62883_AGND DYDo2 Not Stuff 6 VW VCCP 25 1
PR4760
2
1R2F-GP
PC4739 1 2 62883_COMP 7 24 62883_PWM3 PC4741 PC4742 ISEN1 1 2
COMP PWM3/LGATE1#
1
SC1U10V2KX-1GP
PR4761 PR4762 51KR2F-L-GP
SC1U10V2KX-1GP
8K06R2F-GP 62883_FB 8 23 LGATE1 LGATE1 [48] ISEN2 1 2
FB LGATE1 PR4763 51KR2F-L-GP
2
1 2 ISEN3 9 22
PC4740 ISEN3/FB2 VSSP1
SC1000P50V3JN-GP-U ISEN2 10 21 PHASE1 PHASE1 [48]
PC4743 ISEN2 PHASE1
UGATE1
SCD22U25V3KX-GP
1 1 PC4745
BOOT1
ISUM+
ISEN1
ISUM-
SCD22U25V3KX-GP
VSEN
IMON
41
VDD
RTN
GND
VIN
1 2 2
DY 2 1 2
2
62883_AGND PR4764 PC4744
Do Not Stuff SC33P50V2JN-3GP ISL62883HRTZ-T-GP PC4746
11
12
13
62883_ISUM- 14
15
16
17
18
19
20
VSUM-
VSUM-
62883_AGND SCD22U16V3KX-1-GP 2009/07/29
1
UGATE1 UGATE1 [48]
ISEN3 1 262883_COMP_R 1 ISEN1
DY 2 1 2
62883_VDD
62883_VIN
Intel support POC (power on current).

VSUM+
PC4747 PC4748 PR4766 62883_BOOT1 1 PR4767 2 BOOT1_PHASE1

Do Not Stuff SC150P50V2JN-3GP 324KR2F-GP 2009/07/29 PC4749 1 IMVP_IMON 2D2R3J-2-GP
+PWR_SRC
IMVP_IMON [12]
SCD22U25V3KX-GP 2 1 2 PR4794 +1.05V_VTT
VSUM-
PR4768 0R2J-2-GP 1 DY 2 +1.05V_VTT

62883_FB_VSEN +5V_ALW Do Not Stuff
1
PR4781
1 2 PC4750
B PC4751 1R2F-GP SCD22U10V2KX-1GP B
1
6K65R2F-GP
1 2 1 2 PC4752 PC4753 PR4769 PR4770 PR4771 PR4772 PR4773 PR4774 PR4775 PR4776 PR4777 PR4778
1
SC1U10V2KX-1GP
SCD22U25V3KX-GP
PR4779
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
Do Not Stuff
Do Not Stuff
1KR2J-1-GP
Do Not Stuff
1KR2J-1-GP
Do Not Stuff
562R2F-GP SC390P50V2KX-GP PR4797
2
2
1
PR4780
2 VCC_SENSE_L
1K91R2F-1-GP
2 1 2009/07/29 DY DY DY DY
VSS_SENSE [12]
2009/07/29 0R2J-2-GP
2
62883_AGND 62883_AGND
VSUM+ [48] CPU_VID0
CPU_VID1
1
1
CPU_VID2
[48] ISEN1 ISEN1 PC4754 PR4782 PC4756 PC4757 PR4783 CPU_VID3
2
SC330P50V2KX-3GP 82D5R2F-1-GP 2K61R2F-1-GP CPU_VID4

2
SCD33U16V3KX-1GP
SCD01U16V2KX-3GP
ISEN2 CPU_VID5
11KR2F-L-GP
[48] ISEN2
1
PR4784
CPU_VID6
1VSUM_RR
VSUM_RC 2
[48] ISEN3 ISEN3 PM_DPRSLPVR

62883_AGND PSI#
[12] VCC_SENSE
PR4785 PR4786 PR4787 PR4788 PR4789 PR4790 PR4791 PR4792 PR4793
2
1
1
PC4759
Do Not Stuff
Do Not Stuff
Do Not Stuff
1KR2J-1-GP
1KR2J-1-GP
Do Not Stuff
1KR2J-1-GP
Do Not Stuff
1KR2J-1-GP
SC330P50V2KX-3GP PR4795
2
PC4758 NTC-10K-26-GP DY DY DY DY DY
2
[12] VSS_SENSE SCD01U25V2KX-3GP

1
2
1 2 VSUM- VSUM- [48]
1
PC4760 PR4796 2K21R2F-GP NTC 10K close to Choke of Phase1

SC1000P50V3JN-GP-U 2009/07/29
1
2
PC4762
SCD1U25V2KX-GP 62883_AGND
2
A 62883_AGND A
1st Samsung
62883_AGND
PR4798
Do Not Stuff Wistron Corporation
1 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
62883_AGND ISL62883_CPU_CORE_1/2
Custom
DW Calpella X00
5 4
www.vinafix.vn 3 2
1
Sheet 47 of 88
5 4 3 2 1
+PWR_SRC
PC4863 PC4864 PC4865 PC4866
1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
2
2
D D
5
6
7
8
PU4801
D
D
D
D
SIS406DN-T1-GE3-GP
DIS(Auburndale)
Design Current = 34A
Peak Current=48A
S
S
S
G
57.6A<OCP< 67.2A
4
3
2
1
L4801
UGATE2 +VCC_CORE
[47] UGATE2
PHASE2 1 2
[47] PHASE2
ST330U2VDM-4-GP
IND-D36UH-24-GP
1
PTC4802
PTC4801
Do Not Stuff
Do Not Stuff
5
6
7
8
BOOT2 1 2B00T2_R 1 2 PU4803
[47] BOOT2 DYPR4815
D
D
D
D
SE330U2VDM-6-GP
PR4812 PC4867
2
1
1
SIS402DN-T1-GE3-GP
2D2R3J-2-GP SCD22U16V3KX-1-GP Do Not Stuff
1SNUBBER2
PG4801
PG4802
2
2
S
S
S
4 G
3
2
1
2009/07/28
PC4802
LGATE2 Do Not Stuff
PHASE2_R
DY
+VCC_CORE_PHASE2
2
[47] LGATE2
C C
ISEN2 1 2
[47] ISEN2 PR4801 51KR2F-L-GP
VSUM+ 1 2 2009/07/28
[47] VSUM+ PR4802 3K65R3F-GP
VSUM- 1 2
[47] VSUM- PR4803 1R2F-GP
ISEN1 1 2
ISEN3 1 2
+PWR_SRC
1
1
PC4868 PC4869 PC4870 PC4871
SCD1U50V3KX-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
2
5
6
7
8
PU4802
D
D
D
D
SIS406DN-T1-GE3-GP
S
S
S
G
B B
4
3
2
1
L4802
UGATE1 +VCC_CORE
[47] UGATE1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
PHASE1 1 2
[47] PHASE1 Inductor: 0.36UH ETQP4LR36WFC PANASONIC 1.1mohm/ 68.R3610.20A
O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L
IND-D36UH-24-GP
1
1
PTC4803 PTC4804 O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L
DYPR4816 H/S: SiR474DP/ POWERPAK-8/ 10mOhm/12mOhm @4.5Vgs/ 84.00474.037
5
6
7
8
SE330U2VDM-6-GP
SE220U2VDM-12GP
PU4804
2
2
D
D
D
D
Do Not Stuff L/S: Si7170DP/ POWERPAK-8/ 3.6mOhm/4.3mohm@4.5Vgs/ 84.07170.037

Do Not Stuff
Do Not Stuff
SIS402DN-T1-GE3-GP
1SNUBBER1
Freq=300KHz@PER PHASE
2
1
PG4803
PG4804
S
S
S
LGATE1
G
[47] LGATE1
2009/07/28
4
3
2
1
PC4803
Do Not Stuff
DY
2
+VCC_CORE_PHASE1
PHASE1_R
2009/07/28
ISEN1 1 2
VSUM+ 1 2 2009/07/28
[47] VSUM+ PR4808 3K65R3F-GP
A A
VSUM- 1 2 1st Samsung
[47] VSUM- PR4809 1R2F-GP
ISEN2 1 2
[47] ISEN3
ISEN3 1 2 Wistron Corporation
PR4811 51KR2F-L-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
ISL62883_CPU_CORE_2/2
www.vinafix.vn
Custom
DW Calpella X00
5 4 3 2 1
5 4 3 2 1
D
+PWR_SRC +PWR_SRC_1D05V TPS51218 for +1.05V_VTT D
PG4902
1 2
Do Not Stuff
PG4903
1 2
+PWR_SRC_1D05V
Do Not Stuff
PG4904
1 2
Do Not Stuff +1.05V_VTT_P +1.05V_VTT +1.05V_VTT_P +1.05V_VTT
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PG4905
1 2 PG4908 PG4909
2
DIS(Arrandale 1.05V_VTT) 1 2 1 2
PC4924
PC4909
PC4903
PC4904
PC4902
PC4905
Do Not Stuff
PG4906 Design Current = 22.75A Do Not Stuff Do Not Stuff
1
5
6
7
8
5
6
7
8
1 2 PU4902 PU4905 31.28A<OCP<36.96A PG4910 PG4901
D
D
D
D
D
D
D
D
1 2 1 2
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
Do Not Stuff
2009/08/24 Do Not Stuff
PG4911
Do Not Stuff
PG4912
1 2 1 2
S
S
S
S
S
S
G
G
2009/08/18
[9,37,52] VTT_PWRGD
PU4901 PC4906 Do Not Stuff Do Not Stuff
4
3
2
1
4
3
2
1
PR4901 SCD1U25V3KX-GP PG4913 PG4914
PR4902 1 11 2D2R3J-2-GP 1 2 1 2
51218_VTT_TRIP PGOOD GND 51218_VBST_VTT
1 2 2 10 1 2 51218_VBST_VTT1 2 1 PL4901
80K6R2F-GP 51218_VTT_EN TRIP VBST 51218_DRVH_VTT +1.05V_VTT_P Do Not Stuff Do Not Stuff
3 9
51218_VTT_VFB EN DRVH 51218_SW_VTT PG4915 PG4916
C 4 VFB SW 8 1 2 C
PR4921 1 2 51218_VTT_CCM 5 7 +5V_ALW IND-D56UH-12-GP 1 2 1 2
[50,51] RUNPWROK CCM V5IN
Do Not Stuff
SC4D7U6D3V5KX-3GP
SCD1U10V2KX-4GP
0R2J-2-GP 6 51218_DRVL_VTT PC4901 PC4910 PTC4902 PTC4901 PTC4903
DRVL
1
1
PG4921
SE330U2VDM-L-GP
SE330U2VDM-L-GP
Do Not Stuff
PC4908 PR4904 Do Not Stuff PG4917 PG4918
DY DY
1
1
PC4907
SC1KP50V2KX-1GP
PR4903 TPS51218DSCR-GP-U SC1U10V2KX-1GP 1 2 1 2
2
470KR2F-GP
5
6
7
8
5
6
7
8
PU4903 PU4904 2009/08/05 Do Not Stuff Do Not Stuff
2
1 51218_SW_GND_VTT 2
D
D
D
D
D
D
D
D
PG4919 PG4920
1 +1.05V_VTT_VOUT 2
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
1 2 1 2

1 2 PG4925 PG4927
DY VTT_SENSE [12]
S
S
S
S
S
S
G
G
1 2 1 2
PR4912
Do Not Stuff
4
3
2
1
4
3
2
1
Do Not Stuff Do Not Stuff Do Not Stuff
PG4926 PG4928
+3.3V_RUN 1 2 1 2
10KR2F-2-GP
PC4911
PR4905
DY R1 PG4933 PG4923
2
+3.3V_ALW
Vout=0.704V*(R1+R2)/R2 1 2 1 2
2
1
PG4934 PG4944
1
PR4908 1 2 1 2
PR4907 100KR2J-1-GP
10KR2J-3-GP 51218_VTT_VFB Do Not Stuff Do Not Stuff
PG4939 PG4930
2
PQ4901
1 2 1 2
2
20KR2F-L-GP
1 6
B Do Not Stuff Do Not Stuff B
1
VTT_PWRGD 2 5 H_VTTPWRGD_R
+1.05V_VTT
PR4906
R2
3 4
1
PC4912
1
SCD1U25V3KX-GP
2
DMN66D0LDW-7-GP PR4909
2
1KR2J-1-GP
2
H_VTTPWRGD
H_VTTPWRGD [9]
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
Frequency setting O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
470K -->290KHz H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
200K -->340KHz
100K -->380KHz
39K -->430KHz
A A
1st Samsung
Wistron Corporation
Title
TPS51218_+1.05V_VTT
Custom
DW Calpella X00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW PR5012 1 2 0R2J-2-GP 0D75V_EN
[22,34,37,42,51,86] PM_SLP_S3# 0D75V_EN [52]
PR5006
1
5D1R3J-GP
+5V_ALW
2009/08/18
D PR5007 D
2
TPS51116_VDD
1 2 DW
1
+5V_ALW
SC1U10V3KX-3GP
12K4R2F-GP 07/08 Del PC5001
DY
1
1. Not reserve 1.5V_RUN_EN ?? Do Not Stuff
2009/08/05
PC5019
1 2
2
1
SC1U10V3KX-3GP
1
PC5003 PC5018
2
+3.3V_ALW SC1KP50V2KX-1GP PD5001
+PWR_SRC_1D5V
DY
Do Not Stuff
2009/08/05
2
TPS51116_VDD_R
2
16
14
15
PR5004 PU5002 +PWR_SRC +PWR_SRC_1D5V
20KR2F-L-GP PG5002
VDDP
VDDP
ILIM
PR5003 2 1 PR5014 1 2 0R2J-2-GP 1D5V_EN
[22,34,37] PM_SLP_S4#
22 TPS51116_VBST 1 2 TPS51116_VBST1
1
BST Do Not Stuff

[49,51] RUNPWROK 13
1
PGD 0R3J-0-U-GP PG5004
PR50111 2 Do Not Stuff TPS51116_NC#12 21 TPS51116_UGT PC5022
DY 12
NC#12 DH
2 1
DY Do Not Stuff
2
1D5V_EN 11 Do Not Stuff
EN/PSV PG5006
0D75V_EN 10 20 TPS51116_PHS 2 1 +1.5V_SUS_P +1.5V_SUS
RT: Non_ASM VTTEN LX PG5001
TI: ASM 23 Do Not Stuff 1 2
+1.5V_SUS_P VTTIN PG5008
1
19 TPS51116_LGT 2 1 Do Not Stuff

PC5002 DL PG5003
7
C +5V_ALW SC1U10V3KX-3GP NC#7 Do Not Stuff C
1 2
2
PR50011 2 Do Not Stuff TPS51116RGER-GP-U

DY 1 18 Do Not Stuff
+1.5V_SUS_P PGND2 PGND1 PG5005
17
PR50021 TPS51116_TON PGND1
2 0R2J-2-GP 4 1 2
TON TPS51116_VDDQSNS
8
2
VDDQS Do Not Stuff

PC5017 24 9 TPS51116_VDDQSET
2009/08/05 PG5007
Do Not Stuff DY VTT FB
1 2
1
+0D75V_DDR_P 2 +5V_ALW PR5005

VTTS +PWR_SRC_1D5V Do Not Stuff
6 1 2
VCCA DY
VSSA
PG5009
GND
REF
Do Not Stuff 1 2
1
DIS(Auburndale)
DY PC5020 Do Not Stuff
Design Current = 11.82A
25
+V_DDR_REF Do Not Stuff PG5011
2
18.57A<OCP<21.95A
PC5007
1 2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
1TPS51116_REF
1 PR5013 2
PC5035
PC5004
PC5005
PC5006
2
1
PG5012
5
6
7
8
5
6
7
8
PU5003 PU5009 1 2
2
D
D
D
D
D
D
D
D
Design Current = 0.7A
SIS406DN-T1-GE3-GP
Do Not Stuff
Do Not Stuff
PG5013
PC5021 DY 1 2
+0D75V_DDR_P SCD033U16V3KX-GP
2
S
S
S
S
S
S
Do Not Stuff
G
PG5019
4
3
2
1
4
3
2
1
1 2
B +0D75V_DDR_P +0.75V_DDR_VTT +1.5V_SUS_P B
PC5008
PC5009
PC5010
PC5011
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
PG5014 TPS51116_UGT Do Not Stuff

PL5001
1
1 2 PG5020
TPS51116_VBST1 1 2 TPS51116_PHS 1 2 1 2
Do Not Stuff
2
PG5015 PC5012 IND-1D5UH-34-GP Do Not Stuff
SC4D7U6D3V5KX-3GP
1
1 2 SCD1U25V3KX-GP PG5021
SCD1U10V2KX-4GP
PTC5001 PTC5002
PC5013
PC5014
1 2
5
6
7
8
5
6
7
8
1
Do Not Stuff PU5001 PU5008 PR5008
DY DY
D
D
D
D
D
D
D
D
SE220U2VDM-8GP
Do Not Stuff
PG5016
SIS402DN-T1-GE3-GP
Do Not Stuff
PG5022
2
Do Not Stuff
DY 1 2
1
TPS51116_LGT TPS51116_PHS_SET 2009/08/18 Do Not Stuff
1
S
S
S
S
S
S
State S3 S5 VDDR VTTREF VTT
G
DY PC5015
4
3
2
1
4
3
2
1
S0 Hi Hi On On On Do Not Stuff
2
S3 Lo Hi On On Off(Hi-Z)
TPS51116_VDDQSNS
1
S4/S5 Lo Lo Off Off Off
1
PR5009 DY PC5016
30KR2F-GP Do Not Stuff
2
2
TPS51116_VDDQSET
1
VDDQSET VDDQ (V) VTTREF and VTT NOTE
A 1st Samsung A
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PR5010
GND 2.5 VVDDQSNS/2 DDR Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D 30KR2F-GP
Wistron Corporation
2
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L0 Close to VFB Pin (pin5)
V5IN 1.8 VVDDQSNS/2 DDR2 H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V Switching freq-->400KHz Title
TPS51116_+1.5V_SUS
Custom
DW Calpella X00
Date: Thursday, September 03, 2009 Sheet 50 of 88
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN +3.3V_ALW
D PG5102 D
2 1
+5V_ALW Do Not Stuff

PG5103
2 1
SC1U10V3KX-3GP
Do Not Stuff
SC10U6D3V5MX-3GP
1
1
PC5102
PC5104
PC5103
Do Not Stuff
DY DIS(Arrandale) +1.8V_RUN_P +1.8V_RUN
2
Design Current =0.57A
PG5104
1 2
6
PU5102
Do Not Stuff
VCNTL
1D8V_VIN PG5105
[49,50] RUNPWROK 7 POK VIN#5 5
9 +1.8V_RUN_P
2009/07/29 1 2
PR5102 VIN#9
[22,34,37,42,50,86] PM_SLP_S3# 1 21D8V_RUN_EN 8 EN VOUT#3 3 Do Not Stuff
SC22U6D3V5MX-2GP
VOUT#4 4
SC68P50V2JN-1GP
PC5106
PC5107
Do Not Stuff
2K2R2J-2-GP
1
PR5104
15KR2F-GP
PC5108
2
DY
GND
FB
2
5912_1.8V_RUN_FB
APL5930KAI-TRG-GP
2
SO-8-P
C C
Do Not Stuff
1
PC5105
DY
2
Vout=0.8V*(R1+R2)/R2
1
PR5105
12KR2F-L-GP
2
2009/07/29
RT9025 for +1.8V_RUN_GPU +3.3V_ALW
PG5109
1 2
Do Not Stuff
PG5106
+3D3V_1D8_LDO 1 2
DIS:
1
DY Do Not Stuff
B PC5111
Do Not Stuff
PC5109
SC10U10V5KX-2GP
Peak current:300mA B
2
Design current:210mA
+1.8V_PWR +1.8V_RUN_GPU
PG5108
PU5103 1 2
DGPU_1D8V_PGOOD 1 8 Do Not Stuff

[23,25] DGPU_1D8V_PGOOD PGOOD GND
1 2 RT9025_EN 2 7 PG5107
[37] 1.8_GFX_ON EN ADJ
3 VIN VOUT 6 1 2
4 5
GND
VDD NC#5
1
1
PR5106 PC5113 PC5114 PC5110 Do Not Stuff
0R2J-2-GP PC5115 PR5107
DY
SC100P50V2JN-3GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
Do Not Stuff RT9025-25PSP-GP 15KR2F-GP
2
2
2
RT9025_FB
1
+5V_ALW
PR5108
12KR2F-L-GP
1
PC5112
SC1U16V3KX-2GP 2
Vo=0.8*(1+(R1/R2))
2
A A
1st Samsung
Wistron Corporation
Title
APL5930/RT9205
www.vinafix.vn
Custom
DW Calpella X00
5 4 3 2 1
5 4 3 2 1
+0.75V_DDR_VTT
D D
1
R5211
DY Do Not Stuff
Q5204_D 2
R5210
Do Not Stuff
1 2 0D75V_EN
[9,37,49] VTT_PWRGD DY 0D75V_EN [50]
D
Q5203 Q5204
[42] PS_S3CNTRL
PS_S3CNTRLG DY Do Not Stuff PS_S3CNTRL G
2N7002A-7-GP
S
C C
Calpella Platform S3 Power Reduction Platform
S3 Power Reduction CRB Implementation
Design Details
Revision 0.1
MAX Current 3000 mA

DW
07/07 Added +1.5V_CPU
Design Current 2100 mA 1.Added discharge circuit
+1.5V_CPU: +1.5V_SUS +1.5V_CPU
1
R5226
R5215 1 2 0R3J-0-U-GP
DY Do Not Stuff
R5222 1 2 0R3J-0-U-GP
Q5202_D 2
R5223 1 2 0R3J-0-U-GP
AO3420-GP MAX 6 A
D
Rds(on) = 24 mOhm (Max) Q5202
Vgs(max)=+/-12V 2N7002A-7-GP
PS_S3CNTRL G
D S
B B
S
Q5205 AO3420-GP
R5221
G
Do Not Stuff 1
RUN_POWER_ON 1 2 1.5V_CPU_ENABLE C5210

[39,42] RUN_POWER_ON DY DY Do Not Stuff
2
1
R5225
470KR2F-GP C5209
SCD01U50V2KX-1GP
2
2
DW
07/20 corrected
1. Removed C5288
2. RemovedQ5207,R5225,R5220 to save more part counts
A A
1st Samsung
Wistron Corporation
Title
DC to DC 1D5V
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = CPU.GFX.Regulator
D D
+PWR_SRC +PWR_SRC_CPU_GFXCORE +5V_ALW
PG5302 PR5302 1 2 0R2J-2-GP 3211_VID6

[13] GFX_VID6
1 2
PR5303 1 2 0R2J-2-GP 3211_VID5
[13] GFX_VID5
Do Not Stuff
PG5303 PR5304 1 2 0R2J-2-GP 3211_VID4
[13] GFX_VID4
1 2
1
PR5305 1 2 0R2J-2-GP 3211_VID3
[13] GFX_VID3
Do Not Stuff
PG5305 PR5307 1 2 0R2J-2-GP 3211_VID2 PR5306
[13] GFX_VID2 10R3J-3-GP
1 2
PR5308 1 2 0R2J-2-GP 3211_VID1
[13] GFX_VID1
2
Do Not Stuff
PG5307 PR5309 1 2 0R2J-2-GP 3211_VID0
[13] GFX_VID0 +PWR_SRC_CPU_GFXCORE
1 2
PR5301 1 2 Do Not Stuff
Do Not Stuff
+1.05V_VTT DY
PG5309 1 2 3211_GFX_VR_EN
[13] GFX_VR_EN
PR5310 0R2J-2-GP
SC1U10V2KX-1GP
1 2
1
Do Not Stuff +1.05V_VTT PR5311
1
4K7R2J-2-GP PC5305 PC5303 PC5304 PC5306
5
6
7
8
1
PC5301
D
D
D
D
1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD01U25V2KX-3GP
PU5302
2
PR5312 SI7686DP-T1-GP
2
+3.3V_ALW
DY Do Not Stuff
GND_3211_I UMA
GND_3211_I
Thermal Design Current = 12A
G
S
S
S
32
31
30
29
28
27
26
25
[13] GFX_IMON PR5313 PU5301 Max. Current = 22A
4
3
2
1
1
10KR2J-3-GP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
PR5314 24.2A<OCP<28.6A
5K9R2F-GP
2009/08/28 PC5308
C C
1
SCD22U16V3KX-2-GP
PC5307 3211_PWRGD 1 24 3211_VCC +CPU_GFXCORE
2
PWRGD VCC 3211_BST PR53151
2009/08/05 1 2 2 IMON BST 23 2 1R3J-L1-GP 3211_BST_1 1 2 PL5301
3 22 3211_DRVH 3211_DRVH
SC68P50V2JN-1GP 3211_FBRTN CLKEN# DRVH 3211_SW
4 21 1 2
3211_FB FBRTN SW IND-D56UH-12-GP
5 20 +5V_ALW
3211_COMP FB PVCC 3211_DRVL
6 COMP DRVL 19
7 18
SC3D3U10V5KX-2GP
SC47P50V2JN-3GP
+5V_ALW GPU PGND
1
1 2 3211_ILIM 8 17 PR5317
SC220P50V2JN-3GP
Do Not Stuff
ILIM GND
5
6
7
8
33 PU5303
CSCOMP
Do Not Stuff
Do Not Stuff
GND
D
D
D
D
1
1
SIR460DP-T1-GE3-GP
PR5316 9K09R2F-GP PC5310 PTC5302 PTC5301 PC5312 PC5313
DY
CSREF
RAMP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
LLINE
CSFB
PC5309 PC5311 PG5323 PG5324
IREF
RPM
1
2009/08/05
RT
SCD01U25V2KX-3GP
2
13211_SW_GND 2
SC1U10V2KX-1GP
PR5318 PC5314 20KR2F-L-GP 3211_CSCOMP GND_3211_I
9
10
11
12
13
14
15
16
S
S
S
2 3211_PC53141 ADP3211MNR2G-GP
G
1 2 1 2
2
4
3
2
1
1KR2F-3-GP PR5319 1 2 3211_IREF
Do Not Stuff
SC470P50V2KX-3GP PR5320 80K6R2F-GP
3211_CSCOMP
1 2 3211_RPM
3211_CSREF
3211_LLINE
3211_RAMP
3211_CSFB
PR5322 237KR2F-GP 3211_DRVL PC5315
1 2 3211_RT
DY
PR5323 340KR2F-1-GP 2009/08/05
2
GND_3211_I
SC1KP50V2KX-1GP
PC5316
2
+PWR_SRC_CPU_GFXCORE 2 13211_RAMP_1 1 2
PR5325 422KR2F-1-GP
PR5326 PR5327 PR5328
PR5324
1KR2F-3-GP 1 2 3211_CSCOMP_1 1 2 1 2 3211_SW_L
1
B GND_3211_I PC5317 110KR2F-GP B

SC1000P100V3KX-GP PC5318 PC5319 178KR3F-GP 64K9R2F-1-GP
2
SC270P50V2KX-1GP
SC1KP50V2KX-1GP
2009/08/05
3211_FB_1
PR5330
1
NTC-220K-2-GP
Do Not Stuff
1
GND_3211_I 1 2
DY
2
2
PR5329
PG5319
2
PR5335 2009/08/05
1 2 3211_VSENSE 1 2 +CPU_GFXCORE
1
100R2F-L1-GP-U Do Not Stuff

0R2J-2-GP
PR5333
2
PR5331 1 2 0R2J-2-GP VCC_AXG_SENSE [13]

3211_CSCOMP
PC5320
PR5332 1 2 0R2J-2-GP SC1KP50V2KX-1GP
VSS_AXG_SENSE [13]
2
PG5320
PR5336 GND_3211_I
1 2 3211_VSS_GND1 2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
100R2F-L1-GP-U Do Not Stuff
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
A A
1st Samsung
PG5325
1 2
Wistron Corporation
Do Not Stuff
GND_3211_I Title
2009/08/03 ADP3211 CPU_GFXCORE
Custom DW Calpella UMA X00
5 4 3 2 1
www.vinafix.vn
+3.3V_RUN +3.3V_RUN_GPU
SSID = VIDEO Close PCH Close GPU
SSID = Inverter
2
1
2
1
RN5404 RN5409
SRN2K2J-1-GP SRN2K2J-1-GP
DW
07/07 Added
1.Added LVDS DDC CLK/DAT Pull Hi
3
4
3
4
[20] L_DDC_DATA [81] LDDC_DATA
[20] L_DDC_CLK [81] LDDC_CLK INVERTER POWER
UMA/DIS LVDS DDC CLK/DAT select circuit
+PWR_SRC_LCD +PWR_SRC
+3.3V_RUN
U5444
F5401
2 1
3 4 LDDC_DATA_CON
[81] LDDC_DATA B0 A
1
2 5 POLYSW-1D1A24V-1-GP
GND VCC EDID_SELECT# C5401 C5405
[20] L_DDC_DATA 1 B1 S 6
SC1KP50V2KX-1GP SCD1U50V3KX-GP DY EC5403
Do Not Stuff
2
H=>B1 -iGPU PCH (UMA)
NC7SB3157P6X-1GP
L=>B0 -dGPU GPU (DIS) 73.03157.C0H
LDDC_DATA_CON
[23,55] EDID_SELECT# EDID_SELECT# LDDC_CLK_CON
1
+3.3V_RUN
U5445
DY DY EV @ LVDS side
2
3 4 LDDC_CLK_CON
[81] LDDC_CLK B0 A
2 GND VCC 5
1 6 EDID_SELECT#
[20] L_DDC_CLK B1 S C5414 C5415
NC7SB3157P6X-1GP
73.03157.C0H
SSID = VIDEO
LVDS CONNECTOR +LCDVDD
20.F1555.030 +LCDVDD
+PWR_SRC_LCD
SCD1U10V2KX-4GP
JAE-CON30-5-GP-U
37 32
1
C5402
NP2
1
30 +3.3V_RUN C5403 C5406
SC10U6D3V5KX-1GP SCD1U10V2KX-4GP
29 WD
2
28
LCD POWER
2
1
27 07/05
26
25
DYR5410
Do Not Stuff 2. LCD Power Enable control are separated by GPU,PCH,EC
07/23
36 24 1. Added LCD brightness control by EC
23 +3.3V_EEPROM 1 2 +3.3V_RUN 07/28
2
22 LCD_BRIGHTNESS R5404 33R2J-2-GP LCD_BRIGHTNESS 1. Removed LCD brightness control with EC and GPU
21
20 BLON_OUT_R 1 2 BLON_OUT [37]
19 LCD_TST R5406 100R2J-2-GP LCD_TST [37] DGPU_SELECT# :
18 LDDC_CLK_CON
17 LDDC_DATA_CON H=>B1 -iGPU PCH (UMA)
16 LCD_DET_G 1 2 L=>B0 -dGPU GPU (DIS) +3.3V_RUN
35 15 LCD_CBL_DET# U5446
LCD_CBL_DET# [25] R5408
14
13 VGA_TXAOUT0- VGA_TXAOUT0- [74] 100R2J-2-GP 3 4 U5466_4
[81] LCDVDD_EN_GPU B0 A
VGA_TXAOUT0+
12
11
VGA_TXAOUT0+ [74]
UMA/DIS LVDS PWM select circuit [20] LCDVDD_EN_PCH
2
1
GND
B1
VCC
S
5
6 DGPU_SELECT# [21,74]
10 VGA_TXAOUT1- VGA_TXAOUT1- [74]
9 VGA_TXAOUT1+ VGA_TXAOUT1+ [74] R5438
8 Do Not Stuff NC7SB3157P6X-1GP
34 7 VGA_TXAOUT2- 1 2 73.03157.C0H
6 VGA_TXAOUT2+
VGA_TXAOUT2- [74]
VGA_TXAOUT2+ [74]
[37] LBKLT_CTL_EC DY
5
4 VGA_TXACLK- VGA_TXACLK- [74] U5448 +3.3V_RUN
3 VGA_TXACLK+ VGA_TXACLK+ [74]
2 [81] LBKLT_CTL_GPU 3 4 LCD_BRIGHTNESS
B0 A
2 GND VCC 5
1 [20] LBKLT_CTL_PCH 1 B1 S 6 DGPU_PWM_SELECT# [21]
NP1 D5409
33 31 BAT54C-7-F-GP +LCDVDD U5403 +3.3V_RUN
NC7SB3157P6X-1GP
LCD1 R5409
73.03157.C0H [37] SHBM_LCDTST_EN 1
0R2J-2-GP
3 OUT IN#4 4
2 GND
1
3 ENVDD_D 1 2 ENVDD 1 5
EN IN#5
1
U5466_4 2 C5407
L=>B0 -dGPU GPU (DIS)
2
R5411 G5285T11U-GP
1
49K9R2F-L-GP SC1U10V3KX-3GP
C5408
DY Do Not Stuff
2
LCD_BRIGHTNESS
BLON_OUT_R
LCD_TST
Do Not Stuff
Do Not Stuff
1
EC5402
EC5401
1st Samsung
1
R5407
DY DY 10KR2J-3-GP
Wistron Corporation
2

Title
For EMI request
Size
LCD/Inverter Connector
Document Number Rev
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
SSID = VIDEO +5V_CRT_RUN

D5504
+5V_RUN
B0530WS-7-F-GP
K A
1
C5510
SCD01U16V2KX-3GP
2
CRT1
L5502
16
[74] M_RED 1 2 CRT_R
D BLM18BB220SN-GP 6 D
CRT_R 1 11
L5501
[74] M_GREEN 1 2 CRT_G 7

BLM18BB220SN-GP CRT_G 2 12 DDC_DATA_CON
L5503 8
+5V_CRT_RUN CRT_B 3 13 JVGA_HS JVGA_HS [74]
[74] M_BLUE 1 2 CRT_B 9
BLM18BB220SN-GP 4 14 JVGA_VS JVGA_VS [74]
1
1
10
1
AFTP5502 1 5 15 DDC_CLK_CON
1
17
2
DYDY
2
2
VIDEO-15-58-GP-U1
R5502 R5501 R5503 C5508 C5501 C5506 20.20431.015

150R2F-1-GP 150R2F-1-GP 150R2F-1-GP SC8P250V2CC-GP SC8P250V2CC-GP SC8P250V2CC-GP
C5502 C5504
Layout Note: Do Not Stuff Do Not Stuff
C5509 C5507 C5512
SC8P250V2CC-GP SC8P250V2CC-GP SC8P250V2CC-GP
*Pi-filter & 150 Ohm pull-down AFTP5503 1 +5V_CRT_RUN
DW
AFTP5501 1 DDC_DATA_CON
resistors should be as close AFTP5509 1 DDC_CLK_CON 07/14 Change
as to CRT CONN. AFTP5507 1 CRT_R 1.Change CRT1 CONN PN from
20.20431.015 to 20.20401.015 base on ME emm files.
CRT_R CRT_G CRT_B * RGB signal will hit 75 Ohm AFTP5506 1 CRT_G
3
3
AFTP5508 1 CRT_B
C D5501 D5502 D5503 first, then pi-filter, finally AFTP5504 1 JVGA_HS C
DY Do Not Stuff
DY Do Not Stuff
DY Do Not Stuff CRT CONN. AFTP5505 1 JVGA_VS
+3.3V_RUN_GPU +3.3V_RUN_GPU +3.3V_RUN_GPU

1
+3.3V_RUN +3.3V_RUN_GPU
DW +5V_CRT_RUN
07/07 Change
Close PCH Close GPU 1.Change CRT DDC CLK/DAT Circuit
2
1
2
1
2
1
RN5510 RN5511 RN5513
SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP
3
4
3
4
3
4
B B
[20] GMCH_DDCDATA [81] CRT_DAT_DDC

DDC_DATA_CON
[20] GMCH_DDCCLK [81] CRT_CLK_DDC
DDC_CLK_CON
UMA/DIS CRT DDC CLK/DAT select circuit
1
DY DY
2
+3.3V_RUN
U5542
3 4 DDC_DATA_CON2 C5519 C5520

[81] CRT_DAT_DDC B0 A
2 5 Do Not Stuff Do Not Stuff
GND VCC EDID_SELECT#
[20] GMCH_DDCDATA 1 B1 S 6
+3.3V_RUN
5V @ CRT side
NC7SB3157P6X-1GP
73.03157.C0H
Q5517
[23,54] EDID_SELECT# EDID_SELECT#
DDC_DATA_CON2 4 3 DDC_DATA_CON
+3.3V_RUN
U5543
5 2
3 4 DDC_CLK_CON2 6 1
[81] CRT_CLK_DDC B0 A
2 GND VCC 5
A 1 6 EDID_SELECT# 1st Samsung A
[20] GMCH_DDCCLK B1 S DMN66D0LDW-7-GP
NC7SB3157P6X-1GP DDC_CLK_CON2
73.03157.C0H DDC_CLK_CON Wistron Corporation
Title
L=>B0 -dGPU GPU (DIS)
CRT Connector Rev
www.vinafix.vn
A3 SA
Vostro Calpella
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
(Blank)
C C
B B
A A
1st Samsung
Wistron Corporation
Title
HDMI Connector
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
SSID = Thermal
C
AFTP5803 1 EMC2102_FAN_TACH_1
Fan Connector C
AFTP5802 1 EMC2102_FAN_DRIVE
FAN1
5
[39] EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 3
2
[39] EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 1

4
*Layout* 25 mil
K
FOX-CON3-6-GP-U
1
D5801
C5801 AFTP5801
SC22U6D3V5MX-2GP
SDMK0340L-7-F-GP 1
20.D0210.103
B B
A 1st Samsung A
Wistron Corporation
Title

FAN Rev
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
SSID = SATA
SATA HDD Connector SATA HDD Interface comment
******************************
S1:GND
HDD1
S2:RX+
23
S1 S3:RX-
S2 SATA_ITXP0_HRXP0 [24] S4:GND
S3
S5:TX-
[24] SATA_ITXN0_HRXN0
S4 S6:TX+
1 2 SATA_IRXN0_HTXN0 S5
[24] SATA_IRXN0_HTXN0_C
SATA_IRXP0_HTXP0
S7:GND
S6 2 1 SATA_IRXP0_HTXP0_C [24]
C5913 S7 ******************************
SCD01U50V2KX-1GP +3.3V_RUN
+3.3V_RUN
P1------------ 3.3V
P1 C5914 P2------------ 3.3V
P2 SCD01U50V2KX-1GP P3------------ 3.3V
P3 P4:GND
P4
P5 P5:GND / Dell Detected Pin
+5V_RUN +5V_RUN
P6 P6:GND
P7
P8
P7------------ 5V
P9 P8------------ 5V
P10 P9------------ 5V
P11 FFS_INT2 FFS_INT2 [40]
P12 P10--- GND
P13 P11:Dell: FFS_INT for supported HDD
P14
P15 P12:GND
24 P13------------ 12V
SKT-SATA7P+15P-24-GP-U
P14------------ 12V
P15------------ 12V
22.10300.451
Close to CONN Close to CONN ******************************
5V power pin 3.3V power pin
+5V_RUN +3.3V_RUN
C5903
C5907
C5902
C5901
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
1
1
Do Not Stuff
Do Not Stuff
DY DY
2
SSID = SATA
ODD Connector
ODD1
S1 GND
[24] SATA_ITXP1_ORXP1 S2 A+
[24] SATA_ITXN1_ORXN1 S3 A-
S4 GND
[24] SATA_IRXN1_OTXN1_C C5911 2 1 SCD01U50V2KX-1GP SATA_IRXN1_OTXN1 S5
C5912 B-
[24] SATA_IRXP1_OTXP1_C 2 1 SCD01U50V2KX-1GP SATA_IRXP1_OTXP1 S6 B+
S7 GND
P1 DP
SATA_RX- and SATA_RX+ Trace P2 +5V
P3
Length match within 20 mil +5V_RUN
P4
+5V
MD
1
P5 GND
C5915 P6 GND
7
2
SC10U6D3V5MX-3GP GND
8 GND
NP1 NP1
C5908 NP2
SCD1U10V2KX-4GP NP2
SKT-SATA7P+6P-38-GP-U
62.10065.531 1st Samsung
Wistron Corporation
Title
HDD/ODD Connector
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
SSID = AUDIO SSID = AUDIO

AFTP6004 1 AUD_SPK_L-_C
AFTP6002 1 AUD_SPK_L+_C MIC IN
Speaker Connector [30] AUD_VREFOUT_B
AUD_VREFOUT_B
1
C6001
D check cable pin define 2009/06/03 D
1
SC1U10V2KX-1GP
R6003
R6004
4K7R2J-2-GP
4K7R2J-2-GP
2
SPK1 EXT_MIC_JD#
[30] EXT_MIC_JD#
3
AUD_SPK_L- R6006 1 2 0R3J-0-U-GP AUD_SPK_L-_C 1
2
[30] AUD_SPK_L- LIN1
AUD_SPK_L+ R6007 1 2 0R3J-0-U-GP AUD_SPK_L+_C 2 6
[30] AUD_SPK_L+
4 1
1 2 MIC_IN_L_C 2
[30] AUD_EXT_MIC_L L6002 1 MIC_IN_R_C
MLX-CON2-7-GP-U [30] AUD_EXT_MIC_R 2 3
L6003 BLM18BD601SN1D-GP
20.F0693.002 4
1
1
Do Not Stuff
Do Not Stuff
BLM18BD601SN1D-GP 5
1
600ohm 100MHz EC6001 EC6002
AFTP6005 AUDIO-JK186-GP
EC6003
EC6008
DY DY 1
200mA 0.5ohm DC DY DY
22.10265.251
2
Do Not Stuff
Do Not Stuff
2
AFTP6009 1 EXT_MIC_JD#
AFTP6020 1 GND
AFTP6018 1 MIC_IN_L_C
AFTP6019 1 MIC_IN_R_C
C C
Added MIC circuit 2009/05/26
Delete Audio De-pop Circuit

2009/07/24
SSID = AUDIO
Head Phone
2009/06/03
AUD_HP1_JD#
[30] AUD_HP1_JD#
LOUT1
6
1
AUD_HP1_JACK_L 1 2 AUD_HP_JACK_L_1 2
[30] AUD_HP1_JACK_L
AUD_HP1_JACK_R L6004
1 2 AUD_HP_JACK_R_1 3
[30] AUD_HP1_JACK_R
L6001 BLM18BD601SN1D-GP 4
B BLM18BD601SN1D-GP B
5
600ohm 100MHz
AUDIO-JK186-GP
200mA 0.5ohm DC
22.10265.251
1
C6002 C6003 EC6004 EC6005
SC1000P50V3JN-GP-U SC1000P50V3JN-GP-U
2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
AFTP6014 1 AUD_HP1_JD#
AFTP6017 1 GND
AFTP6015 1 AUD_HP_JACK_L_1
AFTP6016 1 AUD_HP_JACK_R_1
Added HP circuit 2009/05/26
A 1st Samsung A
Wistron Corporation
Title
SPEAKER/MIC/AUDIO JACK
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM SSID = RBATT
D D
SPI FLASH ROM (2M bits) for KBC

RN6201
SRN100KJ-6-GP
KBC_PWR 4 1 EC_SPI_CS#
3 2 EC_SPI_HOLD# KBC_PWR
RTC Connector
1
DY
2
+3.3V_RTC_LDO
+3.3V_RTC_LDO C6201 C6203 C6204
C Do Not Stuff SCD1U16V2KX-3GP SCD1U16V2KX-3GP C
1
+RTC_CELL D6201
R6201 1
100KR2J-1-GP +RTC_VCC
RTC1
3
R6202 3
2
U6203 KBC_PWR 2 RTC_PWR 1 2 1
1
[37] EC_SPI_CS# EC_SPI_CS# 1 8 C6202 BAT54CW-1-GP 1KR2J-1-GP 2
R6205 1 CS# VCC
[37] EC_SPI_DI 2 0R2J-2-GP SPI_DO 2 7 EC_SPI_HOLD# SC1U10V3KX-3GP 4
2
R6204 1 SO HOLD#
[37] EC_SPI_WP#_R 2 0R2J-2-GP EC_SPI_WP# 3 WP# SCK 6 EC_SPI_CLK [37] AFTP6202 1
4 5 SPI_DIO SPI_DIO [37]
GND SI FOX-CON2-17-GP
Width=20mils
1
1
EC6202 AT25DF021-SSH-T-GP 20.D0210.102
SC4D7P50V2CN-1GP
2
EC6201 EC6203
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
AFTP6201 1 +RTC_VCC
B B
SPI FLASH ROM (32M bits) for PCH

RN6202 +3.3V_RUN
SRN4K7J-8-GP
+3.3V_RUN 1 4 PCH_SPI_WP#
2 3 PCH_SPI_HOLD_0#
1
DY C6206
SCD1U16V2KX-3GP
2
C6205
Do Not Stuff
+3.3V_RUN
1
R6207
4K7R2J-2-GP U6202 +3.3V_RUN
2
[24] PCH_SPI_CS0# 1 CS# VCC 8

[24] PCH_SPI_DI 1 2 PCH_SPI_DI_R 2 7 PCH_SPI_HOLD_0#
PCH_SPI_WP# SO HOLD#
3 WP# SCK 6 PCH_SPI_CLK [24]
R6206 4 5 PCH_SPI_DO [24]
15R2J-GP GND SI
A 1st Samsung A
1
AT25DF321-SU-GP
DY DY DY
Wistron Corporation
2

EC6205 EC6204 EC6206 Title

EEPROM/RTC Connector
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = USB
USB & ESATA Power SW
USB_OC#0_1 [21,22]
+5V_ALW U6303 +5V_USB1
at least 80 mil 1 GND OC1# 8 at least 80 mil

2 IN OUT1 7
SC1U10V3KX-3GP
ST100U6D3VBML1GP
3 6
SCD1U10V2KX-4GP
Do Not Stuff
EN1# OUT2
1
4 5 R6302 +5V_USB1
Do Not Stuff
[37,76] USB_PWR_EN# EN2# OC2#
TC6303
R6307
C6306
C6305
1 2 USB1
1
C6302
D
TPS2062AD-GP DY 0R3J-0-U-GP USB_P0-
7 D
DY [21] USB_PN0 5
2
2
2
1
3
USB_P0- 2
TR6304 USB_P0+ 3
Do Not Stuff
DY 4
2
8
[21] USB_PP0 USB_P0+
R6308 SKT-USB-277-GP
1 2
0R3J-0-U-GP 22.10321.161
Remove ESD diode, confirmed with EMI
AFTP6317 1 USB_P0-
AFTP6316 1 USB_P0+
AFTP6321 1 +5V_USB1
AFTP6320 1 GND
C C
SSID = ESATA
R6301
1 2
ESATA Power 0R3J-0-U-GP USB_P1-
[21] USB_PN1
3
TR6301
DY Do Not Stuff
Share one power SW with USB port 1
2
[21] USB_PP1 USB_P1+ +5V_USB1
R6306
1 2 ESATA1
1
0R3J-0-U-GP VBUS
Remove ESD diode, confirmed with EMI GND 4
ESATA_ITX_DRX_PU 6 5
ESATA_ITX_DRX_NU A+ GND
7 8 AFTP6306
A- GND
11
ESATA_IRX_DTX_PU GND
10 B+ GND 12 1
+3.3V_RUN +3.3V_RUN +3.3V_RUN ESATA_IRX_DTX_NU 9 13
B- GND
14
USB_P1+ GND
ASM USB_P1-
3
2
D+
D-
GND
15
1
C6317
C6318
C6319
Do Not Stuff
Do Not Stuff
Do Not Stuff
1
R6314 R6315 SKT-USB-ESATA-1-GP

DY DY
Do Not Stuff Do Not Stuff DY DY DY
22.10254.681
2
ASM
2
B R6304 B
D0 ESATA_ITX_DRX_PU_C 1 2 ESATA_ITX_DRX_PU
D1 AFTP6308 1 +5V_USB1
0R3J-0-U-GP AFTP6309 USB_P1-
DY 1
1
AFTP6302 1 USB_P1+
R6316 R6317
2
DY Do Not StuffDY Do Not Stuff
TR6302
2
Do Not Stuff
RN6301 DY
2 3
1 4
3
+3.3V_RUN SRN0J-6-GP
R6310
2 1 R6313 U6301_REPEATER_EN ESATA_ITX_DRX_NU_C 1 2 ESATA_ITX_DRX_NU
DY Do Not Stuff
U6301
CAPS CLOSE TO ESATA1 0R3J-0-U-GP
6 7 R6311
VCC EN ESATA_ITX_DRX_PU_L 1 ESATA_ITX_DRX_PU_R 1 ESATA_ITX_DRX_PU_C ESATA_IRX_DTX_PU_L ESATA_IRX_DTX_PU
2R6318 2 C6311
10
20
VCC
15
DY Do Not Stuff SCD01U50V2KX-1GP
1 2
VCC TX_0P ESATA_ITX_DRX_NU_L 1 ESATA_ITX_DRX_NU_R 1 ESATA_ITX_DRX_NU_C
2R6319 2 C6312 0R3J-0-U-GP
16 VCC TX_0N 14
DY Do Not Stuff SCD01U50V2KX-1GP
ESATA_IRX_DTX_P4_C_L 2 C6313
[24] ESATA_ITX_DRX_P4 1 2
DY TX_1P
5 1
DY ESATA_IRX_DTX_P4_C [24]
2
C6309 Do Not Stuff ESATA_ITX_DRX_P4_R 1 4 Do Not Stuff
ESATA_ITX_DRX_N4_R RX_0P TX_1N ESATA_IRX_DTX_N4_C_L
[24] ESATA_ITX_DRX_N4 DY
1
C6310
2
Do Not Stuff
2 RX_0N 1
DY 2
C6314
ESATA_IRX_DTX_N4_C [24]
TR6303
ESATA_IRX_DTX_PU_L C6315 ESATA_IRX_DTX_P4_L ESATA_IRX_DTX_P4 11 Do Not Stuff Do Not Stuff
SCD01U50V2KX-1GP
2 1 1
DY
R6320
2
Do Not Stuff ESATA_IRX_DTX_N4 12 RX_1P GND
3
13
DY
ESATA_IRX_DTX_NU_L C6316 RX_1N GND
1ESATA_IRX_DTX_N4_L
SCD01U50V2KX-1GP
2 1
R6321 DY 2
Do Not Stuff GND 17
18
3
D0 GND
9 19
D1 D0 GND
8 D1 GND 21
CAPS CLOSE TO ESATA1 ESATA_IRX_DTX_NU_L 1
R6312
2 ESATA_IRX_DTX_NU
SN75LVCP412RTJR-GP
0R3J-0-U-GP
A RN6302 A
4 1
3 2
SRN0J-6-GP
1st Samsung
Wistron Corporation
Title
USB/ESATA Port
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = Wireless
D D
Mini Card Connector(802.11a/b/g/n)
+1.5V_RUN +3.3V_RUN
WLAN1
53
NP1
1 2
+5V_ALW +3.3V_RUN 3 4
[73] WLAN_ACT
[73] BT_ACT 5 6
[23] MINI1_CLKREQ# 7 8
1
9 10
C C6401 C6403 C
Do Not Stuff DY SCD1U16V2KX-3GP
[23] CLK_PCIE_MINI1#
[23] CLK_PCIE_MINI1
11
13
12
14
2
15 16 R6406
0R3J-0-U-GP
USB_P4- 1 2 USB_PN4 [21]
R6404 1 2 Do Not Stuff E51_RXD_R
+3.3V_RUN +1.5V_RUN
[37] E51_RXD
R6403 1 DY 2 Do Not Stuff E51_TXD_R
17 18
[37] E51_TXD DY 19
21
20
22 PLT_RST#
WIFI_RF_EN [37]
PLT_RST# [9,21,34,36,37,70,76,80]
23 24
SCD1U16V2KX-3GP
[23] PCIE_IRXN2_MTXN2 +3.3V_RUN
3
Do Not Stuff
Do Not Stuff
Do Not Stuff
[23] PCIE_IRXP2_MTXP2 25 26
1
1
C6405
C6402
C6404
C6406
27 28
PCH_SMBCLK
DY DY DY [23] PCIE_ITXN2_MRXN2
29
31
30
32 PCH_SMBDATA
PCH_SMBCLK [7,18,19,23,40,76] DY
PCH_SMBDATA [7,18,19,23,40,76]
2
33 34 Do Not Stuff
[23] PCIE_ITXP2_MRXP2 L6401
35 36 USB_P4-
37 38 USB_P4+
2
+3.3V_RUN 39 40
41 42
43 44 LED_WLAN_WIMAX_OUT# [66]
WLAN_ACT 45 46 USB_P4+ 1 2 USB_PP4 [21]
47 48
1
R6402 49 50 R6405
EC6401 +5V_MINI_DEBUG 0R3J-0-U-GP
SC220P50V2KX-3GP
+5V_ALW 1
DY 2 51 52
NP2
2
Do Not Stuff 54
PTWO-CONN52A-4-GP-U
20.F1286.052
B B
+3.3V_RUN
2
R6407
1KR2J-1-GP
SW1
NP1 TP6404 1
1 1 Do Not Stuff
R6408
2 WIRELESS_ON#/OFF_R 1 2 WIRELESS_ON#/OFF [37]
3 10R2J-2-GP
NP2
1
C6407
SW-SLIDE67-GP SC1U10V2KX-1GP
ON OFF 62.40083.001
2
1 2 3
A 1st Samsung A
Wistron Corporation
TP6405 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 WIRELESS_ON#/OFF_R Taipei Hsien 221, Taiwan, R.O.C.
Do Not Stuff
Title
MINICARD(WLAN)/ITP CONN
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title
WWAN Connector
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D PWR BTN LED D
PWR_BTN_LED# 2 1PWR_BTN_LED_R# PWR_BTN_LED_R# [78]

[37] PWR_BTN_LED#
R6628 20KR2J-L2-GP
For LED & Capacity board:

LED Type Color Power rail SCRLK LED
BATTERY LED1 Amber(Multi-color) ALW [37] SCR_LOCK_LED#
SCR_LOCK_LED# 2 1 SCRL_LED_R# SCRL_LED_R# [78]
R6620 20KR2J-L2-GP
SCRL LED White ALW
CAP LED White ALW CAPS LED

CAP_LOCK_LED# 2 1 CAP_LED_R# CAP_LED_R# [78]
[37] CAP_LOCK_LED#
NUM LED White ALW R6621 20KR2J-L2-GP
PWR BTN LED White ALW

NUM LED
SATA ACT LED1 White RUN
NUM_LOCK_LED# 2 1 NUM_LED_R# NUM_LED_R# [78]
[37] NUM_LOCK_LED#
R6622 20KR2J-L2-GP
BT ACT LED White RUN
WLAN/WWAN ACT LED White RUN Bluetooth LED

BT_ACTIVE_K# 2 1 LED_BT_ACT_K_R# LED_BT_ACT_K_R# [78]
[73] BT_ACTIVE_K#
R6623 20KR2J-L2-GP
C C
WWAN LED
[76] LED_WWAN_OUT# 2
R6624
1
20KR2J-L2-GP
WWAN_LED_R# [78] For LED&Capacity board:
WLAN WIMAX_LED
LED Location from left to right
+5V_ALW
[64] LED_WLAN_WIMAX_OUT# 2 1 WLAN_WIMAX_LED_R# [78] For LED&Capacity board: POWER BATTERY
R6634 20KR2J-L2-GP
LED6601
R6611
BATT_LED_ORANGE 1 2BATT_LED_ORANGE_R 3
330R2J-3-GP BATTERY
B 1 B
R6612
BATT_LED_WHITE 1 2BATT_LED_WHITE_R 2
560R2J-3-GP
R6630
Orange
R6617
0R2J-2-GP Q6607 LED-OW-3-GP
Do Not Stuff
Do Not Stuff
1
1
C BAT_O_LED 1 2 BATT_LED_ORANGE
DY DY 83.00326.G70
EC6609
EC6610
1 2 BAT_O_LED_R B R1
[37] BATT_ORANGE_LED
E
2
R2 0R2J-2-GP
PDTC124EU-1-GP
LED6602
White
3
R6632 R6608
R6629
0R2J-2-GP Q6609 PWR2_LED 1 2PWR2_LED_R 1A K2 BREATH POWER LED
C BAT_W_LED 1 2 BATT_LED_WHITE
330R2J-3-GP
1 2 BAT_W_LED_R B R1 LED-Y-74-GP
[37] BATT_WHITE_LED
E
0R2J-2-GP 83.00110.J70
1
R2
PDTC124EU-1-GP EC6607
Do Not Stuff
DY
2
white +5V_ALW
R6631 Q6608
R2
20KR2J-L2-GP E R6619
[37] PWRLED# 1 2 POWER_LED_R# B R1
C POWER_LED_L 1 2 PWR2_LED
DDTA143ECA-7-F-GP
0R2J-2-GP
Remove HDD LED
HD LED
+5V_ALW
Q6606
R2
R6625 E R6626
1 2 SATA_ACT_C# B
[24] SATA_LED# R1
C HDD_LED 1 2 SATA1_ACT_LED SATA1_ACT_LED [78]
20KR2J-L2-GP
A DDTA143ECA-7-F-GP A
0R2J-2-GP
For LED & Capacity board
1st Samsung
Wistron Corporation
Title
LED
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
Internal KeyBoard Connector

TouchPad Connector
D KB1 D
+5V_RUN +5V_RUN
31
1 KB_DET# KB_DET# [25]
KROW7 AFTP6837
SCD1U16V2KX-3GP
2 1
3 KROW6 1 AFTP6836
2
1
C6805
4 KROW4 1 AFTP6839
5 KROW2 1 AFTP6838
6 KROW5 1 AFTP6841 RN6802
2
7 KROW1 1 AFTP6840 KROW[0..7] [37] SRN10KJ-5-GP TPAD1
8 KROW3 1 AFTP6842 5
9 KROW0 1 AFTP6843
3
4
10 KCOL5 1 AFTP6844 KCOL[0..16] [37] 1
11 KCOL4 1 AFTP6845
12 KCOL7 1 AFTP6847 [37] TPCLK 2
13 KCOL6 1 AFTP6846 [37] TPDATA 3
14 KCOL8 1 AFTP6849 4
1
1
15 KCOL3 1 AFTP6848
16 KCOL1 1 AFTP6851 C6804 C6806 AFTP6835 1 6
17 KCOL2 1 AFTP6850 SC33P50V2JN-3GP SC33P50V2JN-3GP
2
2
18 KCOL0 1 AFTP6853
19 KCOL12 1 AFTP6852 ACES-CON4-10-GP-U
20 KCOL16 1 AFTP6855
22 KCOL13 1 AFTP6857 20.K0320.004
24 KCOL9 1 AFTP6859 AFTP6815 1 +5V_RUN
25 KCOL11 1 AFTP6858 AFTP6816 1 TPCLK
C 26 KCOL10 1 AFTP6860 AFTP6817 1 TPDATA C
27
28
29
30
32
+5V_RUN EC6805 1 2Do Not Stuff
ACES-CON30-3-GP
DY
TPCLK EC6806 1 2Do Not Stuff
DY
20.K0421.030 TPDATA EC6807 1 2Do Not Stuff
DY
B
KB Backlight CONN B
+5V_RUN
KBBL1
5
R6815 1 AFTP6833 1 +5V_RUN

1KR2J-1-GP AFTP6832 1 CN7_P2
1 2CN7_P2 2 AFTP6834 1 KB_BL_DET#
[37] KB_BL_DET# KB_BL_DET# 3 AFTP6861 1 KB_BL_CTRL#
KB_BL_CTRL# 4
6
1
2
5
6
ACES-CON4-10-GP-U
[37] KB_BL_CTRL 3 Q6808

FDC655BN-GP 20.K0320.004
2
+5V_RUN +5V_RUN
1
R6803
4
100KR2J-1-GP
DY
1
For EMI
A A
1st Samsung
+5V_RUN EC6801 1 2Do Not Stuff C6812 C6895
DY SCD1U25V2ZY-1GP Do Not Stuff
CN7_P2 EC6802 1
DY 2Do Not Stuff
Place near CON5 Wistron Corporation
KB_BL_DET# EC6803 1 2Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
KB_BL_CTRL# EC6804 1 2Do Not Stuff
DY Title
Keyboard/Touch Pad
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
Hall Sensor Connector

D D
+3.3V_ALW
DY R6903 2009/05/28
1
+3.3V_ALW C6902
SCD1U16V2KX-3GP
2
1
HALL1
R6903
1
DY Do Not Stuff VDD
2
2
VSS
[37] LID_CLOSE# LID_CLOSE# 1 2 LID_CLOSE#_1 3 OUTPUT
1
R6901 10R2J-2-GP
C6901
SCD047U10V2KX-2GP EM-6781-T30-GP
2
74.06781.07B
C C
B B
A A
1st Samsung
Wistron Corporation
Title
Hall sensor
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
GOLDEN FINGER FOR DEBUG BOARD

+3.3V_RUN DBT1
1
[24,36,37] LPC_LAD0 2
[24,36,37] LPC_LAD1 3
[24,36,37] LPC_LAD2 4
C [24,36,37] LPC_LAD3 5 C
[24,36,37] LPC_LFRAME# 6
[9,21,34,36,37,64,76,80] PLT_RST# 7
8
[21] PCLK_FWH 9
10
11
12
MLX-CON10-7-GP
20.D0183.110
B B
A A
1st Samsung
Wistron Corporation
Title
Debug port
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
Braidwood
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
For EMI
Camera Connector 1
R7302
2
D 0R3J-0-U-GP D
USB_PP11 [21]
CAMERA1
9
2
1
CAMERA_USB1+ L7301
Camera Power 2
3 CAMERA_USB1- Do Not Stuff
+3.3V_RUN +3.3V_CAMERA 4 +3.3V_CAMERA
DY
R7301 AUD_DMIC_IN0_R R7300
5 2 1 33R2J-2-GP AUD_DMIC_IN0 [30]
1 2 6
3
7 AUD_DMIC_CLK_G AUD_DMIC_CLK_G [30]
0R3J-0-U-GP 8
1
1
10 R7303
EC7304 C7305
Do Not Stuff DY SC4D7U6D3V3KX-GP ACES-CON8-3-GP-U
1
AFTP7307 1 2 USB_PN11 [21]
2
20.F0779.008 0R3J-0-U-GP
1
EC7302 EC7303
Do Not Stuff
Do Not Stuff
DY DY
AFTP7302 1 AUD_DMIC_CLK_G
2
AFTP7303 1 AUD_DMIC_IN0_R
AFTP7304 1 +3.3V_CAMERA
AFTP7305 1 CAMERA_USB1-
AFTP7306 1 CAMERA_USB1+
C C
For ESD
Bluetooth cable conn.

BT1
15
NP1
BLUETOOTH_DET# 1 2 BT_ACT
WLAN_ACT 3 4 +3.3V_RUN
5 6 USB_PP8
SC2D2U10V3KX-1GP
[21] USB_PP8 USB_PP8 BLUETOOTH_EN 7 8 USB_PN8
[21] USB_PN8 USB_PN8 BT_LED 9 10
1
C7302
[64] BT_ACT BT_ACT 11 12
B BLUETOOTH_EN B
[37] BLUETOOTH_EN 13 14
[64] WLAN_ACT WLAN_ACT NP2
2
16
Assign BT_DET# GPIO ACES-CONN14D-GP
2009/06/09 AFTP6031
AFTP6032
1 BLUETOOTH_DET#
WLAN_ACT
1
20.F1500.014
10KR2J-3-GP
1
1
Do Not Stuff
Do Not Stuff
AFTP6033 1 BLUETOOTH_EN
1
R7307
R7308
AFTP6034 BT_LED
EC7306
1
AFTP6035 BT_ACT
DY DY AFTP6036
1
1 +3.3V_RUN pin define check
2
AFTP6037 1 USB_PP8
2
AFTP6038 1 USB_PN8
BT LED control signal 2009/05/26

Close to BT1
+5V_RUN
+3.3V_RUN
1
1 AFTP6030
R7309
C7304
C7303
Do Not Stuff SCD1U10V2KX-4GP
SC2D2U6D3V3KX-GP
1
A 1st Samsung A
2
BT_ACTIVE_K#
2
[66] BT_ACTIVE_K#
Wistron Corporation
3

Q7302 BT_LED Taipei Hsien 221, Taiwan, R.O.C.
Remove R7301 MMBT3904-7-F-GP
1
2009/06/09 Title
2
Camera CONN
www.vinafix.vn
A3
Vostro Montevina Discrete SA
5 4 3 2 1
5 4 3 2 1
UMA/DIS LVDS signal select circuit

+1.8V_RUN
U7411
[81] VGA_LVDSA_DAT2 38 ATMDS2+ VDD 2
1
[81] VGA_LVDSA_DAT2# 37 ATMDS2- VDD 8
36 16 C7404
[81] VGA_LVDSA_DAT1 ATMDS1+ VDD SCD1U10V2KX-4GP
35 18
2
[81] VGA_LVDSA_DAT1# ATMDS1- VDD
[81] VGA_LVDSA_DAT0 34 ATMDS0+ VDD 20
[81] VGA_LVDSA_DAT0#
33 ATMDS0- VDD 30
D C7401 C7403 D
[81] VGA_LVDSA_CLK 32 ATMDSCLK+ VDD 40
31 42 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
[81] VGA_LVDSA_CLK# ATMDSCLK- VDD
[20] MCH_LVDSA_DAT2
29 BTMDS2+
[20] MCH_LVDSA_DAT2#
28 BTMDS2- TMDS2+ 3 VGA_TXAOUT2+ [54]
[20] MCH_LVDSA_DAT1 27 BTMDS1+ TMDS2- 4 VGA_TXAOUT2- [54]
[20] MCH_LVDSA_DAT1# 26 BTMDS1- TMDS1+ 6 VGA_TXAOUT1+ [54]
[20] MCH_LVDSA_DAT0
25 BTMDS0+ TMDS1- 7 VGA_TXAOUT1- [54]
[20] MCH_LVDSA_DAT0#
24 BTMDS0- TMDS0+ 11 VGA_TXAOUT0+ [54]
[20] MCH_LVDSA_CLK
23 BTMDSCLK+ TMDS0- 12 VGA_TXAOUT0- [54]
[20] MCH_LVDSA_CLK# 22 BTMDSCLK- TMDSCLK+ 14 VGA_TXACLK+ [54]
TMDSCLK- 15 VGA_TXACLK- [54]
[21,54] DGPU_SELECT#
9 SEL
1
VSS 1
R7531 5
VSS
51KR2F-L-GP VSS 10
VSS 13
17
2
DGPU_1D8V_SEL# VSS
VSS 19
VSS 21
1
VSS 39
H=>BTMDS -iGPU PCH (UMA) R7538 41
GND
VSS
45K3R2F-L-GP
L=>ATMDS -dGPU GPU (DIS)
TS3DV421RUAR-GP
2
43
71.03421.003
71.03412.B0G
C C
+5V_CRT_RUN
1
C7407
2 SCD1U10V2KX-4GP
B UMA/DIS CRT Hsync/Vsync select circuit B
DGPU_SELECT Hsync & Vsync level shift

DGPU_SELECT#
+5V_CRT_RUN UMA/DIS CRT signal select circuit
14
U7408A C7408
SSAHCT125PWR-GP SCD1U10V2KX-4GP +5V_CRT_RUN
2 3 VSYNC_5 U7435
[20] GMCH_VSYNC
2 1 16
+5V_CRT_RUN DGPU_SELECT# 1 VCC 4
S YA M_BLUE [55]
14
2
7
[81] VGA_BLUE IA0

4
[20] MCH_BLUE
3 IA1 YB 7 M_GREEN [55]
[81] VGA_GREEN
5 IB0
5 6 VSYNC_5 6 9
[81] VGA_VSYNC [20] MCH_GREEN IB1 YC M_RED [55]
[81] VGA_RED 11 IC0
[20] MCH_RED 10 IC1 YD 12
U7408B 14 ID0
7
+3.3V_RUN DGPU_SELECT# H=> -iGPU PCH (UMA) SSAHCT125PWR-GP 13 ID1 OE# 15

+3.3V_RUN RN7445 8 GND
L=> -dGPU GPU (DIS) VSYNC_5 1 4 JVGA_VS [55]
HSYNC_5 2 3 PI5C3257QE-GP
JVGA_HS [55]
1
DGPU_SELECT 73.53257.B0C
DY EC7401
Do Not Stuff
R7485
20KR2F-L-GP
SRN33J-5-GP-U 2ND = 73.03257.C0B
H=>IA1 -iGPU PCH (UMA)
2
DGPU_SELECT# +5V_CRT_RUN
U7408C L=>IA0 -dGPU GPU (DIS)
14
10
2
DGPU_SELECT SSAHCT125PWR-GP
A HSYNC_5 A
9 8 1st Samsung
D
[20] GMCH_HSYNC
+5V_CRT_RUN
Wistron Corporation
14
13
Q7410
7
[21,54] DGPU_SELECT# DGPU_SELECT# G 2N7002A-7-GP

12 11 HSYNC_5 Taipei Hsien 221, Taiwan, R.O.C.
[81] VGA_HSYNC
S
Title
PX Swith-1
7
U7408D
www.vinafix.vn
SSAHCT125PWR-GP Size Document Number Rev
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
+DC_IN : 19.5V/85W Place near BTB1

+3.3V_RUN : 3300mA +DC_IN
DC_IN baord CON +5V_ALW : 1000mA
Do Not Stuff
+1.5V_RUN : 500mA
1
D D
C7620
Please reoute 300 mil at least. +3.3V_ALW : 58mA
2
DY
+DC_IN
BTB1
SCD1U25V2ZY-1GP
C7621
52
1
NP2
[23] CLK_PCIE_LAN# 49 50 PCIE_ITXP4_MRXP4 [23]

LAN CLK WWAN PCIE
2
[23] CLK_PCIE_LAN 47 48 PCIE_ITXN4_MRXN4 [23]
45 46
[23] PCIE_ITXN3_LRXN3 43 44 PCIE_IRXP4_MTXP4 [23]
LAN PCIE [23] PCIE_ITXP3_LRXP3 41 42 PCIE_IRXN4_MTXN4 [23] WWAN PCIE
39 40
[23] PCIE_IRXN3_LRTXN3 37 38 CLK_PCIE_MINI2# [23]
LAN PCIE [23] PCIE_IRXP3_LRTXP3 35 36 CLK_PCIE_MINI2 [23]
WWAN CLK
33 34 +3.3V_RUN
SC4D7U25V5KX-GP
[21] USB_PP2 31 32 USB_PP5 [21]
USB PORT2 WWAN USB
C7601
[21] USB_PN2 29 30 USB_PN5 [21]
1
[21] USB_OC#2_3 27 28 MINI2_CLKREQ_R# [23]
[37,63] USB_PWR_EN# 25 26 PCH_SMBDATA [7,18,19,23,40,64]
[23] CLKREQ#_LAN 23 24 PCH_SMBCLK [7,18,19,23,40,64] WWAN SMBUS
2
[37] PM_LAN_ENABLE 21 22 LED_WWAN_OUT# [66]
[24] GPO_DSM 19 20 WWAN_RF_EN [21]
C [43] PS_ID_R2 17 18 PLT_RST# [9,21,34,36,37,64,70,80] C
15 16 PCIE_WAKE# [22,34]
13 14 +3.3V_RUN
11 12
SCD1U16V2KX-3GP
+3.3V_RUN 9 10
C7602
+1.5V_RUN 7 8
1
+3.3V_ALW 5 6
3 4
2
+5V_ALW 1 2 +DC_IN
NP1
51
ACES-CONN50A-2-GP
+5V_ALW
20.F1631.050
SC4D7U25V5KX-GP
C7614
1
2
Remove AFTP test point
Confirmed with AFTE.
+5V_ALW
SCD1U16V2KX-3GP
C7615
1
B B
2
+1.5V_RUN
SCD1U16V2KX-3GP
C7618
1
2
+3.3V_ALW
SCD1U16V2KX-3GP
C7619
1
2
A A
1st Samsung
Wistron Corporation
Title
DC_IN Board BTB Connector
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
Audio BD/IO BD CONN
www.vinafix.vn
Custom
Vostro Montevina Discrete SA
5 4 3 2 1
5 4 3 2 1
D D
Finger Printer Connector

+3.3V_RUN
1
C7801 FP1 LED&Capacity board CONN
SCD1U10V2KX-4GP 8
2
R7802 6
0R3J-0-U-GP 5
Biometric_USBPN
[21] USB_PN10 1
1
2
2 Biometric_USBPP
4
3
Close to MEDIA1
[21] USB_PP10
2 MEDIA1
R7801 21 +5V_RUN +5V_ALW +3.3V_RUN
0R3J-0-U-GP BIO_DET# 1 +5V_RUN 1
[25] BIO_DET#
C7803
C7804
C7805
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
7
1
+5V_ALW 2
PTWO-CON6-2-GP 3
4
4
20.K0293.006
2
KBC_PWRBTN# 5
EL7801 [37] KBC_PWRBTN# WLAN_WIMAX_LED_R#
[66] WLAN_WIMAX_LED_R# 6
Do Not Stuff SCRL_LED_R# 7
DY [66]
[66]
SCRL_LED_R#
CAP_LED_R# CAP_LED_R# 8
[66] NUM_LED_R# NUM_LED_R# 9
[66] SATA1_ACT_LED SATA1_ACT_LED 10
1
C [66] LED_BT_ACT_K_R# LED_BT_ACT_K_R# 11 C

[66] WWAN_LED_R# WWAN_LED_R# 12
[66] PWR_BTN_LED_R# PWR_BTN_LED_R# 13 AFTP7806 1 WLAN_WIMAX_LED_R#
AFTP7802 1 +3.3V_RUN CAPA_INT# 14 AFTP7808 1 SCRL_LED_R#
AFTP7803 Biometric_USBPN [37] CAPA_INT# CAPA_RST# AFTP7809 CAP_LED_R#
1 [37] CAPA_RST# 15 1
AFTP7804 1 Biometric_USBPP 16 AFTP7810 1 NUM_LED_R#
THERM_SDA 17 AFTP7811 1 SATA1_ACT_LED
[37,39] THERM_SDA
THERM_SCL 18 AFTP7812 1 LED_BT_ACT_K_R#
[37,39] THERM_SCL
19 AFTP7813 1 WWAN_LED_R#
+3.3V_RUN 20 AFTP7814 1 CAPA_INT#
22 AFTP7815 1 CAPA_RST#
AFTP7816 1 THERM_SDA
PTWO-CON20-2-GP AFTP7817 1 THERM_SCL
AFTP7818 1 +3.3V_RUN
20.K0392.020 AFTP7819 1 +5V_RUN
AFTP7820 1 +5V_ALW
AFTP7821 1 PWR_BTN_LED_R#
AFTP7822 1 KBC_PWRBTN#
B B
A A
1st Samsung
Wistron Corporation
Title
Finger Printer/Felica/Capacity
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = Mechanical HOLE:

EMI Request
H1 H2 H6 H7 H8
+PWR_SRC Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
H10
Do Not Stuff
D D
SCD1U25V2ZY-1GP
Do Not Stuff
1
1
1
EC7901
EC7902
1
DY
2
2
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
H3 H14
1
C
H5 FOR CPU HOLE C
Do Not Stuff
H11 H12 H13
1
DY DY DY
1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
FORH4 FAN BOSS FOR BT

H9
BOSS
STF296R138H83-GP STF237R115H123-GP
1
B B
34.4A908.001 34.4A902.001
SPR1 SPR2 SPR3 SPR4 SPR5

1
1
SPRING-24-GP SPRING-24-GP SPRING-24-GP SPRING-31-GP SPRING-6-GP
34.45T31.001 34.45T31.001 34.45T31.001 34.49U24.001 34.13B01.001

A A
1st Samsung
Wistron Corporation
Title
Miscellaneous Components
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
PCIE_MTX_GRX_P[0..15]
SSID = VIDEO PCIE_MTX_GRX_P[0..15] [8]
PCIE_MTX_GRX_N[0..15]
PCIE_MTX_GRX_N[0..15] [8]
U8001B 2 OF 7
PCIE_MTX_GRX_P0 AE12 AD10 PCIE_MRX_GTX_C_P0 C8033 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P[0..15]

PCIE_MTX_GRX_N0 PEX_RX0 PEX_TX0 PCIE_MRX_GTX_C_N0 C8034 PCIE_MRX_GTX_P[0..15] [8]
AF12 PEX_RX0# PEX_TX0# AD11 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N0
PCIE_MTX_GRX_P1 AG12 AD12 PCIE_MRX_GTX_C_P1 C8035 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P1
PCIE_MTX_GRX_N1 PEX_RX1 PEX_TX1 PCIE_MRX_GTX_C_N1 C8036 PCIE_MRX_GTX_N[0..15]
AG13 PEX_RX1# PEX_TX1# AC12 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N[0..15] [8]
D PCIE_MTX_GRX_P2 AF13 AB11 PCIE_MRX_GTX_C_P2 C8037 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P2 D
PCIE_MTX_GRX_N2 PEX_RX2 PEX_TX2 PCIE_MRX_GTX_C_N2 C8038
AE13 PEX_RX2# PEX_TX2# AB12 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N2
PCIE_MTX_GRX_P3 AE15 AD13 PCIE_MRX_GTX_C_P3 C8039 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P3
AG16 PEX_RX4# PEX_TX4# AC15 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N4
PCIE_MTX_GRX_P5 AF16 AB14 PCIE_MRX_GTX_C_P5 C8044 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P5
PCIE_MTX_GRX_P6 AE18 AC16 PCIE_MRX_GTX_C_P6 C8047 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P6
AG19 PEX_RX7# PEX_TX7# AD18 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N7
PCIE_MTX_GRX_P8 AF19 AC18 PCIE_MRX_GTX_C_P8 C8052 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P8
PCIE_MTX_GRX_P9 AE21 AB19 PCIE_MRX_GTX_C_P9 C8054 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P9
AF21 PEX_RX9# PEX_TX9# AB20 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N9
PCIE_MTX_GRX_P11 AF22 AD21 PCIE_MRX_GTX_C_P11 C8058 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P11
AE22 PEX_RX11# PEX_TX11# AC21 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N11
PCIE_MTX_GRX_P12 AE24 AB21 PCIE_MRX_GTX_C_P12 C8078 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P12
AF24 PEX_RX12# PEX_TX12# AB22 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N12
PCIE_MTX_GRX_P13 AG24 AC22 PCIE_MRX_GTX_C_P13 C8080 2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P13
PCIE_MTX_GRX_P15 PCIE_MRX_GTX_C_P15 C8084 1SCD1U16V2KX-3GP PCIE_MRX_GTX_P15
PCIE_MTX_GRX_N15
AF27
AE27
PEX_RX15 PEX_TX15 AE25
AE26 PCIE_MRX_GTX_C_N15 C8085
2
2 1SCD1U16V2KX-3GP PCIE_MRX_GTX_N15
Revised decoupling C 2009/05/28
+1.05V_GFX_PCIE PEX_RX15# PEX_TX15# +1.05V_GFX_PCIE
Place under GPU Place near GPU
C C
AB13 PEX_IOVDDQ PEX_IOVDD AC9
AB16 AD7
SC22U6D3V5MX-2GP
SC10U6D3V5MX-3GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5MX-3GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
PEX_IOVDDQ PEX_IOVDD
1
1
C8069
C8074
C8064
C8067
C8068
C8066
C8065
C8059
C8060
C8063
C8062
C8061
C8073
C8041
AB17 PEX_IOVDDQ PEX_IOVDD AD8
AB7 PEX_IOVDDQ PEX_IOVDD AE7
AB8 AF7
2
2
PEX_IOVDDQ PEX_IOVDD
AB9 PEX_IOVDDQ PEX_IOVDD AG7
AC13 PEX_IOVDDQ
AC7 AB10 CLK_PCIE_VGA
PEX_IOVDDQ PEX_REFCLK CLK_PCIE_VGA [23]
AD6 AC10 CLK_PCIE_VGA#
PEX_IOVDDQ PEX_REFCLK# CLK_PCIE_VGA# [23] +3.3V_RUN_GPU
AE6 PEX_IOVDDQ
AF6 PEX_IOVDDQ Change R8004
1
Place near GPU Place under GPU AG6 PEX_IOVDDQ PEX_TSTCLK_OUT AF10 PEX_TEST_PLL_CLK_OUT 2
DY 1
PEX_TSTCLK_OUT# AE10 PEX_TEST_PLL_CLK_OUT# Do Not Stuff R8002 R8004
10KR2J-3-GP
resistor value
Revised decoupling C 2009/05/28 2009/06/05
AE9 PEX_CLKREQ#
2
PEX_CLKREQ# PEX_RST#
PEX_RST# AD9
PEX_SVDD_3V3 AG9 +3.3V_RUN_GPU

PEX_TERMP 2 R8001 2K49R2F-GP
PEX_TERMP AG10 1 DW
C8049
SCD1U10V2KX-4GP
1
AF9 07/10 NO STUFF
PEX_PLLVDD +PEX_PLLVDD 1. R8002 made NO STUFF
K5 +GPU_PLLVDD
2
PLLVDD
N11M-GE1-S-A2-GP
2009/05/28
B B
Place under GPU
Remove 0.01u capacity C8039
2009/05/28
Change power rail
2009/05/26
+3.3V_RUN +PEX_PLLVDD
PEX_PLLVDD = 120mA +1.05V_GFX_PCIE
Place under GPU Place near GPU +1.05V_GFX_PCIE
U8028
1
L8011 (Pre pin)
+GPU_PLLVDD
[25] DGPU_HOLD_RST# B L8005
VCC 5 1 2
C8070
1 R8039 2 PLT_RST#_RC 2 1 2
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
[9,21,34,36,37,64,70,76] PLT_RST# A
1
1
C8087
C8046
4 PEX_RST#
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
Y IND-D1UH-20-GP
1
C8086
C8071
C8072
0R2J-2-GP 3 IND-100NH-7-GP
GND
2
Do Not Stuff
100NH 0603
C8076
C8075
2
2
2
DY I SP_PLLVDD=45mA
2
R8017 74LVC1G08GW-1-GP
DCR= 0.13 ohm
2
100KR2J-1-GP R8016
100KR2J-1-GP
1
NV suggestion. Place near GPU

DW Revised decoupling C 2009/05/28 Revised decoupling C 2009/05/28
07/10 Change
1. Change U8028 from Operating voltage Range 5 to 3 V .
A Add 1st Samsung A
2.Added Pull-down resistors on GPU Reset [PEX_REST#] Pin
Wistron Corporation
Title
VGA-PCIE/LVDS(1/4)
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
DW
07/05 +3.3V_RUN_GPU
2. LCD Power Enable control are separated by GPU,PCH,EC
SSID = VIDEO 3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
2
1
07/10 Not Reserve
1. Shorted LBKLT_CTL_GPU,LCDVDD_EN_GPU,PANEL_BKEN_GPU Not Reserve R8134,R8135,R8136.
RN8112
U8001D 4 OF 7 SRN2K2J-1-GP
N1 R1 CRT_CLK_DDC
GPIO0 I2CA_SCL CRT_DAT_DDC CRT_CLK_DDC [55]
G1 T3
3
4
GPIO1 I2CA_SDA CRT_DAT_DDC [55]
C1
[54] LBKLT_CTL_GPU GPIO2 I2CB_SCL I2CB_SCL
M2 R2
[54] LCDVDD_EN_GPU GPIO3 I2CB_SCL I2CB_SDA I2CB_SDA
[37] PANEL_BKEN_GPU M3 R3
PWRCNTL_0 GPIO4 I2CB_SDA
[86] PWRCNTL_0 K3
PWRCNTL_1 GPIO5 LDDC_CLK
[86] PWRCNTL_1 K2 A2 LDDC_CLK [54]
GPIO6 I2CC_SCL LDDC_DATA
J2 B1 LDDC_DATA [54]
THERMTRIP_VGA# GPIO7 I2CC_SDA
[37] THERMTRIP_VGA# C2
GPIO8
D
M1
D2
GPIO9
GPIO10
I2CH_SCL
I2CH_SDA
A3
A4 Default X'tal D
D1
GPIO11
J3 T1
GPIO12 I2CS_SCL
J1 T2
GPIO13 I2CS_SDA
K1
F3
GPIO14 CLK GEN 27M select: X8101
GPIO15 TP_JTAG_TDI_GPU
G3
G2
GPIO16 JTAG_TDI
AG4
AE4 TP_JTAG_TDO_GPU
1
1
TP8102
TP8104 XTAL_IN R8123 1 2 Do Not Stuff
Main 82.30034.651 2 3
DEEPIDLE_WAKE_INT_R# F1
GPIO17 JTAG_TDO DY CLK_VGA_27M [7]
Second ?
[25] DEEPIDLE_WAKE_INT_R# GPIO18 TP_JTAG_TMS_GPU XTAL_SSIN
F2 AF4 1 TP8101 R8131 1 2 Do Not Stuff
GPIO19 JTAG_TMS
AG3 JTAG_RST#_GPU 2 1 DY
1
JTAG_TRST# TP_JTAG_TCK_GPU 1KR2J-1-GP TP8103 R8120 GPU_XTAL_IN
AF3 1 1 4
JTAG_TCK R8132
DY R8125
Remove R8112,
1
Do Not Stuff 10KR2J-3-GP
ROM_SO
C10 ROM_SO_GPU
ROM_SI_GPU
ROM_SO_GPU [83] R8114 2009/06/09 R8115 XTAL-27MHZ-84-GP
[74] VGA_BLUE AD3 A10 1MR2J-1-GP
2
DACA_BLUE ROM_SI ROM_SI_GPU [83]
[74] VGA_GREEN AE3
DACA_GREEN ROM_SCLK_GPU
[74] VGA_RED AE2 C9
2
DACA_RED ROM_SCLK ROM_SCLK_GPU [83]
B10 GPU_XTALOUT
1
ROM_CS#
VGA 27M R8123 R8131 R8125 R8132
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
1
R8116
R8118
R8119
[74] VGA_VSYNC AD1 C8135 C8138
DACA_VSYNC
+DACA_VDD = 120mA [74] VGA_HSYNC AD2
DACA_HSYNC XTAL_IN
D10 XTAL_IN 2 1 GPU_XTAL_IN SS DY POP DY POP SC10P50V2JN-4GP SC10P50V2JN-4GP
E10 GPU_XTALOUT_1 R8114 2 0R2J-2-GP
1 GPU_XTALOUT
2
DACA_RSET XTAL_OUT
AE1 R8113 0R2J-2-GP NON-SS POP DY POP DY
2
+DACA_VDD DACA_RSET XTALBUFF
Place near GPU Place under GPU AG2 E9 R8124 2 1 10KR2J-3-GP
2
DACA_VREF DACA_VDD XTAL_OUTBUFF
AF1 D11 XTAL_SSIN
+DACA_VDD DACA_VREF XTAL_SSIN
Added CLK GEN 27M select circuit 2009/06/15
R8106
124R2F-U-GP
+3.3V_RUN_GPU R4 R8133
2009/06/03
SCD1U10V2KX-5GP
L8106 DACB_BLUE
16mil STRAP_CAL_PU_GND0 Added R8132 (DY) 2009/06/17
C8103
T4 F11 1 2
1
+DACA_VDD DACB_GREEN MULTI_STRAP_REF0_GND STRAP_CAL_PU_GND1
1 2 T5 F10 1 2 40K2R2F-GP
1
BLM18SG331TN1D-GP DACB_RED MULTI_STRAP_REF1_GND R8126 40K2R2F-GP
C8153
C8154
C8144
C8143
C8118
C8108
C8107
U4
SC470P50V2KX-3GP
SC4700P50V2KX-1GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
2
VGA_THERMDC [39]
1
1
DACB_VSYNC
U6 D8
DACB_HSYNC THERMDN DY
Spec 300 ohm, V6
THERMDP
D9 C8102
Do Not Stuff
VGA_THERMDA [39]
2
2
DACB_RSET
ESR<0.25 ohm DACB_VDD W5
DACB_VDD HDCP_TESTMODE R8107 2
R6 AD25 1 10KR2J-3-GP
DACB_VREF TESTMODE CEC R8127 2
N2 1 10KR2J-3-GP +3.3V_RUN_GPU
1
CEC
L6 +SP_PLLVDD
STRAP0 SP_PLLVDD
R8111
[83] STRAP0 STRAP1
C7
STRAP0 SPDIF
F9 2009/06/03
C
10KR2F-2-GP
[83] STRAP1
STRAP2
B9
A9
STRAP1
N5
2009/05/28 Place near GPU C
[83] STRAP2 STRAP2 BUFRST# +1.05V_GFX_PCIE
2
+SP_PLLVDD
L8110
1 2
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
1
IND-100NH-7-GP
C8127
C8120
I SP_PLLVDD=45mA
2
U8001C 3 OF 7 Revised decoupling C 2009/05/28
[74] VGA_LVDSA_CLK AC4 F5
IFPA_TXC IFPD_L0
[74] VGA_LVDSA_CLK# AD4 F4
IFPA_TXC# IFPD_L0#
V5
IFPD_L1
E4
D5
+IFPAB_IOVDD
[74] VGA_LVDSA_DAT0 IFPA_TXD0 IFPD_L1#
[74] VGA_LVDSA_DAT0# V4 C3
IFPA_TXD0# IFPD_L2
[74] VGA_LVDSA_DAT1 AA5 C4
IFPA_TXD1 IFPD_L2#
[74] VGA_LVDSA_DAT1# AA4 B3
IFPA_TXD1# IFPD_L3 +1.8V_RUN_GPU
[74] VGA_LVDSA_DAT2 W4 B4
IFPA_TXD2 IFPD_L3#
[74] VGA_LVDSA_DAT2# Y4
IFPA_TXD2# L8107 IFPAB_IOVDD = 300mA
AB4 R8128
IFPA_TXD3 IFPD_PLLVDD +IFPAB_IOVDD
AB5 N6 2 1 1 2
IFPA_TXD3# IFPD_PLLVDD
+IFPAB_IOVDD 10KR2J-3-GP BLM18PG181SN1D-GP
C8126
C8149
C8150
V3 M6
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
1
1
IFPA_IOVDD IFPD_RSET
D3
+IFPAB_PLLVDD IFPD_AUX_I2CX_SCL
AD5 D4
2
IFPAB_PLLVDD IFPD_AUX_I2CX_SDA# R8129
1
R8121 DY 2 IFPAB_RSET AB6 IFPAB_RSET IFPDE_IOVDD
H6 IFPDE_IOVDD 2 1
Place near GPU
Place under GPU
near IFPA_IOVDD
Do Not Stuff
2009/05/28AB3 10KR2J-3-GP
IFPB_TXC
AB2 D6
IFPB_TXC# IFPE_L0 +IFPAB_IOVDD
B W1
IFPE_L0#
C6
A6
Revised decoupling C 2009/05/28 B
IFPB_TXD4 IFPE_L1
C8151
V1 A7
SCD1U10V2KX-4GP
1
IFPB_TXD4# IFPE_L1#
W3 B6
IFPB_TXD5 IFPE_L2
DW30 LVDS only 1 chanel W2
AA2
IFPB_TXD5# IFPE_L2#
B7
E6
2
IFPB_TXD6 IFPE_L3
Vendor confirm tie to +1.8V powe rail AA3
IFPB_TXD6# IFPE_L3#
E7 Place under GPU
AB1 R8130
AA1
IFPB_TXD7
D7 IFPE_PLLVDD 2 1 near IFPB_IOVDD
IFPB_TXD7# IFPE_PLLVDD
F8
+IFPAB_IOVDD IFPE_RSET 10KR2J-3-GP
V2
IFPB_IOVDD
F7
IFPE_AUX_I2CY_SCL
G6
IFPE_AUX_I2CY_SDA#
P4
IFPC_L0
N4
IFPC_L0#
DW30 not support HDMI M5
M4
IFPC_L1 Unused IFP
IFPC_L1#
NV DG: pull-down 10K L4
IFPC_L2 Interfaces setting
K4
H4
IFPC_L2#
IFPC_L3
2009/06/03
J4
IFPC_L3#
IFPC_IOVDD
1 2
R8135 1 10KR2J-3-GP
2 IFPC_PLLVDD
J6
P6
IFPC_IOVDD +IFPAB_PLLVDD
IFPC_PLLVDD
R8134 10KR2J-3-GP
R5
IFPC_RSET
G4 +1.05V_GFX_PCIE
IFPC_AUX_I2CW_SCL
G5
IFPC_AUX_I2CW_SDA# L8108 IFPAB_PLLVDD = 220mA
Change power rail 1 2 +IFPAB_PLLVDD
N11M-GE1-S-A2-GP 2009/05/28 BLM18PG181SN1D-GP
C8128
C8152
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
1
2
2
Place near GPU
A A
1st Samsung
Wistron Corporation
Title
VGA-LVDS/CRT/DP PORT
www.vinafix.vn
A2 SA
Vostro Calpella
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO

D U8001G 7 OF 7 D
Place under GPU 6 OF 7
U8001F B2 AF8
GND GND
B5 GND GND AF5
+VCC_GFX_CORE J9 B8 AF26
VDD GND GND
J10 VDD B11 GND GND AF23
L9 B20 AF17
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VDD GND GND
M9 VDD B23 GND GND AF14
C8241
C8242
C8243
C8244
C8246
C8247
M11 VDD B26 GND GND AF11
1
M17 VDD E2 GND GND AC26
N9 VDD E5 GND GND AC23
N11 E8 AC20
2
2
VDD GND GND
N17 VDD F6 GND GND AC5
N19 VDD NC#J5 J5 H2 GND GND AC2
P11 D15 H5 Y26
SCD1U10V2KX-4GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
VDD NC#D15 GND GND
P12 VDD NC#C15 C15 J11 GND GND Y23
C8234
P13 VDD J14 GND GND Y5
1
1
C8248
C8249
C8250
P14 VDD J17 GND GND Y2
P15 VDD K19 GND GND W17
P16 K9 W14
2
2
VDD GND GND
P17 VDD RFU_1 T6 L2 GND GND W11
R9 VDD RFU_2 W6 L11 GND GND V9
C R11 Y6 L12 V19 C
VDD RFU_3 GND GND
R12 VDD RFU_4 AA6 L13 GND GND U26
R13 VDD RFU_5 N3 Place under GPU Place near GPU L14 GND GND U23
R14 VDD L15 GND GND U17
Place near GPU R15 +3.3V_RUN_GPU L16 U16
VDD GND GND
R16 VDD L17 GND GND U15
R17 L5 U14
SC4D7U6D3V3KX-GP
VDD GND GND

C8240
C8229
C8230
C8232
C8211
C8231
T9 M12 U13
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
VDD GND GND
1
T11 VDD M13 GND GND U12
1
T17 VDD VDD33 A12 M14 GND GND U11

U9 B12 M15 U5
2
VDD VDD33 GND GND
U19 C12 M16 U2
2
VDD VDD33 GND GND

W9 VDD VDD33 D12 P2 GND
W10 VDD VDD33 E12 P5 GND
W12 VDD VDD33 F12 P9 GND
W13 VDD P19 GND
W18 VDD P23 GND
W19 VDD P26 GND
Revised decoupling C 2009/05/28 T12
T13
GND
GND
T14 GND GND_SENSE E14
Do Not Stuff TP8203 1 TP_VDD_SENSE_E15 E15 T15 W16
Do Not Stuff TP8205 TP_VDD_SENSE_W15 VDD_SENSE GND GND_SENSE
1 W15 VDD_SENSE VID_PLLVDD K6 +GPU_PLLVDD T16 GND
2009/05/28
N11M-GE1-S-A2-GP
N11M-GE1-S-A2-GP
B
"Remote Voltage Sensing" not used,reserve Test-Point. B
Change FBVDDQ power rail
2009/05/28 FBVDD/Q = 2.24A
+1.5V_RUN_GPU
5 OF 7 U8001E Place under GPU +1.5V_RUN_GPU
L19 FBVDDQ FBVDDQ A13

C8222
C8235
C8209
L23 B13
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
FBVDDQ FBVDDQ
1
1
C8251
C8252
C8253
L26 FBVDDQ FBVDDQ C13
M19 FBVDDQ FBVDDQ D13
N22 D14
2
FBVDDQ FBVDDQ
U22 FBVDDQ FBVDDQ E13
Y22 FBVDDQ FBVDDQ F13
FBVDDQ F14
FBVDDQ F15
FBVDDQ F16
FBVDDQ F17
FBVDDQ F19
FBVDDQ F22
H23 Place near GPU +1.5V_RUN_GPU
FBVDDQ
FBVDDQ H26
FBVDDQ J15
C8219
J16
SC4D7U6D3V3KX-GP
FBVDDQ
1
FBVDDQ J18
FBVDDQ J19
2
A 1st Samsung A
N11M-GE1-S-A2-GP
Wistron Corporation
Revised decoupling C 2009/05/28 Title
VGA-POWER/GND(3/4)
www.vinafix.vn
A3 Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO Strap pin resistor need use 1% resistor (NV Design Guide) +3.3V_RUN_GPU
Strap pin define
U8001A 1 OF 7
[84,85] MDA[0..63]
15KR2F-GP
45K3R2F-L-GP
34K8R2F-1-GP
1
1
Do Not Stuff
Do Not Stuff
Do Not Stuff
MDA0 D22 F26 FBA_CMD_0
FBA_D0 FBA_CMD0 FBA_CMD_0 [84]
R8306
R8302
R8305
R8309
R8311
R8312
D MDA1 E24 J24 RAS# D
FBA_D1 FBA_CMD1 RAS# [84,85]
MDA2 FBA_CMD_2
MDA3
E22
D24
FBA_D2 FBA_CMD2 F25
M23 BA1
FBA_CMD_2 [84] DY DY DY
FBA_D3 FBA_CMD3 BA1 [84,85]
MDA4 D26 N27 FBA_CMD_4
FBA_CMD_4 [85]
2
MDA5 FBA_D4 FBA_CMD4 FBA_CMD_5
D27 FBA_D5 FBA_CMD5 M27 FBA_CMD_5 [85]
MDA6 C27 K26 FBA_CMD_6 STRAP0
FBA_D6 FBA_CMD6 FBA_CMD_6 [85] [81] STRAP0
MDA7 B27 J25 FBA_CMD_7
MDA8 A21 J27 FBA_CMD_8 STRAP1
FBA_D8 FBA_CMD8 FBA_CMD_8 [85] [81] STRAP1
MDA9 B21 G23 MAA11
FBA_D9 FBA_CMD9 MAA11 [84,85]
MDA10 C21 G26 CAS# STRAP2
FBA_D10 FBA_CMD10 CAS# [84,85] [81] STRAP2
MDA11 C19 J23 WE#
FBA_D11 FBA_CMD11 WE# [84,85]
MDA12 C18 M25 BA0 ROM_SCLK_GPU
FBA_D12 FBA_CMD12 BA0 [84,85] [81] ROM_SCLK_GPU
MDA13 D18 K27 FBA_CMD_13
MDA14 B18 G25 MAA12 ROM_SI_GPU
FBA_D14 FBA_CMD14 MAA12 [84,85] [81] ROM_SI_GPU
MDA15 C16 L24 MEM_RST
FBA_D15 FBA_CMD15 MEM_RST [84,85]
MDA16 E21 K23 MAA7 ROM_SO_GPU
FBA_D16 FBA_CMD16 MAA7 [84,85] [81] ROM_SO_GPU
MDA17 F21 K24 MAA10
FBA_D17 FBA_CMD17 MAA10 [84,85]
MDA18 D20 G22 FBA_CMD_18
MDA19 F20 FBA_D19 FBA_CMD19 K25 MAA0
MAA0 [84,85] Logical Strap Bit Mapping
MDA20 D17 H22 MAA9
30KR2F-GP
FBA_D20 FBA_CMD20 MAA9 [84,85] Resistor Pull-Up Pull-Down
1
Do Not Stuff
Do Not Stuff
MDA21 F18 M26 MAA6
20KR2F-L-GP
10KR2F-2-GP
FBA_D21 FBA_CMD21 MAA6 [84,85] 5Kohms 1000 0000
Do Not Stuff
R8307
R8301
R8316
R8304
R8308
R8313
MDA22 D16 H24 FBA_CMD_22
FBA_D22 FBA_CMD22 FBA_CMD_22 [84] 10Kohms 1001 0001
MDA23 MAA8
MDA24
E16
A22
FBA_D23 FBA_CMD23 F27
J26 FBA_CMD_24
MAA8 [84,85]
15Kohms 1010 0010 DY DY DY
MDA25 C24 G24 MAA1 20Kohms 1011 0011
MAA1 [84,85]
2
MDA26 FBA_D25 FBA_CMD25 MAA13
D21 FBA_D26 FBA_CMD26 G27 MAA13 [84,85] 25Kohms 1100 0100
MDA27 B22 M24 BA2
FBA_D27 FBA_CMD27 BA2 [84,85] 30Kohms 1101 0101
MDA28 C22 K22 FBA_CMD_28
MDA29 A25 J22 FBA_CMD_29
FBA_CMD_29 [84]
35Kohms 1110 0110
C MDA30 FBA_D29 FBA_CMD29 FBA_CMD_30 C
B25 FBA_D30 FBA_CMD30 L22 FBA_CMD_30 [84] 45Kohms 1111 0111
MDA31 A26
MDA32 FBA_D31
MDA33
U24
V24
FBA_D32
C26 DQMA#0
2009/06/05
FBA_D33 FBA_DQM0 DQMA#0 [84]
MDA34 V23 B19 DQMA#1
MDA35 R24 FBA_D35 FBA_DQM2 D19 DQMA#2
DQMA#2 [84] Strap0 Strap1 Strap2
MDA36 T23 D23 DQMA#3 USER_BIT0 1 3GIO_PADCFG_LUT_ADR0 0 PCI_DEVID_0 1
MDA37 R23 T24 DQMA#4
MDA38 FBA_D37 FBA_DQM4 DQMA#5
DQMA#4 [85] USER_BIT1 1 3GIO_PADCFG_LUT_ADR1 1 PCI_DEVID_1 0
P24 FBA_D38 FBA_DQM5 AA23 DQMA#5 [85]
MDA39 P22 AB27 DQMA#6 USER_BIT2 1 3GIO_PADCFG_LUT_ADR2 1 PCI_DEVID_2 1
MDA40 AC24 T26 DQMA#7
DQMA#7 [85]
USER_BIT3 1 3GIO_PADCFG_LUT_ADR3 1 PCI_DEVID_3 0
MDA41 FBA_D40 FBA_DQM7
AB23 FBA_D41
MDA42 AB24 FBA_D42
EDID is used Reserved N11M-GE1 GPU Device ID=0x0A75
MDA43 W24 D25 QSA#0
FBA_D43 FBA_DQS_RN0 QSA#0 [84]
MDA44 AA22 A18 QSA#1
MDA45 W23 E18 QSA#2
MDA46 W22 FBA_D46 FBA_DQS_RN3 B24 QSA#3
QSA#3 [84] ROM_SI_GPU ROM_SO_GPU ROM_SCLK_GPU
MDA47 V22 R22 QSA#4 RAM_CFG0 VGA_DEVICE 1 PEX_PLL_EN_TERM 0
MDA48 AA25 Y24 QSA#5
MDA49 FBA_D48 FBA_DQS_RN5 QSA#6
QSA#5 [85] RAM_CFG1 SMB_ALT_ADDR 0 SLOT_CLK_CONFIG 1
W27 FBA_D49 FBA_DQS_RN6 AA27 QSA#6 [85]
MDA50 W26 R27 QSA#7 RAM_CFG2 FB_0_BAR_SIZE 0 SUB_VENDOR 0
MDA51 W25 FBA_D51
RAM_CFG3 XCLK_417 0 PCI_DEVID_4 1
MDA52 AB25
MDA53 FBA_D52 QSA0
AB26 FBA_D53 FBA_DQS_WP0 C25 QSA0 [84]
MDA54 AD26 FBA_D54 FBA_DQS_WP1 A19 QSA1
QSA1 [84] Default setting: SAMSUNG sDDR3 64Mx16BIT-->20K pull down (0x0011)
MDA55 AD27 E19 QSA2 If use Hynix sDDR3 64Mx16BIT(0x0010), R8308 change to 15K.
FBA_D55 FBA_DQS_WP2 QSA2 [84]
MDA56 V25 A24 QSA3
FBA_D56 FBA_DQS_WP3 QSA3 [84]
MDA57 R25 FBA_D57 FBA_DQS_WP4 T22 QSA4
QSA4 [85] RAM_CFG[3:0] Config FB_BUS Width Definitions
MDA58 V26 AA24 QSA5 0000
B FBA_D58 FBA_DQS_WP5 QSA5 [85] B
MDA59 V27 AA26 QSA6
MDA60 FBA_D59 FBA_DQS_WP6 QSA7
QSA6 [85] 0001
R26 FBA_D60 FBA_DQS_WP7 T27 QSA7 [85]
MDA61 T25 0010 64MX16 DDR3 64Bit Hynix
FBA_D61
MDA62 N25 0011 64MX16 DDR3 64Bit Samsung
MDA63 FBA_D62 CLKA0
N26 FBA_D63 FBA_CLK0 F24
F23 CLKA0# CLKA0 [84] 0100 Default
FBA_CLK0# CLKA0# [84] 0101
40D2R2F-GP 2 1R8303 FB_CAL_PU_GND A15 N24 CLKA1 0110
40D2R2F-GP FB_CAL_PU_GND FBA_CLK1 CLKA1 [85] 0111
+1.5V_RUN_GPU 2 1R8314 FB_CAL_PD_VDDQ B15 FB_CAL_PD_VDDQ FBA_CLK1# N23 CLKA1#
CLKA1# [85]
60D4R2F-GP 1 2R8315 FB_CAL_TERM_GND B16 FB_CAL_TERM_GND
AC19 FB_PLLAVDD FBA_DEBUG M22
L8301 R19 FB_PLLAVDD
SUB_VENDOR XCLK_417 PEX_PLL_EN_TERM
1 2
16mil +FB_PLLVDD T19
FB_VREF A16
nVIDIA recommend
0 No VBIOS ROM 0 277MHz(POR) 0 Disable (POR)
+1.05V_GFX_PCIE FB_DLLAVDD 1 BIOS ROM present 1 Reserved 1 Enable
BLM18SG331TN1D-GP
N11M-GE1-S-A2-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
3GIO_PADCFG USER[3:0]
C8302
C8301
0000 Desktop 1111 Use EDID to detect panel settings

Place near GPU 1110 Notebook (POR)
2
SLOT_CLOCK_CFG
0 GPU and MCH do not share a common reference clock
1 GPU and MCH share a common reference clock (POR)
FB_PLLAVDD+FB_DLLAVDD=100mA
A 1st Samsung A
DW
07/10 Updated
1.+FB_PLLVDD power rail corrected to +1.05V_GFX_PCIE
Wistron Corporation
Title
VGA-MEMORY/STRAPS(4/4)
www.vinafix.vn
A3 Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
+1.5V_RUN_GPU +1.5V_RUN_GPU
MDA[0..63] [83,85] MDA[0..63] [83,85]
U8401 U8402
K8 E3 MDA17 K8 E3 MDA7
VDD DQL0 MDA18 VDD DQL0 MDA6
K2 F7 K2 F7
N1 F2 N1 F2
R9 F8 R9 F8
B2 H3 B2 H3
D9 H8 D9 H8
G7 G2 G7 G2
R1 H7 MDA[0..63] [83,85] R1 H7 MDA[0..63] [83,85]
VDD DQL7 VDD DQL7
D N9 N9 D
VDD MDA13 VDD MDA29
D7 D7
DQU0 MDA14 DQU0 MDA24
A8 C3 A8 C3
+1.5V_RUN_GPU VDDQ DQU1 MDA9 +1.5V_RUN_GPU VDDQ DQU1 MDA30
A1
VDDQ DQU2
C8
MDA8
A1
VDDQ DQU2
C8
MDA28
UMA
C1
C9
VDDQ DQU3
C2
A7 MDA12
UMA C1
C9
VDDQ DQU3
C2
A7 MDA25 swap for layout
1
1
VDDQ DQU4 VDDQ DQU4
D2
VDDQ DQU5
A2 MDA11
MDA15
swap for layout D2
VDDQ DQU5
A2 MDA26
MDA31
E9 B8 E9 B8
R8404 VDDQ DQU6 MDA10 R8403 VDDQ DQU6 MDA27
F1 A3 F1 A3
1KR2F-3-GP VDDQ DQU7 1KR2F-3-GP VDDQ DQU7
H9 H9
VDDQ QSA1 VDDQ QSA3
H2 C7 H2 C7
2
2
VDDQ DQSU QSA1 [83] VDDQ DQSU QSA3 [83]
B7 QSA#1 B7 QSA#3
DQSU# QSA#1 [83] DQSU# QSA#3 [83]
VREFA1 H1 VREFA2 H1
VREFDQ QSA2 VREFDQ QSA0
M8 F3 QSA2 [83] M8 F3 QSA0 [83]
VREFCA DQSL VREFCA DQSL
1 2 ZQ_VRAM11 L8 G3 QSA#2 1 2 ZQ_VRAM12 L8 G3 QSA#0
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
QSA#2 [83] QSA#0 [83]
1
1
ZQ DQSL# ZQ DQSL#
C8420
C8421
R8406 243R2F-2-GP R8407 243R2F-2-GP
1
1
K1 FBA_CMD_30 K1 FBA_CMD_30
MAA0 ODT FBA_CMD_30 [83] MAA0 ODT FBA_CMD_30 [83]
R8401 N3 R8402 N3
[83,85] MAA0 A0 [83,85] MAA0 A0
1KR2F-3-GP MAA1 P7 1KR2F-3-GP MAA1 P7
2
2
[83,85] MAA1 FBA_CMD_22 A1 FBA_CMD_29 [83,85] MAA1 FBA_CMD_22 A1 FBA_CMD_29
[83] FBA_CMD_22 P3 L2 FBA_CMD_29 [83] [83] FBA_CMD_22 P3 L2 FBA_CMD_29 [83]
2
2
1
FBA_CMD_24 A2 CS# MEM_RST FBA_CMD_24 A2 CS# MEM_RST
[83] FBA_CMD_24 N2 T2 MEM_RST [83,85] [83] FBA_CMD_24 N2 T2 MEM_RST [83,85]
FBA_CMD_0 A3 RESET# R8409 FBA_CMD_0 A3 RESET#
[83] FBA_CMD_0 P8 [83] FBA_CMD_0 P8
1
FBA_CMD_2 A4 FBA_CMD_2 A4
[83] FBA_CMD_2 P2 10KR2J-3-GP [83] FBA_CMD_2 P2
MAA6 A5 R8410 MAA6 A5
[83,85] MAA6 R8 T7 [83,85] MAA6 R8 T7
MAA7 A6 NC#T7 MAA7 A6 NC#T7
[83,85] MAA7 R2 L9 10KR2J-3-GP [83,85] MAA7 R2 L9
2
MAA8 A7 NC#L9 MAA8 A7 NC#L9
[83,85] MAA8 T8 L1 [83,85] MAA8 T8 L1
R3 J9 R3 J9
2
[83,85] MAA9 MAA10 A9 NC#J9 [83,85] MAA9 MAA10 A9 NC#J9
[83,85] MAA10 L7 J1 [83,85] MAA10 L7 J1
MAA11 A10/AP NC#J1 MAA11 A10/AP NC#J1
[83,85] MAA11 R7 [83,85] MAA11 R7
MAA12 A11 MAA12 A11
[83,85] MAA12 N7 [83,85] MAA12 N7
MAA13 A12/BC# MAA13 A12/BC#
[83,85] MAA13 T3 J8 [83,85] MAA13 T3 J8
A13 VSS A13 VSS
M7
NC#M7 VSS
M1
M9
Added MEN_RST M7
NC#M7 VSS
M1
M9
VSS VSS
BA0 VSS
J2 10K pull down R CLKA0 BA0 VSS
J2
[83,85] BA0 M2 P9 [83,85] BA0 M2 P9
[83,85] BA1
BA1 N8
BA0
BA1
VSS
VSS
G8 2009/05/28 [83,85] BA1
BA1 N8
BA0
BA1
VSS
VSS
G8
BA2 M3 B3 BA2 M3 B3
[83,85] BA2 [83,85] BA2
1
BA2 VSS BA2 VSS
T1 T1
VSS R8418 VSS
A9 A9
CLKA0 VSS 243R2F-2-GP CLKA0 VSS
[83] CLKA0 J7 T9 [83] CLKA0 J7 T9
CLKA0# CK VSS CLKA0# CK VSS
[83] CLKA0# K7 E1 [83] CLKA0# K7 E1
CK# VSS CK# VSS
C P1 P1 C
2
FBA_CMD_18 VSS FBA_CMD_18 VSS
[83] FBA_CMD_18 UMA K9 UMA [83] FBA_CMD_18 K9
1
CKE CLKA0# CKE

G1 G1
swap for layout VSSQ swap for layout VSSQ
R8411
F9 F9
10KR2J-3-GP
DQMA#1 VSSQ DQMA#3 VSSQ

[83] DQMA#1 D3 E8 [83] DQMA#3 D3 E8
DQMA#2 DMU VSSQ DQMA#0 DMU VSSQ
[83] DQMA#2 E7 E2 [83] DQMA#0 E7 E2
DML VSSQ DML VSSQ
D8 Revised FBCLK Termination D8
2
VSSQ VSSQ
D1 D1
VSSQ VSSQ
[83,85] WE#
WE#
CAS#
L3
WE# VSSQ
B9 resistor value [83,85] WE#
WE#
CAS#
L3
WE# VSSQ
B9
[83,85] CAS# K3 B1 [83,85] CAS# K3 B1
CAS# VSSQ CAS# VSSQ
Added CKE [83,85] RAS#
RAS# J3
RAS# VSSQ
G9 2009/06/05 [83,85] RAS#
RAS# J3
RAS# VSSQ
G9
10K pull down R K4W1G1646E-HC12-GP

Close to VRAM side K4W1G1646E-HC12-GP
2009/06/05
64X16 SAMSUNG K4W1G1646E-HC12 P/N:72.41164.H0U
64X16 HYNIX H5TQ1G63BFR-12C P/N:72.51G63.C0U
+1.5V_RUN_GPU Place under / near VRAM +1.5V_RUN_GPU Place under / near VRAM
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
C8422
C8423
C8424
C8425
C8427
C8426
C8428
C8429
1
1
2
2
B B
+1.5V_RUN_GPU +1.5V_RUN_GPU
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
1
C8404
C8408
C8410
C8411
C8412
C8405
C8409
C8414
C8415
C8413
2
2
Revised decoupling C 2009/05/28 Revised decoupling C 2009/05/28
A A
1st Samsung
Wistron Corporation
Title
VRAM(1/2)
www.vinafix.vn
A2
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
+1.5V_RUN_GPU
+1.5V_RUN_GPU
MDA[0..63] [83,84]
U8501
MDA[0..63] [83,84]
U8502
K8 E3 MDA46
VDD DQL0 MDA42 MDA63
K2 F7 K8 E3
N1 F2 K2 F7
R9 F8 N1 F2
B2 H3 R9 F8
D9 H8 B2 H3
G7 G2 D9 H8
D R1 H7 MDA[0..63] [83,84] G7 G2 D
VDD DQL7 VDD DQL6 MDA56
N9 R1 H7 MDA[0..63] [83,84]
VDD MDA51 VDD DQL7
D7 N9
DQU0 MDA52 VDD MDA36
A8 C3 D7
+1.5V_RUN_GPU VDDQ DQU1 MDA54 DQU0 MDA38
A1 C8 A8 C3
VDDQ DQU2 MDA49 +1.5V_RUN_GPU VDDQ DQU1 MDA33
C1 C2 A1 C8
VDDQ DQU3 MDA48 VDDQ DQU2 MDA39
C9 A7 C1 C2
1

D2 A2 C9 A7
1
E9 B8 D2 A2
R8510 VDDQ DQU6 MDA53 VDDQ DQU5 MDA32
F1 A3 E9 B8
1KR2F-3-GP VDDQ DQU7 R8501 VDDQ DQU6 MDA35
H9 F1 A3
VDDQ QSA6 1KR2F-3-GP VDDQ DQU7
H2 C7 H9
2
VDDQ DQSU QSA6 [83] VDDQ

B7 QSA#6 H2 C7 QSA4
2
VREFA3 DQSU# QSA#6 [83] VDDQ DQSU QSA#4 QSA4 [83]
H1 B7 QSA#4 [83]
VREFDQ QSA5 VREFA4 DQSU#
M8 F3 QSA5 [83] H1
VREFCA DQSL VREFDQ
1 2 ZQ_VRAM21 L8 G3 QSA#5 M8 F3 QSA7
SCD01U16V2KX-3GP
QSA#5 [83] QSA7 [83]

1
ZQ DQSL# VREFCA DQSL

2 ZQ_VRAM22 QSA#7
C8503
R8509 243R2F-2-GP 1 L8 G3
SCD01U16V2KX-3GP
QSA#7 [83]
1
1
FBA_CMD_28 ZQ DQSL#
C8506
K1 R8503 243R2F-2-GP
FBA_CMD_28 [83]
1
R8507 MAA0 ODT FBA_CMD_28
[83,84] MAA0 N3 K1 FBA_CMD_28 [83]
1KR2F-3-GP MAA1 A0 R8504 MAA0 ODT
[83,84] MAA1 P7 [83,84] MAA0 N3
2
FBA_CMD_4 A1 FBA_CMD_8 1KR2F-3-GP MAA1 A0

P3 L2 P7
2
2
[83] FBA_CMD_4 FBA_CMD_8 [83] [83,84] MAA1
1
FBA_CMD_6 A2 CS# MEM_RST FBA_CMD_4 A1 FBA_CMD_8
N2 T2 P3 L2
2
[83] FBA_CMD_6 A3 RESET# MEM_RST [83,84] [83] FBA_CMD_4 A2 CS# FBA_CMD_8 [83]
FBA_CMD_5 P8 R8506 FBA_CMD_6 N2 T2 MEM_RST
[83] FBA_CMD_5 FBA_CMD_13 A4 [83] FBA_CMD_6 FBA_CMD_5 A3 RESET# MEM_RST [83,84]
[83] FBA_CMD_13 P2 10KR2J-3-GP [83] FBA_CMD_5 P8
MAA6 A5 FBA_CMD_13 A4
[83,84] MAA6 R8 T7 [83] FBA_CMD_13 P2
MAA7 A6 NC#T7 MAA6 A5
R2 L9 R8 T7
2
[83,84] MAA7 MAA8 A7 NC#L9 [83,84] MAA6 MAA7 A6 NC#T7
[83,84] MAA8 T8 L1 [83,84] MAA7 R2 L9
[83,84] MAA9 R3 J9 [83,84] MAA8 T8 L1
MAA10 A9 NC#J9 MAA9 A8 NC#L1
[83,84] MAA10 L7 J1 [83,84] MAA9 R3 J9
MAA11 A10/AP NC#J1 MAA10 A9 NC#J9
[83,84] MAA11 R7 [83,84] MAA10 L7 J1
MAA12 A11 MAA11 A10/AP NC#J1
[83,84] MAA12 N7 [83,84] MAA11 R7
MAA13 A12/BC# MAA12 A11
[83,84] MAA13 T3 J8 [83,84] MAA12 N7
A13 VSS MAA13 A12/BC#
M7 M1 [83,84] MAA13 T3 J8
NC#M7 VSS A13 VSS
M9 M7 M1
VSS NC#M7 VSS
J2 M9
BA0 VSS CLKA1 VSS
[83,84] BA0 M2 P9 J2
BA1 BA0 VSS BA0 VSS
[83,84] BA1 N8 G8 [83,84] BA0 M2 P9
BA2 BA1 VSS BA1 BA0 VSS
[83,84] BA2 M3 B3 [83,84] BA1 N8 G8
1
BA2 VSS BA2 BA1 VSS
T1 [83,84] BA2 M3 B3
VSS R8517 BA2 VSS
A9 T1
CLKA1 VSS 243R2F-2-GP VSS
[83] CLKA1 J7 T9 A9
CLKA1# CK VSS CLKA1 VSS
C
[83] CLKA1# K7 E1 [83] CLKA1 J7 T9 C
CK# VSS CLKA1# CK VSS
P1 K7 E1
2
FBA_CMD_7 VSS CLKA1# [83] CLKA1# CK# VSS
[83] FBA_CMD_7 K9 P1
CKE FBA_CMD_7 VSS
G1 [83] FBA_CMD_7 K9
1
VSSQ CKE
F9 G1
R8508 DQMA#6 VSSQ VSSQ
[83] DQMA#6 D3 E8 F9
DQMA#5 DMU VSSQ DQMA#4 VSSQ
10KR2J-3-GP
[83] DQMA#5 E7 E2 [83] DQMA#4 D3 E8
DML VSSQ DQMA#7 DMU VSSQ
VSSQ
D8
D1
Revised FBCLK Termination [83] DQMA#7 E7
DML VSSQ
E2
D8
2
VSSQ VSSQ
[83,84] WE#
WE#
CAS#
L3
WE# VSSQ
B9 resistor value WE# VSSQ
D1
[83,84] CAS# K3 B1 [83,84] WE# L3 B9
Added CKE [83,84] RAS#
RAS# J3
CAS#
RAS#
VSSQ
VSSQ
G9 2009/06/05 [83,84] CAS#
CAS# K3
WE#
CAS#
VSSQ
VSSQ
B1
RAS# J3 G9
[83,84] RAS# RAS# VSSQ
10K pull down R K4W1G1646E-HC12-GP
Close to VRAM side
2009/06/05 K4W1G1646E-HC12-GP
+1.5V_RUN_GPU Place under / near VRAM +1.5V_RUN_GPU Place under / near VRAM
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
C8534
C8533
C8531
C8532
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
1
C8538
C8537
C8536
C8535
1
1
2
2
B B
+1.5V_RUN_GPU
+1.5V_RUN_GPU
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C8520
C8519
C8518
C8517
C8516
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
C8525
C8524
C8523
C8522
C8521
1
1
2
2
A A
1st Samsung
Wistron Corporation
Title
VRAM
www.vinafix.vn
A2
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_GFX
Vout=0.704V*(R1+R2)/R2
+PWR_SRC +PWR_SRC_GFX_CORE_
D D
PG8617
1 2 +PWR_SRC_GFX_CORE_
Do Not Stuff
PG8613
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
1 2
Do Not Stuff
PC8603
1
1
PC8611
PC8606
PC8609
PC8604
Do Not Stuff
PG8620 +3.3V_RUN_GPU
DY
1 2
2
1
5
6
7
8
D
D
D
D
Do Not Stuff PR8634 PU8601
PG8605 Do Not Stuff DIS
1 2
DY SI7686DP-T1-GP
Thermal Design Current = 12.9A
2
Do Not Stuff Max Current = 16.77A
G
S
S
S
PG8611
1 2
[25] GFX_CORE_PGOOD 18.45A<OCP<21.81A
4
3
2
1
Do Not Stuff
2009/09/01 PU8603 PR8633 PC8616
2D2R3J-2-GP SCD1U25V3KX-GP +VCC_GFX_COREP +VCC_GFX_CORE
PR8632 1 11
+GFX_CORE_TRIP PGOOD GND +GFX_CORE_VBST 1
1 2 2 TRIP VBST 10 2 +GFX_CORE_VBST12 1 PL8601
49K9R2F-L-GP +GFX_CORE_EN 3 9 +GFX_CORE_DRVH PG8601
+GFX_CORE_FB EN DRVH +GFX_CORE_SW
4 8 1 2 2 1
PR8631 1 +GFX_CORE_CCM VFB SW +5V_ALW IND-1D5UH-34-GP
[37] GFX_CORE_EN 2 5 CCM V5IN 7
SCD1U10V2KX-4GP
1KR2F-3-GP 6 +GFX_CORE_DRVL Do Not Stuff
Do Not Stuff
DRVL
1
1
PTC8601 PTC8602 PG8619
SE330U2VDM-L-GP
Do Not Stuff
C PR8638 1 PR8604 PC8617 PR8606 C
DY 2
DY DY 2 1
1+GFX_CORE_LL_R
[22,34,37,42,50,51] PM_SLP_S3#
5
6
7
8
PG8604
470KR2F-GP TPS51218DSCR-GP-U SC1U10V2KX-1GP PU8604 Do Not Stuff
2
D
D
D
D
1
SIR460DP-T1-GE3-GP
PC8602
2
SC1KP50V2KX-1GP
PG8618
2
2 1
2
2
PC8634
Do Not Stuff
1 GPU_VDD_SENS_GAP
S
S
S
PG8622
G
1 2
4
3
2
1
2009/08/05 PC8614 Do Not Stuff
Do Not Stuff PG8612
DY
2
1 2
Do Not Stuff
PG8621
1 2
PR8603 Do Not Stuff

Frequency setting 5K1R2F-2-GP PG8614
1 2
470K -->290KHz
2
Do Not Stuff
200K -->340KHz PG8607
+GFX_CORE_FB 1 2
100K -->380KHz Do Not Stuff
39K -->430KHz
1
PG8606
PR8613 PR8611 PR8607 1 2
B B
75KR2F-GP 36K5R2F-GP 19K6R2F-GP
+3.3V_RUN_GPU Do Not Stuff
PD8601 PG8608
2
PD8601_A 1
PWRCNTL_0#
K A 2 1 2
2009/08/26
1
B0530WS-7-F-GP PR8614 Do Not Stuff
PR8619 5K1R2F-2-GP PG8602
10KR2F-2-GP 1 2
PWRCNTL_1#
PQ8602 Do Not Stuff
2
PR8618 2N7002A-7-GP PG8615
[81] PWRCNTL_0 2 1 PWRCNTL_0_R G 1 2
10KR2F-2-GP
2
+3.3V_RUN_GPU
SCD1U16V2KX-3GP
Do Not Stuff
Do Not Stuff
C8610
PR8602
PG8610
S
DY 2009/08/05 1 2
2
1
PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE 2009/08/05

PR8620 Do Not Stuff
D
1
H H 1.03V 10KR2F-2-GP PG8609
PQ8601 1 2
H L 0.85V PR8617 2N7002A-7-GP
2
2 1 PWRCNTL_1_R G Do Not Stuff

L L 0.8V [81] PWRCNTL_1
PG8603
2
SCD1U16V2KX-3GP
10KR2F-2-GP 1 2
Do Not Stuff
C8608
PR8616
DY
S
Do Not Stuff
2
PG8616
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L 1 2
1
A Inductor: 1.5UH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat =33Arms 68.1R510.10J PD8615 1st Samsung A
K A PD8615_A 1 2 Do Not Stuff
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 B0530WS-7-F-GP PR8615
Wistron Corporation
5K1R2F-2-GP
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Switching freq-->350KHz Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51218 +VCC_GFX_CORE
Custom
DW Calpella (Discrete) X00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
+3.3V_RTC_LDO
+3.3V_RUN_GPU +15V_ALW
2
R8714
2
100KR2J-1-GP +3.3V_RUN_GPU
R8711
Peak current:360mA
1
3D3V_VGA_ON# 100KR2J-1-GP Design current: 252mA
1
1
C8704
SC10U6D3V5KX-1GP +3.3V_ALW
2
Q8710
4
D D
Q8707 AO3434L-GP
D8706 DMN66D0LDW-7-GP R8713
A K 10KR2J-3-GP S D
RUN_ON_3D3GFX_R 2 1 RUN_ON_3D3GFX
3
BAS16XV2T1G-GP-U
R8778
1
2KR2F-3-GP AO3434L-GP MAX 4.2A
G
2 1 C8708
[37] 3.3V_RUN_GPU_EN SCD01U50V2KX-1GP Rds(on) = 52 mOhm (Max)
2
C8786 1 3.3V_GPU_EN_R
SC1U6D3V2KX-GP
2
+3.3V_RTC_LDO
+1.05V_GFX_PCIE: +15V_ALW
2
R8712
2
100KR2J-1-GP +1.05V_GFX_PCIE
R8708
1
1D05V_VGA_ON# 100KR2J-1-GP
Design current:3550mA
1
1
C8701
SC10U6D3V5KX-1GP +1.05V_VTT
2
6
4
U8703
Q8704 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
R8716 S D
3 6
RUN_ON_1D05V_R 2 10KR2J-3-GP
1 RUN_ON_1D05V 4 G D 5
1
C C
FDS8880-NL-GP
1
assign GPIO Added discharge circuit 10.7A
C8705
2009/05/28 2009/06/17 SCD01U50V2KX-1GP Rds=12m ohm
2
1.05V_GFX_ON +1.5V_RUN_GPU
[37] 1.05V_GFX_ON
2
R8709 Place near device side(VGA chip),
+3.3V_RTC_LDO
+1.5V_RUN_GPU: +15V_ALW
DY Do Not Stuff use 10 mil trace between power
rail and Q8701 Drain
1Q87_D
2
R8715
D
2
100KR2J-1-GP +1.5V_RUN_GPU
R8710
Peak current:4230mA
1
1D5V_VGA_ON# Q8701
100KR2J-1-GP
1D5V_VGA_ON# G
DY Do Not Stuff Design current:2961mA
1
1
C8702
S
SC10U6D3V5KX-1GP +1.5V_SUS
2
6
U8705
Q8705 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
R8717 S D
3 6
RUN_ON_1D5V_R 2 10KR2J-3-GP
1 RUN_ON_1D5V 4 G D 5
1
FDS8880-NL-GP
1
10.7A
C8707
SCD01U50V2KX-1GP Rds=12m ohm
2
B B
1D5V_VGA_ON
[37] 1D5V_VGA_ON
A A
1st Samsung
Wistron Corporation
Title
LDO 1.8V
www.vinafix.vn
Custom
Vostro Calpella SA
5 4 3 2 1
5 4 3 2 1
Item Page# Date Request By Issue description Solution Description Rev.
D D
C C
B B
A 1st Samsung A
Wistron Corporation
Title
Change List(1/3)
www.vinafix.vn
A3
Vostro Calpella SA
5 4 3 2 1

dw30 Cp-Dis 09288 RSA 0903 1

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dw30 Cp-Dis 09288 RSA 0903 1

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5 4 3 2 1

DW30 Winery CALPELLA DIS N11M-GE1 Schematics

L1: Top Project code : 91.4EX01.001 +PWR_SRC +VCC_CORE

L2: GND Part Number : 48.4EX11.0SA

L5: VCC INPUTS OUTPUTS

USB 2.0 USB 2.0 x 1 PCIE x 1 Mini-Card

(3 in 1) 14 USB 2.0/1.1 ports Right Side:

480Mbps SATA ports (6) Free fall sensor USB 2.0 x 1

HP OUT INPUTS OUTPUTS

ISL62883 ADP3211 TPS51218 TPS51218DSCR

+5V_ALW +3.3V_ALW +1.5V_CPU

+5V_USB2 +5V_RUN +5V_USB1 +3.3V_LAN +3.3V_CARDAUX +3.3V_RUN +1.8V_RUN +1.8V_RUN_GPU

Regulator LDO Switch

PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN

2N7002SPT DIMM 2 NC7SB3157P6X-1GP

Card WLAN GND S

SMB_CLK ‧ PCH_SMBCLK SMB_CLK

Free fall +3.3V_RUN DY +5V_CRT_RUN

KBC SMBus Block Diagram N11M-GE1 +3.3V_RUN

Thermal Block Diagram Audio Block Diagram

DP2 VGA_THERMDA DPLUS

Thermal/Audio Block Diagram

Default (SPI): Leave both GNT0# and GNT1# floating. No pull up

Enable Intel Anti-Theft Technology:Connect to Vcc3_3

Platform design should provide appropriate pull-up or pull-down

1 GPIO8 Weak internal pull-up. Do not pull low.

Do Not Stuff TP701 1 TP_CPU_1# 19 31

FSC SPEED 100MHz

Clock Generator SLG8SP585

PCI EXPRESS -- GRAPHICS

JTAG & BPM

SB_CK0 W8 M_CLK_DDR2 [19]

M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

DDR SYSTEM MEMORY - B

A CLARKUNF 1st Samsung A

TP1117 1 SB_DIMM_VREF# H17

15 -> 0, 14 -> 1, ... CFG10

0:Enabled; An external Display Port SA_CK2

CFG7 Clarksfield (only for early samples pre-ES1) -

Note: Only temporary for early CFD sample

Vostro Calpella X00

1.1V RAIL POWER

VCC VTT0 C1233 C1234

R28 AJ34 VCC_SENSE [47]

Vostro Calpella X00

+1.5V_CPU +1.5V_CPU +1.5V_CPU +1.5V_CPU

C1308 C1309 +1.05V_VTT

PEG & DMI

C1312 C1313 C1314 C1315 J25 H20

H27 VTT1 VTT1 H19

Size Document Number

AT20 VSS VSS AE34

NCYF TEST PIN:

D SSID = MEMORY M_A_A0

M_A_DQ22 DQ21 VDD1

M_A_DQ46 DQ45 VSS

27 DQS1# VSS 127

M_A_DQS#5 DQS4# VSS

www.vinafix.vn Size Document Number

M_B_DQ45 DQ44 VSS M_CLK_DDR#2

M_B_DQS#5 152 138

M_B_DQS#6 169 139

Digital Display Interface