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VER : 3A
BOM P/N Description Z09 SYSTEM BLOCK
DIAGRAM
D D
Dual Channel DDR III
Memory Down 1333/1600 MHZ
DDRIII-SODIMM1 IMC NVIDIA GPU
P13 PCI-E
PCIE
Ivy Bridge X16 N13P-GV
1GB (128Mb x 32 IO x 4 pcs)
256MB*16 2.5GT/s
BGA 1023
P27,28,29,30,31,32
17W
P2,3,4,5,6 X'TAL
27.0MHz
Max. 2G P14
eDP eDP Conn.
mSATA - HDD FDI DMI P15
P20
DMI(x4)

SATA - HDD FDI DMI


SATA
P20

C C
SATA - ODD SATA
P21 Display
HDMI
HDMI Conn.
USB3.0(USB2.0) P16
USB3.0 *2
USB2.0 *2
USB Port
P23

USB3.0(USB2.0) PCIE-8
USB3.0
USB Port Panther Point PCI-E x1 MINI CARD
P23 WLAN+BT
USB-10 P19
PCI-E x1 PCH
BGA 989 PCI-E x1
BCM57780
USB Port P7, 8, 9, 10, 11, 12 PCIE-3 RJ45 Conn.
(Charger)P23 GIGA LAN P18
P17
X'TAL
USB2.0 32.768KHz X'TAL
25MHz
B B
USB2.0
CCD Conn. USB2.0
X'TAL
P15 25MHz
PCIE-2 RTS5209-GR Cardreader
Cardreader Conn.(2in1)
P8 BATTERY RTC
controller P19
SPI
SPI ROM
Azalia IHDA P8
Daugther board
LPC
2M+4M

LPC
Batery Charger P31 +1.05V P34 +VGFX_AXG P33
ALC271-VB6 WPCE885
DMIC
AUDIO CODEC EC
Daugther board P19 P24 3V/5V P32 +1.8V/+1V P37 CPU core P33

Discharger
+VGPU_CORE P38 +VGPU_IO P38 P37
BOM Option Table
A A
MIC/HP JACK K/B Con. Touch Pad
Reference Description Con.
P22 P19 Thermal Protection
EV@ Optimize SKU
P37
SNB@ For Sandy bridge.
IVB@ For Ivy bridge.
IV@ For UMA. W25X16VSS1G EM-6781-T3 Fan Driver Quanta Computer Inc.
Speaker HALL SENSOR
* do not stuff SPI FLASH P8 P15 P19 PROJECT : Z09
Size Document Number Rev
3A
Block Diagram
Date: Monday, April 09, 2012 Sheet 1 of 40
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Ivy Bridge Processor (DMI,PEG,FDI)


PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
U9A - typical impedance = 43 mohms
G3 PEG_COMP PEG_ICOMPO 12mil PEG_ICOMPO signals should be routed with
PEG_ICOMPI G1
M2 PEG_ICOMPO G4 PEG_ICOMPI, PEG_RCOMPO 4mil, - max length = 500 mils
<7> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO - typical impedance = 14.5 mohms
P6
<7> DMI_TXN1 DMI_RX#[1]
<7> DMI_TXN2 P1 GRN[0..15] <25>
P10 DMI_RX#[2] H22 GRN15
D <7> DMI_TXN3 DMI_RX#[3] PEG_RX#[0] D
J21 GRN14
N3 PEG_RX#[1] B22 GRN13
<7> DMI_TXP0 DMI_RX[0] PEG_RX#[2]
P7 D21 GRN12
<7> DMI_TXP1 DMI_RX[1] PEG_RX#[3]

DMI
<7> DMI_TXP2 P3 A19 GRN11
P11 DMI_RX[2] PEG_RX#[4] D17 GRN10
<7> DMI_TXP3 DMI_RX[3] PEG_RX#[5] B14 GRN9
K1 PEG_RX#[6] D13 GRN8
<7> DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
M8 A11 GRN7
<7> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
<7> DMI_RXN2 N4 B10 GRN6
R2 DMI_TX#[2] PEG_RX#[9] G8 GRN5
<7> DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8 GRN4
K3 PEG_RX#[11] B6 GRN3
<7> DMI_RXP0 DMI_TX[0] PEG_RX#[12]
M7 H8 GRN2
<7> DMI_RXP1 DMI_TX[1] PEG_RX#[13]
<7> DMI_RXP2 P4 E5 GRN1
T3 DMI_TX[2] PEG_RX#[14] K7 GRN0
<7> DMI_RXP3 DMI_TX[3] PEG_RX#[15]
GRP[0..15] <25>
K22 GRP15
PEG_RX[0] K19 GRP14
PEG_RX[1] C21 GRP13
U7 PEG_RX[2] D19 GRP12
<7> FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
W11 C19 GRP11
<7> FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
<7> FDI_TXN2 W1 D16 GRP10

PCI EXPRESS -- GRAPHICS


AA6 FDI0_TX#[2] PEG_RX[5] C13 GRP9
<7> FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
<7> FDI_TXN4 W6 D12 GRP8
V4 FDI1_TX#[0] PEG_RX[7] C11 GRP7
<7> FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
Y2 C9 GRP6
<7> FDI_TXN6 FDI1_TX#[2] PEG_RX[9]

Intel(R) FDI
<7> FDI_TXN7 AC9 F8 GRP5
FDI1_TX#[3] PEG_RX[10] C8 GRP4
PEG_RX[11] C5 GRP3
C U6 PEG_RX[12] H6 GRP2 C
<7> FDI_TXP0 FDI0_TX[0] PEG_RX[13]
W10 F6 GRP1
<7> FDI_TXP1 FDI0_TX[1] PEG_RX[14]
<7> FDI_TXP2 W3 K6 GRP0
AA7 FDI0_TX[2] PEG_RX[15]
<7> FDI_TXP3 FDI0_TX[3] GTN[0..15] <25>
<7> FDI_TXP4 W7 G22 GTN15C C154 EV@0.22u/10V_4 GTN15
T4 FDI1_TX[0] PEG_TX#[0] C23 GTN14C C152 EV@0.22u/10V_4 GTN14
<7> FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
AA3 D23 GTN13C C149 EV@0.22u/10V_4 GTN13
<7> FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
<7> FDI_TXP7 AC8 F21 GTN12C C148 EV@0.22u/10V_4 GTN12
FDI1_TX[3] PEG_TX#[3] H19 GTN11C C146 EV@0.22u/10V_4 GTN11
AA11 PEG_TX#[4] C17 GTN10C C143 EV@0.22u/10V_4 GTN10
<7> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
AC12 K15 GTN9C C142 EV@0.22u/10V_4 GTN9
<7> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17 GTN8C C140 EV@0.22u/10V_4 GTN8
U11 PEG_TX#[7] F14 GTN7C C137 EV@0.22u/10V_4 GTN7
<7> FDI_INT FDI_INT PEG_TX#[8] A15 GTN6C C136 EV@0.22u/10V_4 GTN6
AA10 PEG_TX#[9] J14 GTN5C C156 EV@0.22u/10V_4 GTN5
<7> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
AG8 H13 GTN4C C134 EV@0.22u/10V_4 GTN4
<7> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] M10 GTN3C C162 EV@0.22u/10V_4 GTN3
PEG_TX#[12] F10 GTN2C C132 EV@0.22u/10V_4 GTN2
PEG_TX#[13] D9 GTN1C C130 EV@0.22u/10V_4 GTN1
PEG_TX#[14] J4 GTN0C C128 EV@0.22u/10V_4 GTN0
AF3 PEG_TX#[15]
eDP_ICOMPO 12mil EDP_COMP AD2 eDP_COMPIO F22 GTP15C C153 EV@0.22u/10V_4 GTP15
GTP[0..15] <25>
eDP_COMPIO 4mil INT_EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23 GTP14C C151 EV@0.22u/10V_4 GTP14
eDP_HPD PEG_TX[1] D24 GTP13C C150 EV@0.22u/10V_4 GTP13
PEG_TX[2] E21 GTP12C C147 EV@0.22u/10V_4 GTP12
EDP_AUX# AG4 PEG_TX[3] G19 GTP11C C145 EV@0.22u/10V_4 GTP11
<15> EDP_AUX# AF4 eDP_AUX# PEG_TX[4] B18
EDP_AUX GTP10C C144 EV@0.22u/10V_4 GTP10
<15> EDP_AUX eDP_AUX PEG_TX[5] K17 GTP9C C141 EV@0.22u/10V_4 GTP9
PEG_TX[6]
DP

G17 GTP8C C139 EV@0.22u/10V_4 GTP8


EDP_TX0# AC3 PEG_TX[7] E14 GTP7C C138 EV@0.22u/10V_4 GTP7
B <15> EDP_TX0# eDP_TX#[0] PEG_TX[8] B
AC4 C15 GTP6C C135 EV@0.22u/10V_4 GTP6
AE11 eDP_TX#[1] PEG_TX[9] K13 GTP5C C155 EV@0.22u/10V_4 GTP5
AE7 eDP_TX#[2] PEG_TX[10] G13 GTP4C C133 EV@0.22u/10V_4 GTP4
eDP_TX#[3] PEG_TX[11] K10 GTP3C C161 EV@0.22u/10V_4 GTP3
EDP_TX0 AC1 PEG_TX[12] G10 GTP2C C131 EV@0.22u/10V_4 GTP2
<15> EDP_TX0 eDP_TX[0] PEG_TX[13]
AA4 D8 GTP1C C129 EV@0.22u/10V_4 GTP1
AE10 eDP_TX[1] PEG_TX[14] K4 GTP0C C127 EV@0.22u/10V_4 GTP0
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]

SNB_2CBGA_1P0 0.22uF AC coupling Caps for PCIE GEN1/2/3

DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
DP_COMPIO and ICOMPO signals PCIe Gen3 on future platforms.
should be shorted near balls and routed with For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
- typical impedance < 25 mohms

+1.05V_VTT
DP & PEG Compensation eDP Hot-plug (Disable)
20111104 change from 10k to 1k.
R192
+1.05V_VTT 1K_4

A INT_EDP_HPD# A
EDP_COMP R564 24.9/F_4
3

+1.05V_VTT 2 EDP_HPD
EDP_HPD <15>

Q2
Quanta Computer Inc.
PEG_COMP
CAD Note: Place PU resistor
R193 24.9/F_4 2N7002E R191
within 2 inches of CPU PROJECT : Z09
1

100K_4 Size Document Number Rev


3A
HPD PU/PD resistor values based Ivy Bridge 1/5
on CRB and different to DG Date: Monday, April 09, 2012 Sheet 2 of 40
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Boot S3 S3 RSM

+1.5V_CPU

DRAM_PWRGD
Ivy Bridge Processor (CLK,MISC,JTAG) 100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
U9B
D SM_DRAMPWROK D
J3 CLK_CPU_BCLKP <9>
BCLK H2 CLK_CPU_BCLKN <9>

CLOCKS
BCLK#

MISC
If motherboard only supports external graphics or if it supports
F49 TP95
20111121 Remove R5306/R5311/R5474/R5476. Processor Graphics but without eDP:
<8> H_SNB_IVB# PROC_SELECT# Connect DPLL_REF_SSCLK on Processor to GND through 1K +/-
AG3 CLK_DPLL_SSCLKP <9>
DPLL_REF_CLK AG1 5% resistor.
DPLL_REF_CLK# CLK_DPLL_SSCLKN <9> Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/
TP85 C57 TP53 - 5% resistor
PROC_DETECT#
N59 CLK_PCIE_XDPP_R R230 *0_4 CLK_PCIE_XDPP <9>
BCLK_ITP N58 CLK_PCIE_XDPN_R R229 *0_4
BCLK_ITP# CLK_PCIE_XDPN <9>

TP78 TP_CATERR# C49


CATERR#

THERMAL
Isolate Space:20mils
A48 AT30
<10,24> EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# <4,24>

BF44 SM_RCOMP_0 R209 140/F_4 CAD NOTE: All DDR_COMP signals


R207 56_4 H_PROCHOT#_R C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R206 25.5/F_4 should be routed such that :-
<24,33> H_PROCHOT#

DDR3
MISC
C253 PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2 R204 200/F_4 - max length = 500 mils
2 1 *43P/50V_4N SM_RCOMP[2] - trace width = 15mils and
- MB trace impedance < 68 mohms
(worst case resistance)
D45 Impedance 85ohm
<10> PM_THRMTRIP# THERMTRIP#

N53 TP79
PRDY# N55 XDP_PREQ#
PREQ# TP83
C C
L56 XDP_TCLK_VT <8,22> Place near to XDP connector
TCK L55
Over 130 degree C will TMS XDP_TMS_VT <8,22>

PWR MANAGEMENT
J58 XDP_TRST# TP103
drive low

JTAG & BPM


TRST# 51_4 R232 PCH_XDP_TDO_VT
+1.05V_VTT
<7> PM_SYNC R214 *SHORT_4 PM_SYNC_R C48 M60 XDP_TDI_VT <22>
PM_SYNC TDI L59
TDO PCH_XDP_TDO_VT <8>
C718 0.1U/10V_4
20111021 Add 10k to +3V,CRB 1k
R596 *SHORT_4 H_PWRGOOD_R B46 20111103 del R601
<10> H_PWRGOOD UNCOREPWRGOOD K58 XDP_DBRST#_R R233 0_4 XDP_DBRST# <7>
R595 10K_4 DBR#

PM_DRAM_PWRGD_R BE45 G58 Option for Prochot# function +1.05V_VTT


Isolate Space:20mils SM_DRAMPWROK BPM#[0] E55
TP97
BPM#[1] TP82 68 ohm for unused, 62 ohm for used
E59
BPM#[2] TP81
R194 75/F_4 G55 H_PROCHOT# R219 62_4
+1.05V_VTT TP67 BPM#[3] TP80
G59
BPM#[4] TP98
CPU_PLTRST# R190 43_4 CPU_PLTRST#_R D44 H60 TP100
RESET# BPM#[5] J59 XDP_TMS_VT R606 51_4
BPM#[6] TP99
J61 XDP_TDI_VT R231 51_4
BPM#[7] TP101
R196 XDP_PREQ# R612 *51_4

*750/F_4 XDP_TCLK_VT R611 51_4


XDP_TRST# R228 51_4

SNB_2CBGA_1P0 When MP, JTAG PU/PD resistor can be


B
removed? (Yes Intel, TDI, TDO, TMS, TRST#, B
TCK,PREQ#, PRDY#)

+3V

If PM_DRAM_PWEGD connector,the R5180 must stuff. C190


Thermal Trip <CPU> s3 leakage circuit U8 0.1U/10V_4X
20111128 change net to PCI_PLTRST# 1 5
+3V_S5 +3V_S5 NC VCC
20111121 add Q31 becaue Vh=2.1/Vl=0.9. 2
+1.05V_VTT <9,24> PCI_PLTRST# IN
3 4 CPU_PLTRST#
+1.5V_CPU GNDOUT
R604 R603 C727 74LVC1G07GW_NC
3

*1K_4 *10K_4 0.1u/10V_4

R186 *1.5K/F_4 CPU_PLTRST#_R


2 Q6 +1.5V_CPU R605
<7,33> IMVP_PWRGD
5

U33 200/F_4
2N7002_200MA 2
<7> SYS_PWROK
4 PM_DRAM_PWRGD_Q R598 130/F_4 PM_DRAM_PWRGD_R
IN OUT
1 L L
1

A A
5

74AHC1G09 H High-Z
3

R610 *39_4 3 1
R195
1K_4
*2N7002DW Q44 *2N7002K
Quanta Computer Inc.

2
Q42
4

1
2

Q5
<5,37> MAINON_G PROJECT : Z09
PM_THRMTRIP# 1 3 MMBT3904-7-F_200MA R602 0_4 Size Document Number Rev
SYS_SHDN# <32,37> <7> PM_DRAM_PWRGD
3A
20111030 add resistor. R608 *0_4
Ivy Bridge 2/5
Date: Monday, April 09, 2012 Sheet 3 of 40
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Sandy Bridge Processor (DDR3)


U9C U9D
<14> M_B_DQ[63:0]
<13> M_A_DQ[63:0] AG6 AL4
M_A_DQ0 M_B_DQ0
M_A_DQ1 AJ6 SA_DQ[0] AU36 M_B_DQ1 AL1 SB_DQ[0] BA34
M_A_DQ2 AP11 SA_DQ[1] SA_CLK[0] AV36 M_A_CLK0 <13> M_B_DQ2 AN3 SB_DQ[1] SB_CLK[0] AY34 M_B_CLK0 <14>
AL6 SA_DQ[2] SA_CLK#[0] AY26 M_A_CLK0# <13> AR4 SB_DQ[2] SB_CLK#[0] AR22 M_B_CLK0# <14>
M_A_DQ3 M_B_DQ3
AJ10 SA_DQ[3] SA_CKE[0] M_A_CKE0 <13> AK4 SB_DQ[3] SB_CKE[0] M_B_CKE0 <14>
M_A_DQ4 M_B_DQ4
M_A_DQ5 AJ8 SA_DQ[4] M_B_DQ5 AK3 SB_DQ[4]
D M_A_DQ6 AL8 SA_DQ[5] M_B_DQ6 AN4 SB_DQ[5] D
M_A_DQ7 AL7 SA_DQ[6] M_B_DQ7 AR1 SB_DQ[6]
M_A_DQ8 AR11 SA_DQ[7] M_B_DQ8 AU4 SB_DQ[7]
M_A_DQ9 AP6 SA_DQ[8] AT40 M_A_CLK1 M_B_DQ9 AT2 SB_DQ[8] BA36 M_B_CLK1
AU6 SA_DQ[9] SA_CLK[1] AU40 M_A_CLK1 <13> AV4 SB_DQ[9] SB_CLK[1] BB36
M_A_DQ10 M_A_CLK1# M_B_DQ10 M_B_CLK1#
AV9 SA_DQ[10] SA_CLK#[1] BB26 M_A_CLK1# <13> BA4 SB_DQ[10] SB_CLK#[1] BF27
M_A_DQ11 M_A_CKE1 M_B_DQ11 M_B_CKE1 TP31
M_A_DQ12 AR6 SA_DQ[11] SA_CKE[1] M_A_CKE1 <13> M_B_DQ12 AU3 SB_DQ[11] SB_CKE[1]
M_A_DQ13 AP8 SA_DQ[12] M_B_DQ13 AR3 SB_DQ[12]
M_A_DQ14 AT13 SA_DQ[13] M_B_DQ14 AY2 SB_DQ[13]
M_A_DQ15 AU13 SA_DQ[14] M_B_DQ15 BA3 SB_DQ[14]
M_A_DQ16 BC7 SA_DQ[15] M_B_DQ16 BE9 SB_DQ[15]
M_A_DQ17 BB7 SA_DQ[16] BB40 M_B_DQ17 BD9 SB_DQ[16] BE41
SA_DQ[17] SA_CS#[0] M_A_CS#0 <13> SB_DQ[17] SB_CS#[0] M_B_CS#0 <14>
M_A_DQ18 BA13 BC41 M_A_CS#1 M_B_DQ18 BD13 BE47 M_B_CS#1
SA_DQ[18] SA_CS#[1] M_A_CS#1 <13> SB_DQ[18] SB_CS#[1] TP32
M_A_DQ19 BB11 M_B_DQ19 BF12
M_A_DQ20 BA7 SA_DQ[19] M_B_DQ20 BF8 SB_DQ[19]
M_A_DQ21 BA9 SA_DQ[20] M_B_DQ21 BD10 SB_DQ[20]
M_A_DQ22 BB9 SA_DQ[21] M_B_DQ22 BD14 SB_DQ[21]
M_A_DQ23 AY13 SA_DQ[22] M_B_DQ23 BE13 SB_DQ[22]
M_A_DQ24 AV14 SA_DQ[23] AY40 M_B_DQ24 BF16 SB_DQ[23] AT43
SA_DQ[24] SA_ODT[0] M_A_ODT0 <13> SB_DQ[24] SB_ODT[0] M_B_ODT0 <14>
M_A_DQ25 AR14 BA41 M_A_ODT1 M_B_DQ25 BE17 BG47 M_B_ODT1
SA_DQ[25] SA_ODT[1] M_A_ODT1 <13> SB_DQ[25] SB_ODT[1] TP33
M_A_DQ26 AY17 M_B_DQ26 BE18
M_A_DQ27 AR19 SA_DQ[26] M_B_DQ27 BE21 SB_DQ[26]
M_A_DQ28 BA14 SA_DQ[27] M_B_DQ28 BE14 SB_DQ[27]
M_A_DQ29 AU14 SA_DQ[28] M_B_DQ29 BG14 SB_DQ[28]
M_A_DQ30 BB14 SA_DQ[29] M_B_DQ30 BG18 SB_DQ[29]
SA_DQ[30] M_A_DQSN[7:0] <13> SB_DQ[30] M_B_DQSN[7:0] <14>
M_A_DQ31 BB17 AL11 M_A_DQSN0 M_B_DQ31 BF19 AL3 M_B_DQSN0
M_A_DQ32 BA45 SA_DQ[31] SA_DQS#[0] AR8 M_A_DQSN1 M_B_DQ32 BD50 SB_DQ[31] SB_DQS#[0] AV3 M_B_DQSN1
M_A_DQ33 AR43 SA_DQ[32] SA_DQS#[1] AV11 M_A_DQSN2 M_B_DQ33 BF48 SB_DQ[32] SB_DQS#[1] BG11 M_B_DQSN2
M_A_DQ34 AW48 SA_DQ[33] SA_DQS#[2] AT17 M_A_DQSN3 M_B_DQ34 BD53 SB_DQ[33] SB_DQS#[2] BD17 M_B_DQSN3
M_A_DQ35 BC48 SA_DQ[34] SA_DQS#[3] AV45 M_A_DQSN4 M_B_DQ35 BF52 SB_DQ[34] SB_DQS#[3] BG51 M_B_DQSN4
DDR SYSTEM MEMORY A

SA_DQ[35] SA_DQS#[4] SB_DQ[35] SB_DQS#[4]

DDR SYSTEM MEMORY B


M_A_DQ36 BC45 AY51 M_A_DQSN5 M_B_DQ36 BD49 BA59 M_B_DQSN5
M_A_DQ37 AR45 SA_DQ[36] SA_DQS#[5] AT55 M_A_DQSN6 M_B_DQ37 BE49 SB_DQ[36] SB_DQS#[5] AT60 M_B_DQSN6
M_A_DQ38 AT48 SA_DQ[37] SA_DQS#[6] AK55 M_A_DQSN7 M_B_DQ38 BD54 SB_DQ[37] SB_DQS#[6] AK59 M_B_DQSN7
M_A_DQ39 AY48 SA_DQ[38] SA_DQS#[7] M_B_DQ39 BE53 SB_DQ[38] SB_DQS#[7]
C SA_DQ[39] SB_DQ[39] C
M_A_DQ40 BA49 M_B_DQ40 BF56
M_A_DQ41 AV49 SA_DQ[40] M_B_DQ41 BE57 SB_DQ[40]
M_A_DQ42 BB51 SA_DQ[41] M_B_DQ42 BC59 SB_DQ[41]
M_A_DQ43 AY53 SA_DQ[42] M_B_DQ43 AY60 SB_DQ[42]
M_A_DQ44 BB49 SA_DQ[43] M_B_DQ44 BE54 SB_DQ[43]
SA_DQ[44] M_A_DQSP[7:0] <13> SB_DQ[44]
M_A_DQ45 AU49 AJ11 M_A_DQSP0 M_B_DQ45 BG54
SA_DQ[45] SA_DQS[0] SB_DQ[45] M_B_DQSP[7:0] <14>
M_A_DQ46 BA53 AR10 M_A_DQSP1 M_B_DQ46 BA58 AM2 M_B_DQSP0
M_A_DQ47 BB55 SA_DQ[46] SA_DQS[1] AY11 M_A_DQSP2 M_B_DQ47 AW59 SB_DQ[46] SB_DQS[0] AV1 M_B_DQSP1
M_A_DQ48 BA55 SA_DQ[47] SA_DQS[2] AU17 M_A_DQSP3 M_B_DQ48 AW58 SB_DQ[47] SB_DQS[1] BE11 M_B_DQSP2
M_A_DQ49 AV56 SA_DQ[48] SA_DQS[3] AW45 M_A_DQSP4 M_B_DQ49 AU58 SB_DQ[48] SB_DQS[2] BD18 M_B_DQSP3
M_A_DQ50 AP50 SA_DQ[49] SA_DQS[4] AV51 M_A_DQSP5 M_B_DQ50 AN61 SB_DQ[49] SB_DQS[3] BE51 M_B_DQSP4
M_A_DQ51 AP53 SA_DQ[50] SA_DQS[5] AT56 M_A_DQSP6 M_B_DQ51 AN59 SB_DQ[50] SB_DQS[4] BA61 M_B_DQSP5
M_A_DQ52 AV54 SA_DQ[51] SA_DQS[6] AK54 M_A_DQSP7 M_B_DQ52 AU59 SB_DQ[51] SB_DQS[5] AR59 M_B_DQSP6
M_A_DQ53 AT54 SA_DQ[52] SA_DQS[7] M_B_DQ53 AU61 SB_DQ[52] SB_DQS[6] AK61 M_B_DQSP7
M_A_DQ54 AP56 SA_DQ[53] M_B_DQ54 AN58 SB_DQ[53] SB_DQS[7]
M_A_DQ55 AP52 SA_DQ[54] M_B_DQ55 AR58 SB_DQ[54]
M_A_DQ56 AN57 SA_DQ[55] M_B_DQ56 AK58 SB_DQ[55]
M_A_DQ57 AN53 SA_DQ[56] M_B_DQ57 AL58 SB_DQ[56]
M_A_DQ58 AG56 SA_DQ[57] M_B_DQ58 AG58 SB_DQ[57]
M_A_DQ59 AG53 SA_DQ[58] M_B_DQ59 AG59 SB_DQ[58]
M_A_DQ60 AN55 SA_DQ[59] M_B_DQ60 AM60 SB_DQ[59]
SA_DQ[60] M_A_A[15:0] <13> SB_DQ[60] M_B_A[15:0] <14>
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ61 AL59 BF32 M_B_A0
M_A_DQ62 AG55 SA_DQ[61] SA_MA[0] BB34 M_A_A1 M_B_DQ62 AF61 SB_DQ[61] SB_MA[0] BE33 M_B_A1
M_A_DQ63 AK56 SA_DQ[62] SA_MA[1] BE35 M_A_A2 M_B_DQ63 AH60 SB_DQ[62] SB_MA[1] BD33 M_B_A2
SA_DQ[63] SA_MA[2] BD35 M_A_A3 SB_DQ[63] SB_MA[2] AU30 M_B_A3
SA_MA[3] AT34 M_A_A4 SB_MA[3] BD30 M_B_A4
SA_MA[4] AU34 M_A_A5 SB_MA[4] AV30 M_B_A5
SA_MA[5] BB32 M_A_A6 SB_MA[5] BG30 M_B_A6
BD37 SA_MA[6] AT32 M_A_A7 BG39 SB_MA[6] BD29 M_B_A7
<13> M_A_BS#0 BF36 SA_BS[0] SA_MA[7] AY32 <14> M_B_BS#0 BD42 SB_BS[0] SB_MA[7] BE30
M_A_A8 M_B_A8
<13> M_A_BS#1 BA28 SA_BS[1] SA_MA[8] AV32 <14> M_B_BS#1 AT22 SB_BS[1] SB_MA[8] BE28
M_A_A9 M_B_A9
<13> M_A_BS#2 SA_BS[2] SA_MA[9] BE37 <14> M_B_BS#2 SB_BS[2] SB_MA[9] BD43
M_A_A10 M_B_A10
SA_MA[10] BA30 M_A_A11 SB_MA[10] AT28 M_B_A11
SA_MA[11] BC30 M_A_A12 SB_MA[11] AV28 M_B_A12
B B
BE39 SA_MA[12] AW41 M_A_A13 AV43 SB_MA[12] BD46 M_B_A13
<13> M_A_CAS# BD39 SA_CAS# SA_MA[13] AY28 <14> M_B_CAS# BF40 SB_CAS# SB_MA[13] AT26
M_A_A14 M_B_A14
<13> M_A_RAS# AT41 SA_RAS# SA_MA[14] AU26 <14> M_B_RAS# BD45 SB_RAS# SB_MA[14] AU22
M_A_A15 M_B_A15
<13> M_A_WE# SA_WE# SA_MA[15] <14> M_B_WE# SB_WE# SB_MA[15]

SNB_2CBGA_1P0 SNB_2CBGA_1P0 M_B_CLK1

R588
75/F_4

+0.75V_DDR_VTT
M_B_CLK1#

C758 C757 C756 C755 C753 C754 C759


1u/6.3V_41u/6.3V_4 1u/6.3V_41u/6.3V_41u/6.3V_4 1u/6.3V_4 10u/6.3V_8

20120112 for memory down PU CAP.

+3V_S5
+1.5VSUS 201201119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH,
s3 leakage circuit and EC_DRAMRST_CNTRL and R616. +0.75V_DDR_VTT
S3 circuit:- DRAM_RST# to memory should be high during S3
A R579 *0_4 M_B_A0 R550 36_4 A
R580 R358 M_B_A1 R555 36_4
1K/F_4 1K_4 M_B_A2 R554 36_4
M_B_A3 R531 36_4
Q38 2N7002K M_B_A4 R562 36_4
R577 1K/F_4 3 1 M_B_A5 R565 36_4 +0.75V_DDR_VTT
<13,14> DDR3_DRAMRST# CPU_DRAMRST# <3,24>
M_B_A6 R570 36_4
M_B_A7 R569 36_4 M_B_WE# R535 36_4
M_B_A8 R571 36_4 M_B_CAS# R539 36_4
Quanta Computer Inc.
2

<9> DRAMRST_CNTRL_PCH R573 *0_4 M_B_A9 R557 36_4 M_B_RAS# R542 36_4
M_B_A10 R537 36_4 M_B_BS#0 R534 36_4
R582 M_B_A11 R563 36_4 M_B_BS#2 R533 36_4
<24> EC_DRAMRST_CNTRL R574 0_4 C610 4.99K/F_4 M_B_A12 R549 36_4 M_B_CKE0 R540 36_4
PROJECT : Z09
0.047u/10V_4 M_B_A13 R567 36_4 M_B_ODT0 R541 36_4 Size Document Number Rev
M_B_A14 R568 36_4 M_B_CS#0 R538 36_4
<13,14> DEEPS3_EC M_B_A15 R536 36_4 M_B_BS#1 R532 36_4
Ivy Bridge 3/5 3A

20120204 Change to EC for new BIOS 0.6 Date: Monday, April 09, 2012 Sheet 4 of 40
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CPU VCCIO
Sandy Bridge Processor (POWER) IVY 17W:8.5A
CPU VCCAXG
Cose down IVY 17W:TDC 18A CPU VDDQ
U9F SNB : Spec Sandy Bridge Processor (GRAPHIC POWER) IVY 45W: 5A
330uF/6mohm x 2 330uF/6mohm x 1
Spec Cose down
+1.05V_VTT U9G
3.9mΩ/LoadlineDesign 3.9mΩ/LoadlineDesign Spec
10uF x 10 10uF x 10 total : 1uF x 11 total : 1uF x 11 +VCC_GFX
total : 10uF x 6 total : 10uF x 12 330uF/6mohm x 1
AF46 1uF x 26 1uF x 26
+VCC_CORE VCCIO[1]
VCCIO[3]
AG48 total : 22uF x 6 tatal : 470u x 1(power side*2) CAD Note: +VDDR_REF_CPU should 10uF x 8
AG50 AA46
20120120 remove C621 for debug IC. A26 VCCIO[4] AG51 tatal : 470u x 1(power side*2) AB47 VAXG[1] have 10 mil trace width
VCC[1] VCCIO[5] VAXG[2] 1uF x 10
A29 AJ17 C730 AB50
A31 VCC[2] VCCIO[6] AJ21 + AB51 VAXG[3] AY43
VCC[3] VCCIO[7] VAXG[4] SM_VREF +VDDR_REF_CPU
C235 C237 C238 A34 AJ25 + C603 + C215 AB52
A35 VCC[4] VCCIO[8] AJ43 *330u/2V_7343 330u/2V_7343 470u/2V_7343 AB53 VAXG[5]
D D
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 A38 VCC[5] VCCIO[9] AJ47 AB55 VAXG[6] +1.5V_CPU
A39 VCC[6] VCCIO[10] AK50 AB56 VAXG[7]
A42 VCC[7] VCCIO[11] AK51 AB58 VAXG[8]
C26 VCC[8] VCCIO[12] AL14 AB59 VAXG[9] AJ28
C27 VCC[9] VCCIO[13] AL15 AC61 VAXG[10] VDDQ[1] AJ33
C32 VCC[10] VCCIO[14] AL16 C729 C283 C282 C726 C281 C728 AD47 VAXG[11] VDDQ[2] AJ36
C697 C692 C693 C704 C34 VCC[11] VCCIO[15] AL20 AD48 VAXG[12] VDDQ[3] AJ40 C667 C662 C682 C681 C668
C37 VCC[12] VCCIO[16] AL22 C181 C639 C184 C652 C182 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AD50 VAXG[13] VDDQ[4] AL30 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 C39 VCC[13] VCCIO[17] AL26 AD51 VAXG[14] VDDQ[5] AL34

- 1.5V RAILS
C42 VCC[14] VCCIO[18] AL45 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AD52 VAXG[15] VDDQ[6] AL38
D27 VCC[15] VCCIO[19] AL48 AD53 VAXG[16] VDDQ[7] AL42
D32 VCC[16] VCCIO[20] AM16 AD55 VAXG[17] VDDQ[8] AM33
20120120 remove C622 for debug IC. D34 VCC[17] VCCIO[21] AM17 AD56 VAXG[18] VDDQ[9] AM36
D37 VCC[18] VCCIO[22] AM21 C278 C725 C285 C724 C284 C292 AD58 VAXG[19] VDDQ[10] AM40
C696 C236 C703 D39 VCC[19] VCCIO[23] AM43 AD59 VAXG[20] VDDQ[11] AN30 C242
D42 VCC[20] VCCIO[24] AM47 C656 C180 C604 C710 C183 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AE46 VAXG[21] VDDQ[12] AN34 C666 C691 C680 +
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 E26 VCC[21] VCCIO[25] AN20 N45 VAXG[22] VDDQ[13] AN38 10u/6.3V_6 *10u/6.3V_6 *10u/6.3V_6

POWER
E28 VCC[22] VCCIO[26] AN42 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 P47 VAXG[23] VDDQ[14] AR26 330u/2V_7343
E32 VCC[23] VCCIO[27] AN45 P48 VAXG[24] VDDQ[15] AR28
E34 VCC[24] VCCIO[28] AN48 P50 VAXG[25] VDDQ[16] AR30
E37 VCC[25] VCCIO[29] P51 VAXG[26] VDDQ[17] AR32
E38 VCC[26] C712 C708 C713 C701 C707 P52 VAXG[27] VDDQ[18] AR34

DDR3
VCC[27] VAXG[28] VDDQ[19]

CORE SUPPLY
F25 P53 AR36 C655 C665 C677 C664 C654
F26 VCC[28] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 P55 VAXG[29] VDDQ[20] AR40

PEG AND DDR


F28 VCC[29] C630 C620 C635 C624 C642 C611 C702 C626 C186 C709 C715 C716 C185 P56 VAXG[30] VDDQ[21] AV41 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
F32 VCC[30] P61 VAXG[31] VDDQ[22] AW26
F34 VCC[31] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 T48 VAXG[32] VDDQ[23] BA40
VCC[32] VAXG[33] VDDQ[24]

GRAPHICS
F37 AA14 T58 BB28
F38 VCC[33] VCCIO[30] AA15 T59 VAXG[34] VDDQ[25] BG33
F42 VCC[34] VCCIO[31] AB17 C711 C706 C714 C698 C700 C699 T61 VAXG[35] VDDQ[26]
G42 VCC[35] VCCIO[32] AB20 U46 VAXG[36] C676 C690 C689 C663 C675
H25 VCC[36] VCCIO[33] AC13 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 V47 VAXG[37]
H26 VCC[37] VCCIO[34] AD16 C619 C615 C633 C641 C623 C694 C616 C705 C605 C634 C612 C613 C614 V48 VAXG[38] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
C231 C240 C244 C629 C246 C653 C241 H28 VCC[38] VCCIO[35] AD18 V50 VAXG[39]
H29 VCC[39] VCCIO[36] AD21 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 V51 VAXG[40]
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 H32 VCC[40] VCCIO[37] AE14 V52 VAXG[41]
H34 VCC[41] VCCIO[38] AE15 V53 VAXG[42]
C C
H35 VCC[42] VCCIO[39] AF16 V55 VAXG[43]
H37 VCC[43] VCCIO[40] AF18 V56 VAXG[44]
H38 VCC[44] VCCIO[41] AF20 V58 VAXG[45]
H40 VCC[45] VCCIO[42] AG15 V59 VAXG[46]
VCC[46] VCCIO[43] IVY SPEC VAXG[47]
C669 C683 C658 C684 C670 C657 C645 J25 AG16 22uF_8 x7 Socket TOP cavity W50
J26 VCC[47] VCCIO[44] AG17 W51 VAXG[48]
J28 VCC[48] VCCIO[45] AG20
22uF_8 x5 Socket BOT cavity W52 VAXG[49]
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4
J29 VCC[49] VCCIO[46] AG21 22uF_8 x2 Socket TOP cavity (no stuff) W53 VAXG[50]
J32 VCC[50] VCCIO[47] AJ14 22uF_8 x5 Socket BOT cavity (no stuff) W55 VAXG[51]
VCC[51] VCCIO[48] 330uF_7343 x2 VAXG[52]

POWER
J34 AJ15 W56
J35 VCC[52] VCCIO[49] W61 VAXG[53]
J37 VCC[53] Y48 VAXG[54]
C251 C646 C628 C232 C678 C250 C239 J38 VCC[54] Y61 VAXG[55]
VCC[55] VCCAXG_SENSE/VSSAXG_SENSE R=100, VAXG[56]
J40
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 J42 VCC[56] Trace impedance 15.5~34.5, <25mils.
K26 VCC[57] W16 R187 *SHORT_6
VCC[58] VCCIO50 +1.05V_VTT
K27 W17
VCC[59] VCCIO51 TP69
K29

QUIET RAILS
K32 VCC[60] R593 100_4 AM28
VCC[61] Voltage selection for VCCIO: +VCC_GFX VCCDQ[1] +1.5V_CPU

LINES
SENSE
K34 F45 AN26
C671 C685 C687 C695 C686 C659 C647 K35 VCC[62] this pin must be pulled high CPU VCCPL <33> VCC_AXG_SENSE
G45 VAXG_SENSE VCCDQ[2] C650 1U/6.3V_4X
VCC[63] <33> VSS_AXG_SENSE VSSAXG_SENSE
K37 IVY 17W:1.5A R594 100_4
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 K39 VCC[64] on the motherboard
VCC[66] TP70
K42 BC22 VCCIO_SEL
L25 VCC[67] VCCIO_SEL TP64
On CRB Spec Real
VCC[68]

1.8V RAIL
L28 H_SNB_IVB#_PWRCTRL = low, 1.0V 330uF/7mohm x 1 10uF x 1 R566 *SHORT_8
VCC[69] +1.8V
L33 H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
L36 VCC[70] R560 *SHORT_8 CPU_VCCPLL BB3
VCC[71] 1uF x 2 1uF x 2 VCCPLL[1]
C673 C672 C245 C648 C649 C660 C661 L40 BC1
QUIET RAILS

N26 VCC[72] +1.05V_VTT C200 C192 + C177 BC4 VCCPLL[2]


2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 N30 VCC[73] AM25 R581 *SHORT_4 1u/6.3V_4 1u/6.3V_4 VCCPLL[3]
N34 VCC[74] VCCPQE[1] AN22 *330u/2V_7343
VCC[75] VCCPQE[2] IVY SPEC
N38 C632 1U/6.3V_4X 330uF x1, 10uF_8 x1, 1uF_4 x2
VCC[76] BC43 R590 *51_4
CPU Core Power Socket BOT edge. +VCCSA VDDQ_SENSE BA43 R592 *51_4
+1.5V_CPU

SENSE LINES
VSS_SENSE_VDDQ
IVY 17W:TDC 33A L17
B B
L21 VCCSA[1]
IVY SPEC VCCSA[2]
N16
1.9mΩ/LoadlineDesign A44 H_CPU_SVIDALRT# N20 VCCSA[3]
total : 2.2uF x 35 VIDALERT# VCCSA[4]

SA RAIL
C674 C247 B43 H_CPU_SVIDCLK C627 C618 N22
SVID

VIDSCLK C44 P17 VCCSA[5]


total : 22uF x 12 + +
VIDSOUT
H_CPU_SVIDDAT IVY SPEC C609 C636 C651 + C178
VCCSA[6]
R575 *100/F_4 +VCCSA
330uF x1, 10uF_8 x1 Socket BOT edge, 10u/6.3V_6 10u/6.3V_610u/6.3V_6 10u/6.3V_6 10u/6.3V_6 330u/2V_7343 P20 U10
tatal : 470u x3(Power side*1) 470u/2V_7343 470u/2V_7343 R16 VCCSA[7] VCCSA_SENSE VCCSA_SENSE <36>
10uF_8 x2 Socket BOT cavity. VCCSA[8] SNB_IVB# N.A at SNB EDS #27637 0.7v1
R18
R21 VCCSA[9] R217 *10K_4
Cose down CPU VCCSA U15 VCCSA[10] 201201117 C767 for Intel fw issue, if solve need un-stuff.
V16 VCCSA[11] C767 *33n/10V_4
IVY SPEC IVY 17W: 6A VCCSA[12]
V17 D48 R220 IVB@0_4
1.9mΩ/LoadlineDesign Spec V18 VCCSA[13] VCCSA_VID[0] D49
VCCSA_VID0 <36>
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 <36>
total : 2.2uF x 35 R591 100_4 330uF/7mohm x 1 V21
total : 10uF x 12 F43
+VCC_CORE
VCC_SENSE <33> 10uF x 5
Real C608 C617 C631 C637 C625 W20 VCCSA[15] R597 *10K_4
SENSE LINES

VCC_SENSE G43 VCCSA[16] A 1-K pull-down resistor should be placed on the


tatal : 470u x1(Power side*1) VSS_SENSE VSS_SENSE <33> 1uF x 5 10uF x 3 VCCSA VID lines. This will ensure the VID
R589 100_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
is 00 prior to VCCIO stability..
R94 for SN Bridge
R576 10_4 +1.05V_VTT
AN16 SNB_2CBGA_1P0
VCCIO_SENSE VCCP_SENSE <34>
AN17 For SN Bridge
VSS_SENSE_VCCIO VSSP_SENSE <34>
R578 10_4
S3 STUFF NO_STUFF 20111107 stuff Q5010 and un-staff R5347/R362. VID[1] +VCCSA
4.5A
+1.5VSUS R210 *0_1206 +1.5V_CPU 0 0.9V
enable - R5347/R6362
SNB_2CBGA_1P0 1 0.8V
disable - R211 *0_1206
R5347/R6362
Q41 AO4496 For IV Bridge
8 1
+SMDDR_VREF +VDDR_REF_CPU +1.5V_CPU 7 2 VID[0] VID[1] +VCCSA
6 3
20111024 from +1.5VSUS change to +1.5V_CPU 5 0 0 0.9V
A R234 *0_8 R221 0 1 0.8V A

4
*1K/F_4
Layout note: need routing 1 0 0.725V
MAIND
together and ALERT need Place PU resistor close to CPU 3 1 R583 1 1 0.675V
Place PU resistor close to CPU C688 220_8
between CLK and DATA +1.05V_VTT +1.05V_VTT Q7 470P/50V_4
2N7002K

3
MAIND R218
SVID DATA <32,35,37> MAIND
100K_4 R215
SVID ALERT
SVID CLK R202 R213
*1K/F_4
MAINON_G 2 Quanta Computer Inc.
<3,37> MAINON_G
130/F_4 75/F_4 S3 circuit: 1.5V input to IVB is gated &
H_CPU_SVIDCLK R203 *SHORT_4 Q39
VR_SVID_CLK <33>
H_CPU_SVIDDAT R205 *SHORT_4 VR_SVID_DATA <33> H_CPU_SVIDALRT# R208 43_4 VR_SVID_ALERT#_R R212 *SHORT_4 VR_SVID_ALERT# <33>
IVB Read Vref 0.75V is gated change to 1K/F_4 DMN601K-7 PROJECT : Z09
Size Document Number Rev

1
3A
Ivy Bridge 4/5
Date: Monday, April 09, 2012 Sheet 5 of 40
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Sandy Bridge Processor (GND) Sandy Bridge Processor (RESERVED, CFG)


U9H U9I BE7 SA_DIMM_VREFDQ
U9E BG7 SB_DIMM_VREFDQ
R572 *1K_4
BG17 M4
A13 AM38 BG21 VSS[181] VSS[251] M58 B50 BE7
VSS[1] VSS[91] VSS[182] VSS[252] TP76 CFG[0] RSVD28 SMDDR_VREF_DQ0_M3 <13>
D A17 AM4 BG24 M6 CFG1 C51 BG7 D
VSS[2] VSS[92] VSS[183] VSS[253] TP96 CFG[1] RSVD29 SMDDR_VREF_DQ1_M3 <14>
A21 AM42 BG28 N1 CFG2 B54
A25 VSS[3] VSS[93] AM45 BG37 VSS[184] VSS[254] N17 CFG3 D53 CFG[2] R197 *1K_4
A28 VSS[4] VSS[94] AM48 BG41 VSS[185] VSS[255] N21 CFG4 A51 CFG[3] N42
A33 VSS[5] VSS[95] AM58 BG45 VSS[186] VSS[256] N25 CFG5 C53 CFG[4] RSVD30 L42 processor signal balls BF3 and BG4 for
A37 VSS[6] VSS[96] AN1 BG49 VSS[187] VSS[257] N28 CFG6 C55 CFG[5] RSVD31 L45 Ivy Bridge 4-core and balls BE7
A40 VSS[7] VSS[97] AN21 BG53 VSS[188] VSS[258] N33 CFG7 H49 CFG[6] RSVD32 L47 and BG7 for Ivy Bridge 2-core
A45 VSS[8] VSS[98] AN25 BG9 VSS[189] VSS[259] N36 A55 CFG[7] RSVD33
A49 VSS[9] VSS[99] AN28 C29 VSS[190] VSS[260] N40 H51 CFG[8]
A53 VSS[10] VSS[100] AN33 C35 VSS[191] VSS[261] N43 K49 CFG[9] M13
A9 VSS[11] VSS[101] AN36 C40 VSS[192] VSS[262] N47 K53 CFG[10] RSVD34 M14
AA1 VSS[12] VSS[102] AN40 D10 VSS[193] VSS[263] N48 F53 CFG[11] RSVD35 U14
AA13 VSS[13] VSS[103] AN43 D14 VSS[194] VSS[264] N51 G53 CFG[12] RSVD36 W14
VSS[14] VSS[104] VSS[195] VSS[265] CFG[13] RSVD37 for M3 solution
AA50 AN47 D18 N52 L51 P13
AA51 VSS[15] VSS[105] AN50 D22 VSS[196] VSS[266] N56 F51 CFG[14] RSVD38 need R5265/R5266,
AA52 VSS[16] VSS[106] AN54 D26 VSS[197] VSS[267] N61 D52 CFG[15] W/O M3 then NC
AA53 VSS[17] VSS[107] AP10 D29 VSS[198] VSS[268] P14 L53 CFG[16] AT49
AA55 VSS[18] VSS[108] AP51 D35 VSS[199] VSS[269] P16 CFG[17] RSVD39 K24
AA56 VSS[19] VSS[109] AP55 D4 VSS[200] VSS[270] P18 RSVD40

RESERVED
AA8 VSS[20] VSS[110] AP7 D40 VSS[201] VSS[271] P21 H43
VSS[21] VSS[111] VSS[202] VSS[272] TP65 VCC_VAL_SENSE
AB16 AR13 D43 P58 K43 AH2
AB18
AB21
VSS[22]
VSS[23]
VSS[24]
VSS[112]
VSS[113]
VSS[114]
AR17
AR21
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[273]
VSS[274]
VSS[275]
P59
P9
TP68 VSS_VAL_SENSE RSVD41
RSVD42
RSVD43
AG13
AM14
AB48 AR41 D54 R17 TP66
H45 AM15
AB61 VSS[25] VSS[115] AR48 D58 VSS[206] VSS[276] R20 K45 VAXG_VAL_SENSE RSVD44
VSS[26] VSS[116] VSS[207] VSS[277] TP72 VSSAXG_VAL_SENSE
AC10 AR61 D6 R4
AC14 VSS[27] VSS[117] AR7 E25 VSS[208] VSS[278] R46 N50
AC46 VSS[28] VSS[118] AT14 E29 VSS[209] VSS[279] T1 F48 RSVD45
VSS[29] VSS[119] VSS[210] VSS[280] TP74 VCC_DIE_SENSE
AC6 AT19 E3 T47
C AD17 VSS[30] VSS[120] AT36 E35 VSS[211] VSS[281] T50 C
AD20 VSS[31] VSS[121] AT4 E40 VSS[212] VSS[282] T51 H48
VSS[32] VSS[122] VSS[213] VSS[283] TP71 RSVD6
AD4 AT45 F13 T52 K48
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F15
F19
VSS[214]
VSS[215]
VSS[216]
VSS[284]
VSS[285]
VSS[286]
T53
T55
TP73 RSVD7
DC_TEST_A4
DC_TEST_C4
A4
C4
AE8 AU1 F29 T56 BA19 D3
AF1 VSS[36] VSS[126] AU11 F35 VSS[217] VSS[287] U13 AV19 RSVD8 DC_TEST_D3 D1
AF17 VSS[37] VSS[127] AU28 F40 VSS[218] VSS[288] U8 AT21 RSVD9 DC_TEST_D1 A58
AF21 VSS[38] VSS[128] AU32 F55 VSS[219] VSS[289] V20 BB21 RSVD10 DC_TEST_A58 A59
AF47 VSS[39] VSS[129] AU51 G48 VSS[220] VSS[290] V61 BB19 RSVD11 DC_TEST_A59 C59
AF48 VSS[40] VSS[130] AU7 G51 VSS[221] VSS[291] W13 AY21 RSVD12 DC_TEST_C59 A61
AF50 VSS[41] VSS[131] AV17 R599 G6 VSS[222] VSS[292] W15 BA22 RSVD13 DC_TEST_A61 C61
AF51 VSS[42] VSS[132] AV21 *SNB@0_4 G61 VSS[223] VSS[293] W18 AY22 RSVD14 DC_TEST_C61 D61
AF52 VSS[43] VSS[133] AV22 H10 VSS[224] VSS[294] W21 AU19 RSVD15 DC_TEST_D61 BD61
AF53 VSS[44] VSS[134] AV34 H14 VSS[225] VSS[295] W46 AU21 RSVD16 DC_TEST_BD61 BE61
AF55 VSS[45] VSS[135] AV40 H17 VSS[226] VSS[296] W8 BD21 RSVD17 DC_TEST_BE61 BE59
AF56 VSS[46] VSS[136] AV48 H21 VSS[227] VSS[297] Y4 BD22 RSVD18 DC_TEST_BE59 BG61
AF58 VSS[47] VSS[137] AV55 H4 VSS[228] VSS[298] Y47 BD25 RSVD19 DC_TEST_BG61 BG59
AF59 VSS[48] VSS[138] AW13 H53 VSS[229] VSS[299] Y58 BD26 RSVD20 DC_TEST_BG59 BG58
AG10 VSS[49] VSS[139] AW43 H58 VSS[230] VSS[300] Y59 BG22 RSVD21 DC_TEST_BG58 BG4
AG14 VSS[50] VSS[140] AW61 J1 VSS[231] VSS[301] BE22 RSVD22 DC_TEST_BG4 BG3
AG18 VSS[51] VSS[141] AW7 J49 VSS[232] BG26 RSVD23 DC_TEST_BG3 BE3
AG47 VSS[52] VSS[142] AY14 J55 VSS[233] BE26 RSVD24 DC_TEST_BE3 BG1
AG52 VSS[53] VSS[143] AY19 K11 VSS[234] BF23 RSVD25 DC_TEST_BG1 BE1
AG61 VSS[54] VSS[144] AY30 K21 VSS[235] BE24 RSVD26 DC_TEST_BE1 BD1
AG7 VSS[55] VSS[145] AY36 K51 VSS[236] A5 RSVD27 DC_TEST_BD1
AH4 VSS[56] VSS[146] AY4 K8 VSS[237] VSS_NCTF_1 A57
AH58 VSS[57] VSS[147] AY41 L16 VSS[238] VSS_NCTF_2 BC61
AJ13 VSS[58] VSS[148] AY45 L20 VSS[239] VSS_NCTF_3 BD3
B AJ16 VSS[59] VSS[149] AY49 L22 VSS[240] VSS_NCTF_4 BD59 SNB_2CBGA_1P0 B
VSS[60] VSS[150] VSS[241] VSS_NCTF_5
NCTF

AJ20 AY55 L26 BE4


AJ22 VSS[61] VSS[151] AY58 L30 VSS[242] VSS_NCTF_6 BE58
AJ26 VSS[62] VSS[152] AY9 L34 VSS[243] VSS_NCTF_7 BG5
AJ30 VSS[63] VSS[153] BA1 L38 VSS[244] VSS_NCTF_8 BG57 CFG5 R225 *1K/F_4
AJ34 VSS[64] VSS[154] BA11 L43 VSS[245] VSS_NCTF_9 C3 CFG6 R227 *1K/F_4
AJ38 VSS[65] VSS[155] BA17 L48 VSS[246] VSS_NCTF_10 C58
AJ42 VSS[66] VSS[156] BA21 L61 VSS[247] VSS_NCTF_11 D59
AJ45 VSS[67] VSS[157] BA26 M11 VSS[248] VSS_NCTF_12 E1
AJ48 VSS[68] VSS[158] BA32 M15 VSS[249] VSS_NCTF_13 E61
CFG[6:5] (PCIE Port Bifurcation Straps)
AJ7 VSS[69] VSS[159] BA48 VSS[250] VSS_NCTF_14
VSS[70] VSS[160]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AK1 BA51 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
AK52 VSS[71] VSS[161] BB53
AL10 VSS[72] VSS[162] BC13
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
AL13 VSS[73] VSS[163] BC5 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AL17 VSS[74] VSS[164] BC57 SNB_2CBGA_1P0
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19
AL33 VSS[78] VSS[168] BD23
AL36 VSS[79]
VSS[80]
VSS[169]
VSS[170]
BD27 Processor Strapping The CFG signals have a default value of '1' if not terminated on the board. CFG2 R226 1K/F_4
AL40 BD32
AL43 VSS[81] VSS[171] BD36 20111102 stuff for revers
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
1 0
AM13 VSS[84] VSS[174] BD48 CFG3 R224 *1K/F_4
AM20 VSS[85] VSS[175] BD52
CFG2
AM22 VSS[86] VSS[176] BD56 (PCI-E Static x16 Lane Reversal) Normal Operation Lane Reversed CFG4 R223 1K/F_4
AM26 VSS[87] VSS[177] BD8
A VSS[88] VSS[178] A
AM30 BE5 CFG3 CFG7 R222 *1K/F_4
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180] (PCI-E Static x4 Lane Reversal) Normal Operation Lane Reversed

CFG4
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
SNB_2CBGA_1P0
(DP Presence Strap) Quanta Computer Inc.
CFG7
PROJECT : Z09
PEG train immediately following PEG wait for BIOS training Size Document Number Rev
(PEG Defer Training)
xxRESETB de assertion Ivy Bridge 5/5 3A

Date: Monday, April 09, 2012 Sheet 6 of 40


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CPT/PPT (LVDS,DDI)
U26D
07
CPT/PPT (DMI,FDI,PM) <15> INT_LVDS_BLON
J47
M45 L_BKLTEN SDVO_TVCLKINN
AP43
AP45
<15> INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
U26C Need notice BIOS if DMI or FDI reverse. P45 AM42
<15> INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN AM40
D BC24 BJ14 T40 SDVO_STALLP D
<2> DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 <2> L_DDC_CLK
BE20 AY14 K47 AP39
<2> DMI_RXN1 DMI1RXN FDI_RXN1 FDI_TXN1 <2> L_DDC_DATA SDVO_INTN
BG18 BE14 AP40
<2> DMI_RXN2 DMI2RXN FDI_RXN2 FDI_TXN2 <2> SDVO_INTP
BG20 BH13 T45
<2> DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 <2> L_CTRL_CLK
BC12 P39
BE24 FDI_RXN4 BJ12 FDI_TXN4 <2> L_CTRL_DATA
<2> DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 <2>
BC20 BG10 AF37 P38
<2> DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 <2> LVD_IBG SDVO_CTRLCLK HDMI_DDCCLK_SW <16>
BJ18 BG9 AF36 M39
<2> DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 <2> LVD_VBG SDVO_CTRLDATA HDMI_DDCDATA_SW <16>
BJ20
<2> DMI_RXP3 DMI3RXP BG14 AE48
FDI_RXP0 FDI_TXP0 <2> LVD_VREFH

INT. HDMI
AW24 BB14 AE47 AT49
<2> DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 <2> LVD_VREFL DDPB_AUXN
AW20 BF14 AT47
<2> DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 <2> DDPB_AUXP
BB18 BG13 AT40
<2> DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 <2> DDPB_HPD HDMI_HP <16>
AV18 BE12 AK39

DMI
FDI
<2> DMI_TXN3

LVDS
DMI3TXN FDI_RXP4 BG12 FDI_TXP4 <2> AK40 LVDSA_CLK# AV42 INT_HDMITX2N_C
AY24 FDI_RXP5 BJ10 FDI_TXP5 <2> LVDSA_CLK DDPB_0N AV40 INT_HDMITX2N_C <16>
<2> DMI_TXP0 INT_HDMITX2P_C
AY20 DMI0TXP FDI_RXP6 BH9 FDI_TXP6 <2> AN48 DDPB_0P AV45 INT_HDMITX2P_C <16>
<2> DMI_TXP1 INT_HDMITX1N_C
AY18 DMI1TXP FDI_RXP7 FDI_TXP7 <2> AM47 LVDSA_DATA#0 DDPB_1N AV46 INT_HDMITX1N_C <16>
INT_HDMITX1P_C

Digital Display Interface


<2> DMI_TXP2 DMI2TXP LVDSA_DATA#1 DDPB_1P INT_HDMITX1P_C <16>
AU18 20111102 FDI reverse AK47 AU48 INT_HDMITX0N_C
<2> DMI_TXP3 DMI3TXP LVDSA_DATA#2 DDPB_2N INT_HDMITX0N_C <16>
AW16 20111111 FDI change to normal AJ48 AU47 INT_HDMITX0P_C
FDI_INT FDI_INT <2> LVDSA_DATA#3 DDPB_2P AV47 INT_HDMITX0P_C <16>
20111102 DMI reverse INT_HDMICLK-_C
BJ24 AV12 AN47 DDPB_3N AV49 INT_HDMICLK-_C <16>
20111111 DMI change to normal INT_HDMICLK+_C
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <2> AM49 LVDSA_DATA0 DDPB_3P INT_HDMICLK+_C <16>
R505 49.9/F_4 DMI_COMP BG25 BC10 AK49 LVDSA_DATA1
+1.05V_VTT DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <2> LVDSA_DATA2
AJ47 P46
R502 750/F_4 BH21 AV14 LVDSA_DATA3 DDPC_CTRLCLK P42
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <2> DDPC_CTRLDATA

DisplayPort C
BB10 AF40
FDI_LSYNC1 FDI_LSYNC1 <2> AF39 LVDSB_CLK# AP47
C
LVDSB_CLK DDPC_AUXN AP49 C
20110214 add SUSWAEN to SUSACK connector. DPWROK need to be AH45 DDPC_AUXP AT38
A18 shorted to RSMRST# when Deep S4/S5 state is not support AH47 LVDSB_DATA#0 DDPC_HPD
DSWVRMEN DSWVREN <8> LVDSB_DATA#1
SUSWARN#_R R642 0_4 AF49 AY47
LVDSB_DATA#2 DDPC_0N

System Power Management


AF45 AY49
R91 *0_4 SUSACK#_R C12 E22 DPWROK_R R94 0_4 20120104 change DPWROK from PCH_Rsmrst# to EC control. LVDSB_DATA#3 DDPC_0P AY43
<24> SUSACK# SUSACK# DPWROK DPWROK <24> DDPC_1N
AH43 AY45
XDP_DBRST# AH49 LVDSB_DATA0 DDPC_1P BA47
<3> XDP_DBRST# LVDSB_DATA1 DDPC_2N
K3 B9 PCIE_WAKE#_LAN R397 0_4 AF47 BA48
SYS_RESET# WAKE# PCIE_LAN_WAKE# <17> LVDSB_DATA2 DDPC_2P
C431 *1U/10V_4 AF43 BB47
20111206 add R5193 un-stuff for normal s3 PCIE LAN wake up. LVDSB_DATA3 DDPC_3N BB49
SYS_PWROK R405 *SHORT_4 SYS_PWROK_R P12 N3 CLKRUN# DDPC_3P
SYS_PWROK +3V CLKRUN# / GPIO32 CLKRUN# <19,24>
N48 M43
R382 *0_4 EC_PWROK_R L22 G8 P49 CRT_BLUE DDPD_CTRLCLK M36
PWROK +3V_S5 SUS_STAT# / GPIO61 LPCPD# <19> CRT_GREEN DDPD_CTRLDATA

DisplayPort D
R403 *SHORT_4 T49
CRT_RED
PWROK_EC R414 *SHORT_4 APWROK_R L10 +3V_S5 N14 PCH_SUSCLK 20111123 add for TPM LPCPD# pin. AT45

CRT
APWROK SUSCLK / GPIO62 TP36 DDPD_AUXN
R404 *SHORT_4 T39 AT43
M40 CRT_DDC_CLK DDPD_AUXP BH41
PM_DRAM_PWRGD B13 D10 CRT_DDC_DATA DDPD_HPD
<3> PM_DRAM_PWRGD DRAMPWROK +3V_S5 SLP_S5# / GPIO63 TP35
BB43
M47 DDPD_0N BB45
PCH_RSMRST# C21 H4 M49 CRT_HSYNC DDPD_0P BF44
<24> PCH_RSMRST# RSMRST# SLP_S4# SUSC# <24> CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
R635 *0_4 SUSWARN#_R K16 F4 DAC_IREF T43 DDPD_2N BE42
<20,24> IOAC_PCIERST# SUSWARN#/SUSPWRDNACK/GPIO30 +3V_S5
SLP_S3# SUSB# <24> DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N BG42
R69 *SHORT_4 E20 G10 SLP_A# R120 DDPD_3P
B <24> DNBSWON# PWRBTN# SLP_A# TP37 B
PM_PWRBTN# 1K/F_4 Panther Point_R1P0
TP40
ACPRESENT H20 DSW G16 SLP_SUS#
<31> ACPRESENT ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# <11,24>
1% or 5%

PM_BATLOW# E10 AP14


BATLOW# / GPIO72 +3V_S5 PMSYNCH PM_SYNC <3>

PM_RI# A10 +3V_S5 K14 SLP_LAN#


RI# SLP_LAN# / GPIO29

Panther Point_R1P0

PCH Pull-high/low(CLG) System PWR_OK(CLG) IMVP_PWRGD PU +3V


+3V_S5
CRB 1.0 change R5196 to 1K PWROK_EC PD
+3V_S5
CRB 1.0 uses 1k +3V_S5
so AND gate output dont need PD again
+3V

CLKRUN# R429 8.2K_4 PM_RI# R359 10K_4 C434


C426 *0.1U/10V_4
XDP_DBRST# R433 4.99K/F_4 PM_BATLOW# R363 8.2K_4 0.1u/10V_4

5
R432 *1K_4 PCIE_WAKE#_LAN R398 10K_4 U25
5

to PCH Pin12, XDP and EE debug U24 2


2 4 IMVP_PWRGD <3,33>
PCH_RSMRST# R76 10K_4 SLP_LAN# R84 *10K_4 IMVP_PWRGD_R
A SYS_PWROK 4 1 A
<3> SYS_PWROK GFX_PWRGD <24,33>
SUSWARN#_R R62 10K_4 1 PWROK_EC
PWROK_EC <24>
*TC7SH08

3
SYS_PWROK R352 *10K_4 ACPRESENT R346 *10K_4 TC7SH08FU
3

201201119 stuff R346. R411


100K_4

PM_DRAM_PWRGD R396 200/F_4 Quanta Computer Inc.


wo S3 leakage, un-stuff R5180 R409 0_4
20111107 R5180 un-stuff. PROJECT : Z09
20111128 add 0ohm to passed IMVP_PERGD Size Document Number Rev
R406 *0_4 3A
include GFX_PWRGD to SYS_PWROK for PCH check
Panther Point 1/6
Date: Monday, April 09, 2012 Sheet 7 of 40
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RTC Circuitry(RTC) +3V_RTC PCH2(CLG)


20mils
R35 20K_4 RTC_RST#

CPT/PPT (HDA,JTAG,SATA) 08

1
J2
C31
D14 1u/6.3V_4 C424 18p/50V_4

1
R545 *SHORT_6 30mils *SHORT_ PAD1
+3VPCU

2
VCCRTC_1 U26A
R48 20K_4 SRTC_RST# Y4 R408
20MIL BAT54C 32.768KHZ 10M_4 RTC_X1 A20 C38
RTCX1 FWH0 / LAD0 LPC_LAD0 <19,20,24>

1
J1 A38

LPC
FWH1 / LAD1 LPC_LAD1 <19,20,24>
R530 C38 C36 C425 18p/50V_4 RTC_X2 C20 B37
LPC_LAD2 <19,20,24>

2
1K_4 1u/6.3V_4 1u/6.3V_4 RTCX2 FWH2 / LAD2 C37
FWH3 / LAD3 LPC_LAD3 <19,20,24>
*SHORT_ PAD1 RTC_RST# D20

2
RTCRST# D36
D FWH4 / LFRAME# LPC_LFRAME# <19,20,24> D
SRTC_RST# G22 CRB 1.0 uses 10kohm
+5V_S5 SRTCRST# E36 PCH_DRQ#0
20MIL 20MIL TP5

RTC
R68 1M_4 SM_INTRUDER# K22 LDRQ0# K36 PCH_DRQ#1
20110530-modify +3V_RTC INTRUDER# +3V LDRQ1# / GPIO23 TP11
VCCRTC_2 1 3VCCRTC_3 R519 4.7K_4 VCCRTC_4 R518 4.7K_4
PCH_INVRMEN C17 V5
Q33 R517 Add MOSFET to separate CODEC SYNC signal INTVRMEN SERIRQ R135 8.2K_4
SERIRQ <19,24>
+3V
MMBT3904 20120109 change footprint. R349 *SHORT_4
+5V
2
1

68.1K/F_4 ZRH use 2N7002D AM3 SATA_RXN0 <21>


SATA0RXN

2
ACZ_BITCLK_R N34 AM1 SATA_RXP0 <21>
HDA_BCLK SATA0RXP

SATA 6G
AP7 SATA HDD
SATA0TXN SATA_TXN0 <21>
BT1 ACZ_SYNC_CODEC 1 3 ACZ_SYNC_R L34 AP5 SATA_TXP0 <21>
RTC SOCKET HDA_SYNC SATA0TXP 20110908 acer request HDD,MSATA need SATA3.
R529 Q21 SPKR T10 AM10 SATA_RXN1 <20>
<19> SPKR SPKR SATA1RXN
20MIL CRB 1.0 2N7002K AM8
SATA_RXP1 <20>
2

150K/F_4 R348 ACZ_RST#_R K34 SATA1RXP AP11


HDA_RST# SATA1TXN SATA_TXN1 <20> mSATA
20111117 change back RTC connect 1M_4 AP10 SATA_TXP1 <20>
20111118 change RTC connect to 2P. SATA1TXP
20111121 change back RTC connector to socket. E34 AD7
<19> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
20111116 For EMI solution. AD5
HDA Bus(CLG) C430 22p/50V_4
TP9
G34
HDA_SDIN1
SATA2RXP
SATA2TXN
AH5
AH4
DG recommended that AC coupling capacitors should be
SATA2TXP TP15 close to the connector (<100 mils) for optimal signal quality.
R390 33_4 ACZ_BITCLK_R C34
<19> PCH_AZ_CODEC_BITCLK

IHDA
HDA_SDIN2 AB8
R347 33_4 ACZ_SYNC_CODEC A34 SATA3RXN AB10
<19> PCH_AZ_CODEC_SYNC HDA_SDIN3 SATA3RXP
UM77 SATA port 1,3 disable.
AF3
R51 33_4 ACZ_RST#_R SATA3TXN AF1
<19> PCH_AZ_CODEC_RST# SATA3TXP TP26
ACZ_SDOUT_R A36

SATA
R376 33_4 ACZ_SDOUT_R HDA_SDO Y7
<19> PCH_AZ_CODEC_SDOUT SATA4RXN Y5
PCH_GPIO33 C36 SATA4RXP AD3
TP2 HDA_DOCK_EN# / GPIO33 +3V SATA4TXN AD1
PCH JTAG Debug (CLG) TP13
PCH_GPIO13 N32
HDA_DOCK_RST# / GPIO13 +3V_S5 SATA4TXP
Y3
+3V_S5 SATA5RXN SATA_RXN5_C <21>
20111128 Remove net TP_INT#, becaue change to pin E12. Y1 SATA_RXP5_C <21> SATA ODD
SATA5RXP AB3
C SATA5TXN SATA_TXN5 <21> C
<3,22> XDP_TCLK_VT XDP_TCLK_VT J3 AB1 SATA_TXP5 <21>
JTAG_TCK SATA5TXP
XDP_TMS_VT H7 Y11

JTAG
<3,22> XDP_TMS_VT JTAG_TMS SATAICOMPO
R423 R421 R97 <3> PCH_XDP_TDO_VT PCH_XDP_TDO_VT K5 Y10 SATA_COMP R128 37.4/F_4 +1.05V_VTT
210/F_4 210/F_4 210/F_4 JTAG_TDI SATAICOMPI
PCH_XDP_TDO H1
TP14 JTAG_TDO
XDP_TMS_VT AB12
PCH_XDP_TDO_VT SATA3RCOMPO
PCH_XDP_TDO AB13 SATA3_COMP R131 49.9/F_4
XDP_TCLK_VT SATA3COMPI

PCH_SPI_CLK T3 AH1 SATA3_RBIAS R464 750/F_4


SPI_CLK SATA3RBIAS
R428 R422 R419 R96 PCH_SPI_CS0# Y14
51_4 100/F_4 100/F_4 100/F_4 20111110 change power plant to +3V_PCH_ME SPI_CS0# 20111108 PU 10k to +3V, becaue no sata LED.
R524 *47K_4 PCH_SPI_CS1# T1

SPI
+3V_PCH_ME SPI_CS1# P3 SATA_ACT# R443 10K_4 +3V SATA0GP/GPIO21
SATALED#
SATA4GP/GPIO16
PCH_SPI_SI V4 +3V V14 PCH_ODD_EN SATA5GP/GPIO49
SPI_MOSI SATA0GP / GPIO21 PCH_ODD_EN <21>
If these pins are unused use 8.2k
PCH_SPI_SO U3 +3V P1 BBS_BIT0 R459 10K_4
SPI_MISO SATA1GP / GPIO19 +3V to 10k pull-up to +Vcc3_3 or 8.2k
20111127 add R444 PU 10K to +3V for PCH_ODD_EN not use. to 10k pull-down to ground
PCH Dual SPI (Default for WIN8) PCH Strap Table Panther Point_R1P0

(CLG) W25Q32BVSSIG / AKE391P0N00----->4MB


Pin Name Strap description Sampled Configuration
W25Q16BVSSIG / AKE38FP0N01----->2MB
0 = Default (weak pull-down 20K) R460 *1K_4 SPKR
R492 *SHORT_6
SPKR No reboot mode setting PWROK +3V
+3V_S5 +3V_PCH_ME 1 = Setting to No-Reboot mode
+3V_PCH_ME 0 = "top-block swap" mode R418 *1K_4
10/11 add GNT3# / GPIO55 Top-Block Swap Override PWROK PCI_GNT3# <9> Used as GPIO only. at chklist 1.2
B U27 1 = Default (weak pull-up 20K) B
PCH_SPI_CS0# 1 8
PCH_SPI_CLK R490 33_4 6 CE# VDD
PCH_SPI_SI R489 33_4 5 SCK R391 330K_4 PCH_INVRMEN
PCH_SPI_SO R522 33_4 2 SI 7 R491 3.3K_4
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +3V_RTC
SO HOLD#
3 4
C520 WP# VSS C114 GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK
*22p/50V_4 ROM-2M_ME 0.1u/10V_4 GNT1# GNT0# Boot Location
R412 *1K_4
Default weak pull-up on GNT0/1#
1 1 SPI * BBS_BIT1 <9> [Need external pull-down for LPC BIOS]
+3V_PCH_ME R520 3.3K_4 GPIO19 Boot BIOS Selection 0 [bit-0] PWROK 0 0 LPC R448 *1K_4 BBS_BIT0

10/11 add +3V_PCH_ME


U28 0 = effect (default)(weak pull-down 20K)
PCH_SPI_CS1# 1 8 HDA_SDO Flash Descriptor Security RSMRST R377 *SHORT_4 ACZ_SDOUT_R
PCH_SPI_CLK R486 33_4 6 CE# VDD <24> ME_WR# ME_WR default EC setting folating
PCH_SPI_SI R494 33_4 5 SCK 1 = overridden
PCH_SPI_SO R525 33_4 2 SI 7 R488 3.3K_4 R482 2.2K_4
SO HOLD# 0 = Set to Vss (weak pull-down 20K) +1.8V for future CPU, Sandy Bridge NC
DF_TVS DMI/FDI Termination voltage PWROK R483 1K_4 DF_TVS needs to be pulled up to VccDFTERM power rail
DF_TVS <10>
C508 *22p/50V_4 3 4 1 = Set to Vcc through 2.2 kOhm ±5% - R8361 change to 0 or not??
WP# VSS H_SNB_IVB# <3>
C580
20111129 contact to EC thougth series resistor. ROM-4M_EC 0.1u/10V_4 0 = Disable R439 *1K_4
<24> PCH_SPI_CLK_EC GPIO28 On-die PLL Voltage Regulator RSMRST# PLL_ODVR_EN <10>
<24> PCH_SPI_SI_EC 1 = Enable (weak pull-up 20K)
<24> PCH_SPI_SO_EC
R523 3.3K_4
0 = Support by 1.8V (weak pull-down) R350 1K_4 ACZ_SYNC_R
+3V_PCH_ME HDA_SYNC On-Die PLL VR Voltage Select RSMRST +3V_S5 Needs to be pulled High for Huron River platform.
R521 *0_4 PCH_SPI_CS0#
1 = Support by 1.5V chklist 1.2

Intel ME Crypto Transport Layer 0 = Disable (Default)


GPIO15 Security (TLS) cipher suite RSMRST R413 1K_4
1 = Enable +3V_S5 PCH_GPIO15 <10>
internal PD
A <24> SPI_CS0#_UR_ME R526 0_4 PCH_SPI_CS1# A

DEEP S4/S5 well High = Enable (Default) +3V_RTC R60 330K_4 R59 *330K_4
DSWVREN On Die DSW VR Enable DSW
Low = Disable DSWVREN <7>

+3V_PCH_ME R479 *1K_4


NV_ALE Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V NV_ALE <9>
20111103 add pull up 10k to PSI CS#.
Only for Interposer

SPI_CS0#_UR_ME R620 47K_4


Quanta Computer Inc.
PROJECT :Z09
Size Document Number Rev
3A
Panther Point 2/6
Date: Monday, April 09, 2012 Sheet 8 of 40
5 4 3 2 1

www.teknisi-indonesia.com
5 4 3 2 1

CPT/PPT (PCI,USB,NVRAM)
CPT/PPT (PCI-E,SMBUS,CLK)
PCIE port 1 for commeral model S3 can't weak up.
U26B

20111122 add for Touch pad interrupt pin from GPIO13 to GPIO11.
09
BG34
U26E BJ34 PERN1 E12 SMBALERT#
PERP1 +3V_S5 SMBALERT# / GPIO11 SMBALERT# <19>
AY7 AV32
RSVD1 AV7 AU32 PETN1 H14 SMB_PCH_CLK
RSVD2 PETP1 SMBCLK SMB_PCH_CLK <20>
BG26 AU3
BJ26 TP1 RSVD3 BG4 BE34 C9 SMB_PCH_DAT
TP2 RSVD4 <19> PCIE_RX2- PERN2 SMBDATA SMB_PCH_DAT <20>
BH25 <19> PCIE_RX2+ BF34
BJ16 TP3 AT10 C108 0.1U/10V_4 PCIE_TX2-_C BB32 PERP2
TP4 RSVD5 Cardreader <19> PCIE_TX2- PETN2
BG16 BC8 <19> PCIE_TX2+ C105 0.1U/10V_4 PCIE_TX2+_C AY32

SMBUS
AH38 TP5 RSVD6 PETP2 A12 DRAMRST_CNTRL_PCH
TP6 +3V_S5 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <4>
AH37 AU2 <17> PCIE_RX3- BG36
D
AK43 TP7 RSVD7 AT4 BJ36 PERN3 C8 SMB_ME0_CLK
D
TP8 RSVD8 <17> PCIE_RX3+ PERP3 SML0CLK
AK45 AT3 C103 0.1u/10V_4 PCIE_TXN3_C AV34
C18 TP9 RSVD9 AT1
LAN <17> PCIE_TX3-
C100 0.1u/10V_4 PCIE_TXP3_C AU34 PETN3 G12 SMB_ME0_DAT For LAN
TP10 RSVD10 <17> PCIE_TX3+ PETP3 SML0DATA
N30 AY3
H3 TP11 RSVD11 AT5 BF36
AH12 TP12 RSVD12 AV3 BE36 PERN4 20110907 del net SML1ALERT#
AM4 TP13 RSVD13 AV1 AY34 PERP4 C13 SML1ALERT#_R
TP14 RSVD14 PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74 TP24
AM5 BB1 BB34
Y13 TP15 RSVD15 BA3 PETP4 E14 SMB_ME1_CLK
+3V_S5

PCI-E*
K24 TP16 RSVD16 BB5 BG37 SML1CLK / GPIO58
L24 TP17 RSVD17 BB3 BH37 PERN5
+3V_S5 M16 SMB_ME1_DAT For EC
AB46 TP18 RSVD18 BB7 AY36 PERP5 SML1DATA / GPIO75
AB45 TP19 RSVD19 BE8 BB36 PETN5

RSVD
TP20 RSVD20 BD4 PETP5
RSVD21 BF6 BJ38
UM77 4~7 PCIE port disable
RSVD22 BG38 PERN6

Controller
B21 AV5 AU36 PERP6 M7 CL_CLK1
TP21 RSVD23 NV_ALE <8> PETN6 CL_CLK1 CL_CLK1 <20>
M20 AV10 AV36
AY16 TP22 RSVD24 PETP6

Link
BG46 TP23 AT8 BG40 T11 CL_DATA1
TP24 RSVD25 PERN7 CL_DATA1 CL_DATA1 <20>
TX AC cap place at connector side, AC cap to BJ40
AY5 AY40 PERP7
connector < 400mils RSVD26 PETN7
BA2 BB40 P10 CL_RST1#
BE28 USB3.0
USB30_RX1N
RSVD27 PETP7 CL_RST1# CL_RST1# <20>
<23> USB30_RX1- TP25
BC30 USB30_RX2N AT12 BE38
<23> USB30_RX2- BE32 TP26 RSVD28 BF3 <20> PCIE_RX8- BC38 PERN8
TP17 USB30_RX3N
TP27 RSVD29 <20> PCIE_RX8+ PERP8
TP30 BJ32 C106 0.1u/10V_4 PCIE_TXN8_C AW38
BC28 TP28 USB30_RX4N
port9 can be used on debug mode
Wireless <20> PCIE_TX8-
C109 0.1u/10V_4 PCIE_TXP8_C AY38 PETN8
<23> USB30_RX1+ TP29 USB30_RX1P <20> PCIE_TX8+ PETP8
BE30 USB30_RX2P
<23> USB30_RX2+ TP30
TP20 BF32 M10 PCIE_CLKREQ_PEG#_R R103 EV@0_4
TP31 USB30_RX3P PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# <25>
TP29 BG32 C24 <19> CLK_PCIE_MMC# Y40
TP32 USB30_RX4P USBP0N USBP0- <23> CLKOUT_PCIE0N
AV26 USB30_TX1N A24 MB USB left side Cardreader <19> CLK_PCIE_MMC Y39 +3V_S5
<23> USB30_TX1- BB26 TP33 USBP0P C25 USBP0+ <23> CLKOUT_PCIE0P AB37
<23> USB30_TX2- TP34 USB30_TX2N USBP1N USBP1- <23> +3V_S5 CLKOUT_PEG_A_N CLK_PCIE_VGAN <25>

CLOCKS
TP18 AU28 B25 MB usb left side XHCI for USBP0-3 PCIE_CLKREQ0# J2 AB38
TP35 USB30_TX3N USBP1P USBP1+ <23> <19> PCIE_CLKREQ0# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGAP <25>
TP21 AY30 C26
TP36 USB30_TX4N USBP2N TP7
AU26 A26
<23> USB30_TX1+ TP37 USB30_TX1P USBP2P TP1
AY26 K28 AB49 AV22
<23> USB30_TX2+ TP38 USB30_TX2P USBP3N CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_BCLKN <3>
TP16 AV28 H28 AB47 AU22
TP39 USB30_TX3P USBP3P TP61 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_BCLKP <3>
TP19 AW30 E28 EHCI1 +3V
TP40 USB30_TX4P USBP4N
C D28 PCIE_CLKREQ1# M1 C
USBP4P C28 PCIECLKRQ1# / GPIO18 AM12
USBP5N CLKOUT_DP_N CLK_DPLL_SSCLKN <3>
A28 AM13
USBP5P CLKOUT_DP_P CLK_DPLL_SSCLKP <3>
C29 AA48
USBP6N B29 USB port6/7 may not be available on all PCH sku AA47 CLKOUT_PCIE2N
PCI_PIRQA# K40 USBP6P N28 (HM55 support 12port only) CLKOUT_PCIE2P BF18 CLK_BUF_PCIE_3GPLLN
PIRQA# USBP7N +3V CLKIN_DMI_N
PCI_PIRQB# K38 M28 PCIE_CLKREQ2# V10 BE18 CLK_BUF_PCIE_3GPLLP
PCI

PCI_PIRQC# H38 PIRQB# USBP7P L30 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P


G38 PIRQC# USBP8N K30 USBP8- <15>
PCI_PIRQD# Camera
PIRQD# USBP8P USBP8+ <15>
G30 Y37 BJ30 CLK_BUF_BCLKN
USBP9N USBP9- <23> CLKOUT_PCIE3N CLKIN_GND1_N
DGPU_EDIDSEL# C46 +3V E30 MB USB right side Y36 BG30 CLK_BUF_BCLKP
USB

C44 REQ1# / GPIO50 USBP9P C30 USBP9+ <23> CLKOUT_PCIE3P CLKIN_GND1_P


DGPU_SELECT# +3V +3V_S5
REQ2# / GPIO52 USBP10N USBP10- <20>
REQ#3 E40 +3V A30 BT+WL PCIE_CLKREQ3# A8
REQ3# / GPIO54 USBP10P L32 USBP10+ <20> PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREFCLKN
EHCI2 XTAL25_IN
USBP11N TP4 CLKIN_DOT_96N
<8> BBS_BIT1 D47 +3V K32 TP6 E24 CLK_BUF_DREFCLKP

3
4
BOARD_ID2 E42 GNT1# / GPIO51 USBP11P G32 Y43 CLKIN_DOT_96P
<10> BOARD_ID2 GNT2# / GPIO53 +3V USBP12N CLKOUT_PCIE4N
F46 +3V E32 UM77 USB port 6,7,12,13 disable. Y45 Y2
<8> PCI_GNT3# GNT3# / GPIO55 USBP12P CLKOUT_PCIE4P
C32 +3V_S5 AK7 CLK_BUF_DREFSSCLKN 25MHz_XTAL
USBP13N A32 PCIE_CLKREQ4# L12 CLKIN_SATA_N AK5 CLK_BUF_DREFSSCLKP
MPC_PWR_CTRL# G42 USBP13P PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
+3V

1
2
DGPU_PWR_EN G40 PIRQE# / GPIO2 20110908 WLAN support S3 wake up function. XTAL25_OUT
<39> DGPU_PWR_EN
C42 PIRQF# / GPIO3 +3V C33 V45 K45
<25> DGPU_HOLD_RST# DGPU_HOLD_RST# +3V USB_BIAS R86 22.6/F_4 CLK_PCH_14M
PIRQG# / GPIO4 USBRBIAS# <20> CLK_PCIE_WLAN# CLKOUT_PCIE5N REFCLK14IN
EXTTS_SNI_DRV1_PCH D44 +3V Wireless V46
PIRQH# / GPIO5 <20> CLK_PCIE_WLAN CLKOUT_PCIE5P
+3V_S5
B33 <20> PCIE_CLKREQ5# PCIE_CLKREQ5# L14 H45 CLK_PCI_FB C87 10p/50V_4
TP12 PCI_PME# K10 USBRBIAS PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
PME# R133
PCI_PLTRST# C6 +3V_S5 A14 USB_OC0# AB42 V47 XTAL25_IN
<3,24> PCI_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <23> <17> CLK_PCIE_LOM# CLKOUT_PEG_B_N XTAL25_IN
+3V_S5 K20 USB_OC1# AB40 V49 XTAL25_OUT
20111108 Add PCLK_TPM for TPM. +3V_S5
OC1# / GPIO40 B17 USB_OC2#
LAN <17> CLK_PCIE_LOM CLKOUT_PEG_B_P
+3V_S5
XTAL25_OUT
H49 OC2# / GPIO41 C16 RAM_ID0 CLK_PCIE_LAN_REQ# E6 1M_4
H43 CLKOUT_PCI0 +3V_S5 OC3# / GPIO42 L16
<17> CLK_PCIE_LAN_REQ# PEG_B_CLKRQ# / GPIO56
<19> PCLK_TPM R104 22_4 PCLK_TPM_R +3V_S5 USB_OC4# C74 10p/50V_4
CLK_PCI_FB R431 22_4 CLK_PCI_FB_C J48 CLKOUT_PCI1 OC4# / GPIO43 A16 RAM_ID1 Y47 XCLK_RCOMP R132 90.9/F_4
CLKOUT_PCI2 +3V_S5 OC5# / GPIO9 XCLK_RCOMP +1.05V_VTT
R115 22_4 CLK_LPC_DEBUG_C K42 +3V_S5 D14 RAM_ID2 V40
<20> CLK_LPC_DEBUG CLKOUT_PCI3 OC6# / GPIO10 CLKOUT_PCIE6N
R99 22_4 CLK_PCI_775_C H40 +3V_S5 C14 RAM_ID3 TP34 V42
<24> CLK_PCI_EC CLKOUT_PCI4 OC7# / GPIO14 CLKOUT_PCIE6P
+3V_S5 20120201 Change CAP from 27P to 10P.
CLK_PCIE_REQ6# T13
Panther Point_R1P0 PCIECLKRQ6# / GPIO45
V38 +3V K43 CLK_FLEX0 R85 *SHORT_4 SKU_ID1

FLEX CLOCKS
TP42 V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
B CLKOUT_PCIE7P B
+3V_S5 +3V F47 CLK_FLEX1
CLKOUTFLEX1 / GPIO65 TP59
CLK_PCIE_REQ7# K12
PCIECLKRQ7# / GPIO46 H47
+3V CLKOUTFLEX2 / GPIO66 BOARD_ID4 <10,19>
AK14
<3> CLK_PCIE_XDPN CLKOUT_ITPXDP_N
<3> CLK_PCIE_XDPP AK13 +3V K49 R457 *SHORT_4 ODD_PRSNT# <21>
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67

Panther Point_R1P0

PLTRST#(CLG) +3V 20111128 change power plant to +3V. PCI/USBOC# Pull-up(CLG)


+3V_S5 +3V CLK_REQ/Strap Pin(CLG) SMBus(EC) +3V_S5 SMBus(PCH)
+3V
PCI_PIRQA# R74 8.2K_4
USB_OC0# R55 10K_4 PCI_PIRQB# R75 8.2K_4 +3V_S5
C417 USB_OC1# R82 10K_4 PCI_PIRQC# R373 8.2K_4
0.1u/10V_4 USB_OC2# R392 10K_4 PCI_PIRQD# R40 8.2K_4 R79 10K_4 PCIE_CLKREQ4# R338 R339 R316 R317
USB_OC4# R88 10K_4 R364 10K_4 PCIE_CLKREQ5# 2.2K_4 2.2K_4 4.7K_4 4.7K_4
5

R430 10K_4 PCIE_CLKREQ0#


PCI_PLTRST# 2
4 +3V
R399 10K_4 PCIE_CLKREQ3#
5
Q19
S5 5
Q20
S0
PLTRST# R402 10K_4 CLK_PCIE_LAN_REQ#
PLTRST# <17,19,20,24,25>
1 R44 R365 10K_4 CLK_PCIE_REQ6#
10 1 DGPU_HOLD_RST# R83 10K_4 CLK_PCIE_REQ7# 3 4 SMB_ME1_CLK SMB_PCH_DAT 3 4
<24> 2ND_MBCLK
U23 MPC Switch Control MPC_PWR_CTRL# 9 2 DGPU_EDIDSEL# CLK_SDATA <13,14,19>
3

TC7SH08FU R351 EXTTS_SNI_DRV1_PCH 8 3 dGPU_SELECT# +3V


100K_4 Low = MPC ON REQ#3 7 4 2 2
MPC_PWR_CTRL# High = MPC OFF (Default) 6 5 R424 10K_4 PCIE_CLKREQ1#
R124 10K_4 PCIE_CLKREQ2# <24> 2ND_MBDATA 6 1 SMB_ME1_DAT SMB_PCH_CLK 6 1
10KX8 CLK_SCLK <13,14,19>
MPC_PWR_CTRL# R49 *1K_4
R366 *0_4 +3V_S5
2N7002DW 2N7002DW
R102 10K_4 PCIE_CLKREQ_PEG#_R

dGPU_PW_CTRL# SKU_ID1 SKU_ID0 VGA H/W Setup 20111021 remove pull/down resistor
DDRIII Memory down strap Optimize SKU (GPIO68) (GPIO64) (GPIO16) Signal Menu 20111117 change footprint to dual type.
RAM RAM_IDn CTL : dGPU_VRON
A +3V_S5 A
+3V UMA Only 1 0 0 UMA Hidden UMA boot CLK_BUF_BCLKN R504 10K_4
R394 *RAMID@5K/F_4 RAM_ID0 R379 RAMID@10K_4 CLK_BUF_BCLKP R503 10K_4
R393 RAMID@15K/F_4 RAM_ID1 R378 *RAMID@10K_4 Hynix 0x000 R93 EV@10K_4 SKU_ID1
R70 RAMID@15K/F_4 RAM_ID2 R71 *RAMID@10K_4 R100 IV@10K_4 dGPU Only 0 or 1 0 1 GPU Hidden GPU boot
R395 RAMID@15K/F_4 RAM_ID3 R380 *RAMID@10K_4 CLK_BUF_PCIE_3GPLLN R164 10K_4 +3V_S5
Elpida 0x001 Switchable CLK_BUF_PCIE_3GPLLP R163 10K_4
(Mux) 0 1 0 UMA+GPU dGPU/SG UMA boot CLK_BUF_DREFCLKN R89 10K_4 if net DRAMRST_CNTRL_PCH change to PCH control need stuff R358.
+3V CLK_BUF_DREFCLKP R90 10K_4
Optimize CLK_BUF_DREFSSCLKN R480 10K_4
R108 EV@10K_4 (Muxless) 0 1 1 UMA UMA/SG UMA boot CLK_BUF_DREFSSCLKP R478 10K_4
SKU_ID0 <10>
R114 IV@10K_4 CLK_PCH_14M R111 10K_4

+3V dGPU_PW_CTRL#
R72 10K_4 SMBALERT# Quanta Computer Inc.
CLOCK TERMINATION for FCIM R343 2.2K_4 SMB_PCH_CLK
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) R340 2.2K_4 SMB_PCH_DAT
1 = GPU power is control by H/W (pure Discrete SKU) R361 2.2K_4 SMB_ME0_CLK
PROJECT : Z09
R386 *100K_4 DGPU_PWR_EN R370 10K_4 R360 2.2K_4 SMB_ME0_DAT Size Document Number Rev
R357 10K_4 SML1ALERT#_R 3A
Panther Point 3/6
Date: Monday, April 09, 2012 Sheet 9 of 40
5 4 3 2 1

www.teknisi-indonesia.com
5 4 3 2 1

S_GPIO R112 100_4


CPT/PPT (GPIO,VSS_NCTF,RSVD)
T7
U26F

BMBUSY# / GPIO0 +3V +3V TACH4 / GPIO68


C40 DGPU_PW_CTRL#
GPIO Pull-up/Pull-down(CLG)
10
SIO_EXT_SMI# A42 +3V +3V B41 LCD_SELECT
<24> SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
BOARD_ID1 H36 +3V +3V C41 BOARD_ID3 +3V_S5
TACH2 / GPIO6 TACH6 / GPIO70
D SIO_EXT_SCI# E38 A40 R407 1.5K/F_4 PCH_GPIO24 R73 *10K_4 D
<24> SIO_EXT_SCI# TACH3 / GPIO7 +3V +3V TACH7 / GPIO71 +3V
ICC_EN# C10 +3V_S5 PLL_ODVR_EN R440 10K_4
TP25 GPIO8
SMIB C4 +3V
LAN_PHY_PWR_CTRL / GPIO12 +3V_S5
G2 P4 SIO_A20GATE SIO_EXT_SMI# R39 10K_4
<8> PCH_GPIO15 GPIO15 +3V_S5 A20GATE SIO_A20GATE <24>
SIO_EXT_SCI# R50 10K_4
AU16 EC_PECI_R R162 *0_4
PECI EC_PECI <3,24>
U2 STP_PCI# R420 *10K_4
<9> SKU_ID0 SATA4GP / GPIO16 +3V P5 SIO_RCIN# SIO_A20GATE R105 10K_4
RCIN# SIO_RCIN# <24>
SIO_RCIN# R98 10K_4

GPIO
TP75
DGPU_PWROK D40 AY11 CRIT_TEMP_REP# R458 10K_4
TACH0 / GPIO17 +3V

CPU/MISC
<25> DGPU_PWROK PROCPWRGD H_PWRGOOD <3>
G_SENSOR_ID T5 AY10 PCH_THRMTRIP# R156 390_4 +3VPCU
SCLOCK / GPIO22 +3V THRMTRIP# PM_THRMTRIP# <3>
20120201 reserve GPIO27 PU +3VPCU
PCH_GPIO24 E8 T14 R616 10K_4
GPIO24 / MEM_LED+3V_S5 INIT3_3V# WK_GPIO27 R101 *10K_4
WK_GPIO27 E16 DSW AY1
<24> WK_GPIO27 GPIO27 DF_TVS DF_TVS <8>
20111017 un-stuff R5126 for DSW
PLL_ODVR_EN P8 +3V_S5 DGPU_PWROK R87 *10K_4
<8> PLL_ODVR_EN GPIO28 AH8
STP_PCI# K1 TS_VSS1
STP_PCI# / GPIO34 +3V
AK11 GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.
DGPU_VRON K4 TS_VSS2
<38,39> DGPU_VRON GPIO35 +3V AH10
C TS_VSS3 C
DMI_OVRVLTG V8
SATA2GP / GPIO36 +3V AK10
TS_VSS4
Low = Tx, Rx terminated to
FDI_OVRVLTG M5 DMI TERMINATION
SATA3GP / GPIO37 +3V same voltage (DC Coupling Mode)
VOLTAGE OVERRIDE (DEFAULT)
MFG_MODE N2 P37 USB3.0 IC CTL
SLOAD / GPIO38 +3V NC_1
BOARD_ID0 M3 +3V
SDATAOUT0 / GPIO39 +3V
LOW = USB3.0 IC
20110907 del R5217 and net SML1ALERT# TEST_SET_UP V13 +3V BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
CRIT_TEMP_REP# V3 +3V BG48
SATA5GP / GPIO49 VSS_NCTF_16 R148 *10K_4 DMI_OVRVLTG R146 *200K/F_4
SV_DET D6 BH3
TP23 GPIO57 +3V_S5 VSS_NCTF_17 +3V_S5
BH47
VSS_NCTF_18 SMIB R401 10K_4
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44 high VDDR=+1.35V_SUS for DDR3L
VSS_NCTF_2 VSS_NCTF_20 +3V_S5 Low VDDR =+1.5V_SUS(default)
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21 R362 *10K_4 SV_DET R400 100K_4

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 assign to VID for VDDR control
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
B SV_SET_UP B
A6 BJ6 +3V
VSS_NCTF_6 VSS_NCTF_24
B3 C2 High = Strong (Default) R106 10K_4 BOARD_ID0 R107 *10K_4
VSS_NCTF_7 VSS_NCTF_25 R389 10K_4 BOARD_ID1 R374 *10K_4
B47 C48 R385 10K_4 BOARD_ID2 R369 *10K_4
VSS_NCTF_8 VSS_NCTF_26 +3V R384 *10K_4 BOARD_ID3 R368 10K_4
BD1 D1 R425 *10K_4 BOARD_ID4 R427 10K_4
VSS_NCTF_9 VSS_NCTF_27 TEST_SET_UP R147 10K_4 <9> BOARD_ID2
BD49 D49 R149 *1K_4
VSS_NCTF_10 VSS_NCTF_28 <9,19> BOARD_ID4
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
Board_ID4 Hight=Symatic, LOW=ELAN.
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
SGPIO
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32 GPU power is control by
SATA2GP : strap for reserved at chklist 1.2 +3V high H/W (pure Discrete SKU)
Panther Point_R1P0
SATA3GP : strap for reserved at chklist 1.2 S_GPIO R113 1K_4 GPU power is control by PCH
NOTE: The internal pull-down is disabled after PLTRST# deasserts. R116 *1K_4 +3V low GPIO (Discrete, SG or Optimize)
NOTE: This signal should not be pulled high when strap is sampled.
R372 IV@1K_4 DGPU_PW_CTRL# R388 EV@100K_4
A A
2011/09/01 add select resistor +3V +3V +3V

LCD_SELECT R371 *LVDS@1.5K/F_4 R436 100K_4 FDI_OVRVLTG R437 *1K_4 G_SENSOR_ID R117 10K_4
R119 *1K_4
R387 EDP@1K_4
MFG-TEST Quanta Computer Inc.
+3V

LVDS = Pull HIGH FDI TERMINATION LOW - Tx, Rx terminated High = Disable (Default) MFG_MODE R445 10K_4
PROJECT : Z09
VOLTAGE OVERRIDE to same voltage G_SENSOR_ID R444 *1K_4 Size Document Number Rev
eDP = Pull LOW Low = Enable Panther Point 4/6 3A

Date: Monday, April 09, 2012 Sheet 10 of 40


5 4 3 2 1

www.teknisi-indonesia.com
5 4 3 2 1

PCH5(CLG)

20111021 remove vcc core power sense net


CPT/PPT (POWER)
+VCCA_DAC_1_2 +3V
11
VccADAC =1mA(8mils)
U26G POWER L2 180ohm/5A CPT/PPT (POWER)
+1.05V_VTT R136 *0_8
+1.05V_VTT +1.05V_VTT
VccCORE =1.3 A(60mils) C61 C55 C43

20111117 remove 0ohm resistor.


AA23
AC23 VCCCORE[1] VCCADAC
U48 C47
10u/6.3V_6
0.01u/25V_4 0.1u/10V_4 10u/6.3V_6
20120104 change power plant from +3V_S5 to +3VPCU.
U26J POWER
VCCCORE[2]

CRT
AD21 +VCCACLK AD49 N26 20111117 remove 0ohm resistor.
C82 C81 C92 C88 AD23 VCCCORE[3] U47 R449 *SHORT_4 VCCACLK VCCIO[29] C59
VCCCORE[4] VSSADAC +3VPCU

VCC CORE
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 4.7u/6.3V_6 AF21 VCCDSW3_3= 3mA P26 1u/6.3V_4 VCCSUS3_3 = 119mA(15mils)
AF23 VCCCORE[5] +VCCPDSW T16 VCCIO[30]
AG21 VCCCORE[6] VCCDSW3_3 P28 +3VCC_S5
D
R5285 near PCH ball for VCCP GND sense AG23 VCCCORE[7] VCCIO[31] D
AG24 VCCCORE[8] AK36 C52 PCH_VCCDSW V12 T27 R56 *SHORT_6 20111018 change for DSW
AG26 VCCCORE[9] VCCALVDS 0.1u/10V_4 DCPSUSBYP VCCIO[32]
+1.05V_VTT AG27 VCCCORE[10] AK37 T29
AG29 VCCCORE[11] VSSALVDS C65 +3V_SUS_CLKF33 T38 VCCIO[33] C62
VCCCORE[12] When Dis sku and eDP , LVDS power can short to GND +1.05V_VTT +VCCAPLL_CPY_PCH VCC3_3[5]
AJ23 *0.1u/10V_4 0.1u/10V_4

LVDS
20111117 remove 0ohm resistor. AJ26 VCCCORE[13] AM37 T23 +3V_VCCPUSB
+1.05V_VTT +1.05V_VCCAPLL_EXP AJ27 VCCCORE[14] VCCTX_LVDS[1] 20111101 remove vccalcd and vcctx_lds power, when LVDS disable. L7 *10uH/100mA_8 BH23 VCCSUS3_3[7]
AJ29 VCCCORE[15] AM38 VCCAPLLDMI2 T24
L6 *1uH/25mA_6 AJ31 VCCCORE[16] VCCTX_LVDS[2] R141 *SHORT_6 +VCCDPLL_CPY AL29 VCCSUS3_3[8] R57 *SHORT_6
VCCCORE[17] +1.05V_VTT VCCIO[14]
AP36 C118 V23

USB
VCCTX_LVDS[3] *10u/6.3V_6 VCCSUS3_3[9]
C119 AP37 +VCCSUS1 AL24 V24 C50
*10u/6.3V_6 AN19 VCCTX_LVDS[4] DCPSUS[3] VCCSUS3_3[10] 0.1u/10V_4
VCCIO[28] P24 +3V_VCCAUBG
C97 VCCSUS3_3[6]
VCCME(+1.05V) = ??A(??mils)
BJ22 +3V_VCC_GIO +3V *1u/6.3V_4 AA19
+1.05V_VTT VCCAPLLEXP VCCASW[1] T26 +VCCAUPLL R123 *SHORT_6
+1.05V_VTT VCCIO[34] +1.05V_VTT
VccIO =2.925 A(140mils) V33 AA21 VCC5REFSUS=1mA

HVCMOS
AN16 VCC3_3[6] R125 *SHORT_6 VCCASW[2]
VCCIO[15] +1.05V_VTT
VccASW =1.01 A(60mils)
AA24 M26 +5V_PCH_VCC5REFSUS R110 10/F_4
VCCASW[3] V5REF_SUS +5VCC_S5
20111117 remove 0ohm resistor. AN17 C66 VCCDMI = 42mA(10mils)
C99 C98 C91 VCCIO[16] V34 0.1u/10V_4 +1.1V_VCC_DMI AA26 D11 RB500V-40

Clock and Miscellaneous


VCC3_3[7] VCCASW[4] +3VCC_S5
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C84 C79 C80 AN23 +VCCA_USBSUS C44
AN21 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 AA27 DCPSUS[4] 0.1u/10V_4 20111018 change for DSW
VCCIO[17] R169 *SHORT_4 VCCASW[5] AN24 +3V_VCCPSUS
AN26 AA29 VCCSUS3_3[1] C96
VCCIO[18] C104 VCCASW[6] *1u/6.3V_4
AN27 AT16 +VCCAFDI_VRM +VCCAFDI_VRM 1u/6.3V_4 20120216 remove R168 for power plant chnge to +1.05V_VTT. AA31 V5REF= 1mA
VCCIO[19] VCCVRM[3] VCCASW[7]
+1.1V VCC_DMI witdth >= 20mils.
C94 C101 AP21 AC26 P34 +5V_PCH_VCC5REF R353 10/F_4
VCCIO[20] VCCASW[8] V5REF +5V
1u/6.3V_4 10u/6.3V_6 C69 C70
AP23 AT20 VCCCLKDMI = 20mA(8mils) 10u/6.3V_6 10u/6.3V_6 AC27 D10 RB500V-40 +3V
VCCIO[21] VCCDMI[1] VCCASW[9] N20 C49

DMI

PCI/GPIO/LPC
AP24 +1.1V_VCC_DMI_CCI +VCC_DMI_CCI +1.05V_VTT AC29 VCCSUS3_3[2] 1u/6.3V_4

VCCIO
VCCIO[22] VCCASW[10] N22 20111018 change for DSW
AP26 AB36 L4 *10uH/100mA_8 AC31 VCCSUS3_3[3]
VCCIO[23] VCCCLKDMI R144 *1/F_4 VCCASW[11] P20 +3V_VCCPSUS R58 *SHORT_6
VCCSUS3_3[4] +3VCC_S5
AT24 AD29
+3V +3V_VCC_EXP VCCIO[24] C78 C77 R139 *SHORT_4 VCCASW[12] P22
C
VCCSUS3_3[5]
VCCSUS3_3 = 119mA(15mils) C
1u/6.3V_4 *10u/6.3V_6 AD31 C48
R167 *SHORT_8 AN33 VCCASW[13] 1u/10V_4
VCCIO[25] W21 AA16
AN34 AG16 VCCASW[14] VCC3_3[1]
C121 VCCIO[26] VCCDFTERM[1] +VCCP_NAND +1.8V W23 W16 +3V_VCCPCORE R130 *SHORT_6
VCCPNAND = 190 mA(15mils) VCCASW[15] VCC3_3[8] +3V
0.1u/10V_4
BH29 AG17 W24 T34 VCCPCORE = 28mA(10mils)
+3V

DFT / SPI
VCC3_3[3] VCCDFTERM[2] R159 *SHORT_8 VCCASW[16] VCC3_3[4] C71
W26 0.1u/10V_4
AJ16 C93 VCCASW[17] C56
VCCDFTERM[3] 0.1u/10V_4 W29 0.1u/10V_4
+VCCAFDI_VRM AP16 VCCASW[18]
+VCCAFDI_VRM VCCVRM[2] +1.05V_VTT
AJ17 W31 AJ2 +3V
VCCDFTERM[4] VCCASW[19] VCC3_3[2]
+1.05V_VTT R506 *0_8 +1.05V_VCCAPLL_FDI BG6 R134 *SHORT_6 W33
VccAFDIPLL VCCASW[20] AF13 C95
+3V_VCCME_SPI VCCIO[5] 0.1u/10V_4
VCCSPI = 20mA(8mils)
+1.05V_VCCDPLL_FDI AP17 C86 C51 0.1u/10V_4 +VCCRTCEXT N16
VCCIO[27] DCPRTC
FDI

R158 *SHORT_8 V1 1u/6.3V_4 AH13 +1.05V_VTT


VCCSPI VCCIO[12]
AU20 +VCCAFDI_VRM Y49 AH14 20111117 remove 0ohm resistor.
+1.1V_VCC_DMI VCCDMI[2] +VCCAFDI_VRM VCCVRM[4] VCCIO[13]
C67 R138 *SHORT_6 C89
+1.1V VCC_DMI witdth >= 20mils. 1u/6.3V_4 1u/10V_4
Panther Point_R1P0 AF14
C85 +1.05V_VCCA_A_DPL BD47 VCCIO[6]
65mA(10mils) ??mA(??mils)

SATA
1u/6.3V_4 VCCADPLLA AK1 +V1.1LAN_VCCAPLL L24 *10uH/100mA_8
VCCAPLLSATA +1.05V_VTT
8mA(8mils) +1.05V_VCCA_B_DPL BF47 VCCVRM= 114mA(15mils)
VCCADPLLB C476
R143 *SHORT_6 AF11 +VCCAFDI_VRM *10u/6.3V_6
+VCCDIFFCLK AF17 VCCVRM[1]
VccDMI needs to be powered by the same 1.05 V voltage source as +VCCDIFFCLKN AF33 VCCIO[7]
the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/ C90 AF34 VCCDIFFCLKN[1] AC16
VCC reference plane. VCCDIFFCLKN[2] VCCIO[2] +1.05V_VTT
20120105 change power plant to +3V for power saving. 1u/6.3V_4 VCCDIFFCLKN= 55mA(10mils) AG34
+1.05V_VTT VCCDIFFCLKN[3] AC17 20111117 remove 0ohm resistor.
+3V VCCIO[3] C76
VCCSSC= 95mA(10mils)
+3V_VCCME_SPI R127 *0_6 +V1.05V_SSCVCC AG33 AD17 1u/6.3V_4
+VCCAFDI_VRM R634 *0_6 +3V_S5 VCCSSC VCCIO[4]

R121 0_6 C63 C58 0.1u/10V_4 +VCCSST V16 +1.05V_VTT VCCME = 1.01A(60mils)
B
*1u/6.3V_4 DCPSST B
VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1
+1.5V R170 *SHORT_6 1.5V (Mobile)
Reserve +3V_S5 to VCCSPI for EC 795 co-layout +1.05V_VTT T17 T21
R171 *0_6 +V1.05M_VCCSUS V19 DCPSUS[1] VCCASW[22]
+1.05V_VTT

MISC
DCPSUS[2]
R173 *SHORT_41mA(8mils) +VTT_VCCPCPU V21
VCCASW[23]

CPU
BJ8
20120216 remove R172 for power plant chnge to +1.05V_VTT. C111 C120 C116 V_PROC_IO T19
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 VCCASW[21]
VCCRTC<1mA(8mils) +3V_RTC 20111107 remove R5144 PU 1.5VSUS.

RTC
A22 P32 +V3.3A_1.5A_HDA_IO R375 *SHORT_4 VCCSUSHDA= 10mA(8mils)

HDA
VCCRTC VCCSUSHDA +3V_S5

C40 C37 C39 Panther Point_R1P0 C53 C429


1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 *1u/6.3V_4 0.1u/10V_4

+5VCC_S5 +3V_S5 +3VCC_S5

+5V_S5 1 3 1 3

+3V C411 R354 AO3413 Q23 C412 R355 AO3413 Q22


+1.05V_VTT L5 10uH/100mA_8 +1.05V_VCCA_A_DPL *0.33u/10V_6 100K_4 *0.33u/10V_6 100K_4

2
R118 *0_6

R126 1/F_4 L3 10uH/100mA_8 +3V_SUS_CLKF33 + C529 C115


220u/2.5V_3528 1u/6.3V_4 R344
*SHORT_6 R345
C68 C57 *SHORT_6
4.7u/6.3V_6 1u/10V_4
L26 10uH/100mA_8 +1.05V_VCCA_B_DPL
<7,24> SLP_SUS#

6
A + C512 C112 A
220u/2.5V_3528 1u/6.3V_4 Q24
2N7002DW

20111117 change mose footprint to dual type.

1
20111018 ADD DSW Cricuit Quanta Computer Inc.
20111030 modify cuirucit.
PROJECT : Z09
Size Document Number Rev
3A
Panther Point 5/6
Date: Monday, April 09, 2012 Sheet 11 of 40
5 4 3 2 1

www.teknisi-indonesia.com
5 4 3 2 1

PCH6(CLG)
12
U26I

AY4 H46
IBEX PEAK-M (GND) AY42
AY46
VSS[159]
VSS[160]
VSS[259]
VSS[260]
K18
K26
AY8 VSS[161] VSS[261] K39
D VSS[162] VSS[262] D
B11 K46
B15 VSS[163] VSS[263] K7
B19 VSS[164] VSS[264] L18
B23 VSS[165] VSS[265] L2
B27 VSS[166] VSS[266] L20
B31 VSS[167] VSS[267] L26
B35 VSS[168] VSS[268] L28
B39 VSS[169] VSS[269] L36
B7 VSS[170] VSS[270] L48
U26H F45 VSS[171] VSS[271] M12
H5 BB12 VSS[172] VSS[272] P16
VSS[0] BB16 VSS[173] VSS[273] M18
AA17 AK38 BB20 VSS[174] VSS[274] M22
AA2 VSS[1] VSS[80] AK4 BB22 VSS[175] VSS[275] M24
AA3 VSS[2] VSS[81] AK42 BB24 VSS[176] VSS[276] M30
AA33 VSS[3] VSS[82] AK46 BB28 VSS[177] VSS[277] M32
AA34 VSS[4] VSS[83] AK8 BB30 VSS[178] VSS[278] M34
AB11 VSS[5] VSS[84] AL16 BB38 VSS[179] VSS[279] M38
AB14 VSS[6] VSS[85] AL17 BB4 VSS[180] VSS[280] M4
AB39 VSS[7] VSS[86] AL19 BB46 VSS[181] VSS[281] M42
AB4 VSS[8] VSS[87] AL2 BC14 VSS[182] VSS[282] M46
AB43 VSS[9] VSS[88] AL21 BC18 VSS[183] VSS[283] M8
AB5 VSS[10] VSS[89] AL23 BC2 VSS[184] VSS[284] N18
AB7 VSS[11] VSS[90] AL26 BC22 VSS[185] VSS[285] P30
AC19 VSS[12] VSS[91] AL27 BC26 VSS[186] VSS[286] N47
AC2 VSS[13] VSS[92] AL31 BC32 VSS[187] VSS[287] P11
AC21 VSS[14] VSS[93] AL33 BC34 VSS[188] VSS[288] P18
AC24 VSS[15] VSS[94] AL34 BC36 VSS[189] VSS[289] T33
AC33 VSS[16] VSS[95] AL48 BC40 VSS[190] VSS[290] P40
AC34 VSS[17] VSS[96] AM11 BC42 VSS[191] VSS[291] P43
AC48 VSS[18] VSS[97] AM14 BC48 VSS[192] VSS[292] P47
C AD10 VSS[19] VSS[98] AM36 BD46 VSS[193] VSS[293] P7 C
AD11 VSS[20] VSS[99] AM39 BD5 VSS[194] VSS[294] R2
AD12 VSS[21] VSS[100] AM43 BE22 VSS[195] VSS[295] R48
AD13 VSS[22] VSS[101] AM45 BE26 VSS[196] VSS[296] T12
AD19 VSS[23] VSS[102] AM46 BE40 VSS[197] VSS[297] T31
AD24 VSS[24] VSS[103] AM7 BF10 VSS[198] VSS[298] T37
AD26 VSS[25] VSS[104] AN2 BF12 VSS[199] VSS[299] T4
AD27 VSS[26] VSS[105] AN29 BF16 VSS[200] VSS[300] W34
AD33 VSS[27] VSS[106] AN3 BF20 VSS[201] VSS[301] T46
AD34 VSS[28] VSS[107] AN31 BF22 VSS[202] VSS[302] T47
AD36 VSS[29] VSS[108] AP12 BF24 VSS[203] VSS[303] T8
AD37 VSS[30] VSS[109] AP19 BF26 VSS[204] VSS[304] V11
AD38 VSS[31] VSS[110] AP28 BF28 VSS[205] VSS[305] V17
AD39 VSS[32] VSS[111] AP30 BD3 VSS[206] VSS[306] V26
AD4 VSS[33] VSS[112] AP32 BF30 VSS[207] VSS[307] V27
AD40 VSS[34] VSS[113] AP38 BF38 VSS[208] VSS[308] V29
AD42 VSS[35] VSS[114] AP4 BF40 VSS[209] VSS[309] V31
AD43 VSS[36] VSS[115] AP42 BF8 VSS[210] VSS[310] V36
AD45 VSS[37] VSS[116] AP46 BG17 VSS[211] VSS[311] V39
AD46 VSS[38] VSS[117] AP8 BG21 VSS[212] VSS[312] V43
AD8 VSS[39] VSS[118] AR2 BG33 VSS[213] VSS[313] V7
AE2 VSS[40] VSS[119] AR48 BG44 VSS[214] VSS[314] W17
AE3 VSS[41] VSS[120] AT11 BG8 VSS[215] VSS[315] W19
AF10 VSS[42] VSS[121] AT13 BH11 VSS[216] VSS[316] W2
AF12 VSS[43] VSS[122] AT18 BH15 VSS[217] VSS[317] W27
AD14 VSS[44] VSS[123] AT22 BH17 VSS[218] VSS[318] W48
AD16 VSS[45] VSS[124] AT26 BH19 VSS[219] VSS[319] Y12
AF16 VSS[46] VSS[125] AT28 H10 VSS[220] VSS[320] Y38
AF19 VSS[47] VSS[126] AT30 BH27 VSS[221] VSS[321] Y4
AF24 VSS[48] VSS[127] AT32 BH31 VSS[222] VSS[322] Y42
AF26 VSS[49] VSS[128] AT34 BH33 VSS[223] VSS[323] Y46
B AF27 VSS[50] VSS[129] AT39 BH35 VSS[224] VSS[324] Y8 B
AF29 VSS[51] VSS[130] AT42 BH39 VSS[225] VSS[325] BG29
AF31 VSS[52] VSS[131] AT46 BH43 VSS[226] VSS[328] N24
AF38 VSS[53] VSS[132] AT7 BH7 VSS[227] VSS[329] AJ3
AF4 VSS[54] VSS[133] AU24 D3 VSS[228] VSS[330] AD47
AF42 VSS[55] VSS[134] AU30 D12 VSS[229] VSS[331] B43
AF46 VSS[56] VSS[135] AV16 D16 VSS[230] VSS[333] BE10
AF5 VSS[57] VSS[136] AV20 D18 VSS[231] VSS[334] BG41
AF7 VSS[58] VSS[137] AV24 D22 VSS[232] VSS[335] G14
AF8 VSS[59] VSS[138] AV30 D24 VSS[233] VSS[337] H16
AG19 VSS[60] VSS[139] AV38 D26 VSS[234] VSS[338] T36
AG2 VSS[61] VSS[140] AV4 D30 VSS[235] VSS[340] BG22
AG31 VSS[62] VSS[141] AV43 D32 VSS[236] VSS[342] BG24
AG48 VSS[63] VSS[142] AV8 D34 VSS[237] VSS[343] C22
AH11 VSS[64] VSS[143] AW14 D38 VSS[238] VSS[344] AP13
AH3 VSS[65] VSS[144] AW18 D42 VSS[239] VSS[345] M14
AH36 VSS[66] VSS[145] AW2 D8 VSS[240] VSS[346] AP3
AH39 VSS[67] VSS[146] AW22 E18 VSS[241] VSS[347] AP1
AH40 VSS[68] VSS[147] AW26 E26 VSS[242] VSS[348] BE16
AH42 VSS[69] VSS[148] AW28 G18 VSS[243] VSS[349] BC16
AH46 VSS[70] VSS[149] AW32 G20 VSS[244] VSS[350] BG28
AH7 VSS[71] VSS[150] AW34 G26 VSS[245] VSS[351] BJ28
AJ19 VSS[72] VSS[151] AW36 G28 VSS[246] VSS[352]
AJ21 VSS[73] VSS[152] AW40 G36 VSS[247]
AJ24 VSS[74] VSS[153] AW48 G48 VSS[248]
AJ33 VSS[75] VSS[154] AV11 H12 VSS[249]
AJ34 VSS[76] VSS[155] AY12 H18 VSS[250]
AK12 VSS[77] VSS[156] AY22 H22 VSS[251]
AK3 VSS[78] VSS[157] AY28 H24 VSS[252]
VSS[79] VSS[158] H26 VSS[253]
Panther Point_R1P0 H30 VSS[254]
H32 VSS[255]
A A
H34 VSS[256]
F3 VSS[257]
VSS[258]

Panther Point_R1P0

Quanta Computer Inc.


PROJECT : Z09
Size Document Number Rev
3A
Panther Point 6/6
Date: Monday, April 09, 2012 Sheet 12 of 40
5 4 3 2 1

www.teknisi-indonesia.com
5 4 3 2 1

DDR3 DIMM-A

JDIM1A M_A_DQ[63:0] <4>


+1.5VSUS

75
76
81
82
87
JDIM1B

VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
55
13
<4> M_A_A[15:0] 98 5 88 VDD5 VSS20 60
M_A_A0 M_A_DQ5
M_A_A1 97 A0 DQ0 7 M_A_DQ1 93 VDD6 VSS21 61
M_A_A2 96 A1 DQ1 15 M_A_DQ6 94 VDD7 VSS22 65
M_A_A3 95 A2 DQ2 17 M_A_DQ7
2.48A 99 VDD8 VSS23 66
M_A_A4 92 A3 DQ3 4 M_A_DQ4 100 VDD9 VSS24 71
D A4 DQ4 VDD10 VSS25 D
M_A_A5 91 6 M_A_DQ0 105 72
M_A_A6 90 A5 DQ5 16 M_A_DQ3 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM


M_A_A7 86 A6 DQ6 18 M_A_DQ2 111 VDD12 VSS27 128
M_A_A8 89 A7 DQ7 21 M_A_DQ13 112 VDD13 VSS28 133
M_A_A9 85 A8 DQ8 23 M_A_DQ8 117 VDD14 VSS29 134
M_A_A10 107 A9 DQ9 33 M_A_DQ14 118 VDD15 VSS30 138
M_A_A11 84 A10/AP DQ10 35 M_A_DQ15 123 VDD16 VSS31 139
M_A_A12 83 A11 DQ11 22 M_A_DQ12 124 VDD17 VSS32 144
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ9 VDD18 VSS33 145
M_A_A14 80 A13 DQ13 34 M_A_DQ11 199 VSS34 150
78 A14 DQ14 36 +3V VDDSPD VSS35 151
M_A_A15 M_A_DQ10
A15 DQ15 39 M_A_DQ20 77 VSS36 155

PC2100 DDR3 SDRAM SO-DIMM


109 DQ16 41 M_A_DQ21 122 NC1 VSS37 156
<4> M_A_BS#0 108 BA0 DQ17 51 125 NC2 VSS38 161
M_A_DQ22
<4> M_A_BS#1 79 BA1 DQ18 53 NCTEST VSS39 162
M_A_DQ19
<4> M_A_BS#2 114 BA2 DQ19 40 198 VSS40 167
M_A_DQ16 TP22
<4> M_A_CS#0 121 S0# DQ20 42 30 EVENT# VSS41 168
M_A_DQ17
<4> M_A_CS#1 101 S1# DQ21 50 <4,14> DDR3_DRAMRST# RESET# VSS42 172
M_A_DQ23
<4> M_A_CLK0 103 CK0 DQ22 52 VSS43 173
M_A_DQ18
<4> M_A_CLK0# 102 CK0# DQ23 57 1 VSS44 178
M_A_DQ29 R559 *M3@0_6 +SMDDR_VREF_DQ0
<4> M_A_CLK1 104 CK1 DQ24 59 <6> SMDDR_VREF_DQ0_M3 126 VREF_DQ VSS45 179
M_A_DQ28 +SMDDR_VREF_DIMM_A
<4> M_A_CLK1# 73 CK1# DQ25 67 VREF_CA VSS46 184
M_A_DQ30
<4> M_A_CKE0 74 CKE0 DQ26 69 VSS47 185
M_A_DQ25
<4> M_A_CKE1 115 CKE1 DQ27 56 2 VSS48 189
M_A_DQ27
<4> M_A_CAS# 110 CAS# DQ28 58 3 VSS1 VSS49 190
M_A_DQ24
<4> M_A_RAS# 113 RAS# DQ29 68 8 VSS2 VSS50 195
M_A_DQ26

(204P)
<4> M_A_WE# 197 WE# DQ30 70 9 VSS3 VSS51 196
C R238 10K_4 DIMM1_SA0 M_A_DQ31 C
R239 10K_4 DIMM1_SA1 201 SA0 DQ31 129 M_A_DQ33 13 VSS4 VSS52
CLK_SCLK 202 SA1 DQ32 131 M_A_DQ32 14 VSS5
<9,14,19> CLK_SCLK CLK_SDATA 200 SCL DQ33 141 M_A_DQ39 19 VSS6 +0.75V_DDR_VTT
<9,14,19> CLK_SDATA SDA DQ34 143 M_A_DQ38 20 VSS7
116 DQ35 130 M_A_DQ36 25 VSS8
<4> M_A_ODT0 120 ODT0 DQ36 132 26 VSS9 203
M_A_DQ37
<4> M_A_ODT1 ODT1 DQ37 140 31 VSS10 VTT1 204
M_A_DQ35
11 DQ38 142 M_A_DQ34 32 VSS11 VTT2
28 DM0 DQ39 147 M_A_DQ41 37 VSS12 205
46 DM1 DQ40 149 M_A_DQ45 38 VSS13 GND 206
(204P)

63 DM2 DQ41 157 M_A_DQ46 43 VSS14 GND


136 DM3 DQ42 159 M_A_DQ47 VSS15
153 DM4 DQ43 146 M_A_DQ40
170 DM5 DQ44 148 M_A_DQ44
DM6 DQ45 DDR3-DIMM1_H=5.2_Reverse
187 158 M_A_DQ42
DM7 DQ46 160 M_A_DQ43
<4> M_A_DQSP[7:0] 12 DQ47 163
M_A_DQSP0 M_A_DQ48
M_A_DQSP1 29 DQS0 DQ48 165 M_A_DQ52
DQS1 DQ49 +SMDDR_VREF
M_A_DQSP2 47 175 M_A_DQ50
M_A_DQSP3 64 DQS2 DQ50 177 M_A_DQ55
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ53 +1.5VSUS +1.5VSUS
M_A_DQSP5 154 DQS4 DQ52 166 M_A_DQ49
M_A_DQSP6 171 DQS5 DQ53 174 M_A_DQ54
M_A_DQSP7 188 DQS6 DQ54 176 M_A_DQ51
<4> M_A_DQSN[7:0] 10 DQS7 DQ55 181
M_A_DQSN0 M_A_DQ57 R556 20110817 change to 1K/F_4 R601 20110817 change to 1K/F_4
M_A_DQSN1 27 DQS#0 DQ56 183 M_A_DQ60
DQS#1 DQ57 1K/F_4 1K/F_4
B M_A_DQSN2 45 191 M_A_DQ63 B
DQS#2 DQ58
M_A_DQSN3
M_A_DQSN4
62
135 DQS#3 DQ59
193
180
M_A_DQ58
M_A_DQ56
M1 solution R558 *0_6 +SMDDR_VREF_DQ0 R607 *0_6 +SMDDR_VREF_DIMM_A
M_A_DQSN5 152 DQS#4 DQ60 182 M_A_DQ61
M_A_DQSN6 169 DQS#5 DQ61 192 M_A_DQ62
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ59 R600 C723
DQS#7 DQ63
1K/F_4 470p/X7R_4
SMDDR_VREF_DQ0_M3 1 3
DDR3-DIMM1_H=5.2_Reverse

Q36 R546 C601

2
CRV add *AP2302GN
Place these Caps near So-Dimm0. 1K/F_4 470p/X7R_4

<4,14> DEEPS3_EC

+1.5VSUS

+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM_A
C267
C638 C717 C720 C719 C248 C243 C640 C643
+

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 *150u/6.3V_3528 C600 C602 C721 C722
SA1 SA0
.1u/16V_4 2.2u/6.3V_6 .1u/16V_4 2.2u/6.3V_6
CHA0 0 0
A A
CHA1 0 1
+3V +0.75V_DDR_VTT
CHB0 1 0
C731 C736 C323 C324 C312 C317 C318
Quanta Computer Inc.
CHB1 1 1
2.2u/6.3V_6 .1u/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 *10u/6.3V_6 PROJECT : Z09
Size Document Number Rev
3A
DDRIII SO-DIMM-0
Date: Monday, April 09, 2012 Sheet 13 of 40
5 4 3 2 1

www.teknisi-indonesia.com
1 2 3 4 5 6 7 8

<DDR> BYTE0_0-7 BYTE4_32-39 BYTE6_48-55


14
<4> M_B_DQSP[7:0]
<4> M_B_DQSN[7:0]
<4> M_B_DQ[63:0]
BYTE2_16-23
BYTE1_8-15 BYTE5_40-47 BYTE7_56-63
U30 U31 BYTE3_24-31 U32 U35

+SMDDR_VREF_DIMM M8 E3 M_B_DQ3 +SMDDR_VREF_DIMM M8 E3 M_B_DQ23 +SMDDR_VREF_DIMM M8 E3 M_B_DQ38 +SMDDR_VREF_DIMM M8 E3 M_B_DQ54


R587 *M3@0_6 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ2 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ18 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ35 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ50
<6> SMDDR_VREF_DQ1_M3 VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1
F2 M_B_DQ7 F2 M_B_DQ19 F2 M_B_DQ34 F2 M_B_DQ55
<4> M_B_A[15:0] DQL2 DQL2 DQL2 DQL2
M_B_A0 N3 F8 M_B_DQ6 M_B_A0 N3 F8 M_B_DQ22 M_B_A0 N3 F8 M_B_DQ39 M_B_A0 N3 F8 M_B_DQ51
M_B_A1 P7 A0 DQL3 H3 M_B_DQ5 M_B_A1 P7 A0 DQL3 H3 M_B_DQ21 M_B_A1 P7 A0 DQL3 H3 M_B_DQ33 M_B_A1 P7 A0 DQL3 H3 M_B_DQ49
M_B_A2 P3 A1 DQL4 H8 M_B_DQ4 M_B_A2 P3 A1 DQL4 H8 M_B_DQ16 M_B_A2 P3 A1 DQL4 H8 M_B_DQ37 M_B_A2 P3 A1 DQL4 H8 M_B_DQ48
M_B_A3 N2 A2 DQL5 G2 M_B_DQ1 M_B_A3 N2 A2 DQL5 G2 M_B_DQ20 M_B_A3 N2 A2 DQL5 G2 M_B_DQ32 M_B_A3 N2 A2 DQL5 G2 M_B_DQ53
M_B_A4 P8 A3 DQL6 H7 M_B_DQ0 M_B_A4 P8 A3 DQL6 H7 M_B_DQ17 M_B_A4 P8 A3 DQL6 H7 M_B_DQ36 M_B_A4 P8 A3 DQL6 H7 M_B_DQ52
M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7
A M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 A
M_B_A7 R2 A6 D7 M_B_DQ12 M_B_A7 R2 A6 D7 M_B_DQ31 M_B_A7 R2 A6 D7 M_B_DQ42 M_B_A7 R2 A6 D7 M_B_DQ59
SO-DIMMB SPD Address is 0XA4
M_B_A8 T8 A7 DQU0 C3 M_B_DQ15 M_B_A8 T8 A7 DQU0 C3 M_B_DQ28 M_B_A8 T8 A7 DQU0 C3 M_B_DQ44 M_B_A8 T8 A7 DQU0 C3 M_B_DQ61
SO-DIMMB TS Address is 0X34 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
M_B_A9 R3 C8 M_B_DQ13 M_B_A9 R3 C8 M_B_DQ30 M_B_A9 R3 C8 M_B_DQ47 M_B_A9 R3 C8 M_B_DQ62
M_B_A10 L7 A9 DQU2 C2 M_B_DQ14 M_B_A10 L7 A9 DQU2 C2 M_B_DQ25 M_B_A10 L7 A9 DQU2 C2 M_B_DQ45 M_B_A10 L7 A9 DQU2 C2 M_B_DQ57
M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ10 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ27 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ46 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ58
M_B_A12 N7 A11 DQU4 A2 M_B_DQ9 M_B_A12 N7 A11 DQU4 A2 M_B_DQ29 M_B_A12 N7 A11 DQU4 A2 M_B_DQ41 M_B_A12 N7 A11 DQU4 A2 M_B_DQ56
M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ11 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ26 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ43 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ63
M_B_A14 T7 A13 DQU6 A3 M_B_DQ8 M_B_A14 T7 A13 DQU6 A3 M_B_DQ24 M_B_A14 T7 A13 DQU6 A3 M_B_DQ40 M_B_A14 T7 A13 DQU6 A3 M_B_DQ60
M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7
A15 +1.5VSUS A15 +1.5VSUS A15 +1.5VSUS A15 +1.5VSUS

M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2


<4> M_B_BS#0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
N8 D9 M_B_BS#1 N8 D9 M_B_BS#1 N8 D9 M_B_BS#1 N8 D9
<4> M_B_BS#1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7
<4> M_B_BS#2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9
<4> M_B_CLK0 CK VDD#N9 CK VDD#N9 CK VDD#N9 CK VDD#N9
K7 R1 M_B_CLK0# K7 R1 M_B_CLK0# K7 R1 M_B_CLK0# K7 R1
<4> M_B_CLK0# CK VDD#R1 CK VDD#R1 CK VDD#R1 CK VDD#R1
K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9
<4> M_B_CKE0 CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS

K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1


<4> M_B_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 M_B_CS#0 L2 A8 M_B_CS#0 L2 A8 M_B_CS#0 L2 A8
<4> M_B_CS#0 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8
J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1
<4> M_B_RAS# RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 M_B_CAS# K3 C9 M_B_CAS# K3 C9 M_B_CAS# K3 C9
<4> M_B_CAS# CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2
<4> M_B_WE# WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_B_DQSP0 F3 VDDQ#F1 H2 M_B_DQSP2 F3 VDDQ#F1 H2 M_B_DQSP4 F3 VDDQ#F1 H2 M_B_DQSP6 F3 VDDQ#F1 H2
M_B_DQSP1 C7 DQSL VDDQ#H2 H9 M_B_DQSP3 C7 DQSL VDDQ#H2 H9 M_B_DQSP5 C7 DQSL VDDQ#H2 H9 M_B_DQSP7 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9

E7 A9 E7 A9 E7 A9 E7 A9
B DML VSS#A9 DML VSS#A9 DML VSS#A9 DML VSS#A9 B
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_B_DQSN0 G3 VSS#G8 J2 M_B_DQSN2 G3 VSS#G8 J2 M_B_DQSN4 G3 VSS#G8 J2 M_B_DQSN6 G3 VSS#G8 J2
M_B_DQSN1 B7 DQSL VSS#J2 J8 M_B_DQSN3 B7 DQSL VSS#J2 J8 M_B_DQSN5 B7 DQSL VSS#J2 J8 M_B_DQSN7 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9
<4,13> DDR3_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_B_ZQ1 L8 VSS#T1 T9 M_B_ZQ2 L8 VSS#T1 T9 M_B_ZQ3 L8 VSS#T1 T9 M_B_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
B1 B1 B1 B1
Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1
2

2
B9 B9 B9 B9
R185 VSSQ#B9 D1 R198 VSSQ#B9 D1 R216 VSSQ#B9 D1 R235 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240/F_4 240/F_4 240/F_4 240/F_4
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
M_B_CLK0 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
1

1
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
C301 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
1.6P/50V_4 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
M_B_CLK0# 100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
RAM _DDR3 RAM _DDR3 RAM _DDR3 RAM _DDR3
R543 R544
30/F_4 30/F_4

SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM

C593 +SMDDR_VREF_DIMM SMDDR_VREF_DQ1


C 0.1u/10V_4 C

C202 C203 C233 C280 C313 C314 C279


C175 C262 C296 C169 C258 C293 C209 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4

Place these Caps near Memory Down


+1.5VSUS +1.5VSUS
+1.5VSUS
+1.5VSUS
+1.5VSUS

C196 C198 C191 C194 C188 C187 C189 C195 C167 C171 C165 C173 C174 C179 C172 C166
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C193 C199 C168 C170 C176 R200 +SMDDR_VREF_DIMM R585
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 change to 1K/F_4 +SMDDR_VREF
1K/F_4 1K/F_4
+SMDDR_VREF

+1.5VSUS +1.5VSUS +SMDDR_VREF_DIMM R201 *0_6 SMDDR_VREF_DQ1_M3 1 3 SMDDR_VREF_DQ1 R586 *0_6


+1.5VSUS

R199 Q40 R584

2
1K/F_4 C211 REV:B Add *AP2302GN 1K/F_4 C234
C223 C229 C227 C222 C220 C221 C226 C228 C206 C207 C216 C212 C214 C208 C218 C213 0.1u/10V_4 0.1u/10V_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C210 C205 C217 C224 C230
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 <4,13> DEEPS3_EC

+1.5VSUS
+1.5VSUS +1.5VSUS

4/27 add
201201118 Unstuff U34 and C732
C271 C276 C270 C274 C275 C268 C269 C273 +3V
D D
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C255 C263 C260 C259 C261 C257 C256 C265 C254 C264 C266 C272 C277
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 U34
CLK_SCLK 6 1
<9,13,19> CLK_SCLK SCL A0
+1.5VSUS CLK_SDATA 5 2
<9,13,19> CLK_SDATA SDA A1 3
A2
+1.5VSUS +1.5VSUS 7 8 C732
WP VCC 4
GND *0.1u/10V_4
C303 C304 C309 C306 C308 C307 C302 C305
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C679 *M24C02-WMN6TP Quanta Computer Inc.

+
C300 C294 C291 C289 C295 C297 C290 C298 C299 C286 C288 C287 C310 address:A2
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 *150u/6.3V_3528
PROJECT : Z09
Size Document Number Rev
WP =1 : WRITE DISABLE 3A
DDR3 MEMORY DOWN
Date: Monday, April 09, 2012 Sheet 14 of 40
1 2 3 4 5 6 7 8

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5 4 3 2 1

Lid Switch (Hall sensor) eDP 7/28 modify

+3VPCU
25mil

EDP_AUX C33 0.1U/10V_4 EDP_AUX_C


<2> EDP_AUX
EDP_AUX# C34 0.1U/10V_4 EDP_AUX#_C
<2> EDP_AUX#
D2 *5.5V/25V/410P_4 25mil EDP_TX0 C42 0.1U/10V_4 EDP_TX0_C
D <2> EDP_TX0 D
1 2 EDP_TX0# C41 0.1U/10V_4 EDP_TX0#_C
<2> EDP_TX0#

C9 0.1u/10V_4_X7R
R19
1

*100K_4

2 LID#
INT_LVDS_DIGON
<7> INT_LVDS_DIGON
2

INT_LVDS_BLON
<7> INT_LVDS_BLON
D4
3

HE1 *5.5V/25V/410P_4
EM-6781-T3
1

R32 *0_4 LVDS_BRIGHT


<24> CONTRAST

R25 0_4
<7> INT_LVDS_BRIGHT
PT3661-BB : AL003661003

+3V

R52 *100K_4 EDP_AUX_C R45 *100K_4


R61 *100K_4 EDP_AUX#_C R65 *100K_4

C C

Penal SPEC: LCD CONNECTOR LCD Power


Iout:78~79.5mA +3V
Vout:32~34V
+3V

LED Driver-IC C26 C22

0.1u/10V_4_X7R C17 U2
1000p/50V_4
1U/6.3V_4 6 1 LCDVCC
IN OUT
VIN 4 2
IN GND C25 C21
INT_LVDS_DIGON 3 5 20111118 Remove C21/C12. C29
ON/OFF GND 0.1u/10V_4 .01u/25V_4 2.2U/6.3V_6
20120222 del 0 ohm R299. 20111122 change to 10u 1A inductor for FAE suggest.
20111121 change to 10u 0.1A indecator. 40V, 2A, 1mm(max) AAT4280-4
L22 D9
10uH_1A DFLS240-7-F VOUT
2 1 R24

20120111 Change C407 to 4.7uf 50V 1206 size. VOUT


LVDS_BRIGHT R20 10K_4 LVDS_BRIGHT_R C407 20120222 del 0 ohm R315. 20120221 add CN7 pin33/34 to GND. 100K_4
20111024 If phas shift PWM mode replace R65 to 10K. 0.8A
4.7u/50V_1206 R324 LVDS
1M_4 30
C369 29 30 34
28 29 34
2.2U/25V_6 28
27 33
23

22

21

20

19

18

17

16

U22 FB1 26 27 33
FB2 25 26 32
PAD

PAD

PAD

VIN

NC

SW
PWM

FAULT

24 FB3 24 25 32
PAD 23 24 31
25 22 23 31

B
30
PAD
PAD
26
R334
CCD_PWR
21
20
22
21
Backlight Control B
GNDP 56K_4 +3V 20
C20 1u/6.3V_4 VDDIO 1 CCD +3V-current budget 0.2A 19
VDDIO 15 20111111 change to R423 to 56K. 18 19
BL_ON R21 1.2K_4 2 PGND 17 18 +3VPCU
EN TPS61187 14 LCDVCC R34 *SHORT_6 16 17
R23 620K/F_4 3 OVC 15 16
FSLCT 13 MODE 14 15
R26 45.3K_4 4 RFPWM/MODE 13 14 R275
ISET 12 FB1 USBP8-_R 12 13 *100K_4
R33 *10K_4 5 IFB1 CCD-USB USBP8+_R 11 12 +3V LID#
+3V FPO 11 LID# <24>
11 FB2 10
20111024 Reserve if Host need to know any IFB2 9 10
GND
IFB6

IFB5

IFB4

IFB3
PAD

PAD

PAD

fault trigger on backlight driver EDP_HPD 8 9


<2> EDP_HPD 8
7
EDP_AUX_C 6 7 R314
Vovc=[Rupper/Rdowm+1]*Vov_th LID#,EC intrnal PU
27

28

29

10

EDP_AUX#_C 5 6 R296
(Rupper=1M,Vov_th=1.95V) 5

1
4 10K_4
EDP_TX0_C 3 4 10K_4 D8
EDP_TX0#_C 2 3
2 BAS316
1
1 BL#
FB3

2
CN7
R FLCT F SW
20111013 Create LED D-IC BL_ON
833K 600KHz
R41 *SHORT_4 INT_LVDS_BLON

3
625K 800KHz Q16
USBP8+_R R284 2N7002DW
<9> USBP8+
USBP8-_R 2
<9> USBP8- EC_FPBACK# <24>
499K 1MHz 100K_4
Q17
R36 *SHORT_4 DTC144EUA

1
4

1
A A
VIN VOUT
R67 Select is from 210Hz~20KHz,866K~9.09K.
20111117 change mose footprint to dual type.

VDDIO R22 *0_4 MODE 20120111 Un-stuff C410 for LCD flacking
C393 C397 C406 issue, FAE suggestion.
*0.1u/50V_8 C410
4.7u/25V_8 1000p/50V_4 R341
9.09K_4 *0.033u/16V_4_X7R

20111024 Bypass CAP for FAE request.


Close to Pin1 Quanta Computer Inc.
20120116 change Bypass CAP to 50V.
20111024 Reserve Phase shift PWM mode cirucit, PROJECT : Z09
if R67 high impedance, bypassing capacitor is Size Document Number Rev
for improves noise sensitivit and not exceed 33pf. 3A
LVDS/CAMERA/LID
Date: Monday, April 09, 2012 Sheet 15 of 40
5 4 3 2 1

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5 4 3 2 1

HDMI from PCH


C354 0.1u/10V_4 INT_HDMITX0N
<7> INT_HDMITX0N_C
C353 0.1u/10V_4 INT_HDMITX0P
<7> INT_HDMITX0P_C
C350 0.1u/10V_4 INT_HDMITX2N
<7> INT_HDMITX2N_C
C349 0.1u/10V_4 INT_HDMITX2P
<7> INT_HDMITX2P_C
C352 0.1u/10V_4 INT_HDMITX1N
<7> INT_HDMITX1N_C
C351 0.1u/10V_4 INT_HDMITX1P
<7> INT_HDMITX1P_C
C356 0.1u/10V_4 INT_HDMICLK-
D <7> INT_HDMICLK-_C D
C355 0.1u/10V_4 INT_HDMICLK+
<7> INT_HDMICLK+_C

R7 R8 R1 R2 R3 R4 R5 R6
680_4 680_4 680_4 680_4
680_4 680_4 680_4 680_4

3
Q1
+3V 2

R294 2N7002D
*100K/F_4

1
20111118 change R747 to 100K.

I2C
C +5V C

MOS close to connector

2
D6
+3V +3V +3V RB501V-40
HDMI-detect

1
R310 R288 Q12
10K_4 2.2K_4 R260
<24> HDMI_HPD_EC#

2
BSN20 2.2K_4

+3V HDMI_DDCCLK_SW 1 3 HDMI_DDCCLK_MB


<7> HDMI_DDCCLK_SW
+5V
follow CRB 1.0 change to 2.2K

R292 R266 +5V


*10K_4 10K_4

2
HDMI_MB_HP
HDMI_HP <7>
D7
5

+3V +3V RB501V-40


Q10
2N7002DW

1
R289 Q13
2.2K_4 R261

2
BSN20 2.2K_4
4

B B
HDMI_DDCDATA_SW 1 3 HDMI_DDCDATA_MB
<7> HDMI_DDCDATA_SW
20111117 change mose footprint to dual type.
follow CRB 1.0 change to 2.2K

EMI
INT_HDMITX2P
HDMI connector
CN1
R254 *100/F_4 20
INT_HDMITX2P 1 SHELL1
INT_HDMITX2N 2 D2+
INT_HDMITX2N 3 D2 Shield
INT_HDMITX1P INT_HDMITX1P 4 D2-
5 D1+
R253 *100/F_4 INT_HDMITX1N 6 D1 Shield
INT_HDMITX0P 7 D1-
INT_HDMITX1N 8 D0+
INT_HDMITX0N 9 D0 Shield 23
INT_HDMITX0P INT_HDMICLK+ 10 D0- GND
11 CK+ 22
R255 *100/F_4 INT_HDMICLK- 12 CK Shield GND
+5V 13 CK-
INT_HDMITX0N 14 CE Remote
F1 HDMI_DDCCLK_MB 15 NC
A INT_HDMICLK+ KMC3S110RY D1 HDMI_DDCDATA_MB 16 DDC CLK A
2 1 HDMI_5V_R SSM22LLPT 17 DDC DATA
R256 *100/F_4 HDMI_5V 18 GND
19 +5V
INT_HDMICLK- C1 HDMI_MB_HP HP_DET_CN HP DET 21
R263 *SHORT_4 SHELL2
470p/X7R_4

R262
HDMI
Quanta Computer Inc.
20K_4

20110919 change to 20k. PROJECT : Z09


Size Document Number Rev
3A
HDMI (PS8101)
Date: Monday, April 09, 2012 Sheet 16 of 40
5 4 3 2 1

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5 4 3 2 1

Giga-LAN BCM57780

+3V_LAN
31
U10
15mil
+3V_LAN 42 25 BIASVDD L15 BLM18AG601SN1D_6
VDDO BIASVDDH C344 0.1u/10V_4_X7R
6
VAUX_12 VDDC
20110214 Add C622 and C621 for power noise. 15 14 XTALVDD L13 BLM18AG601SN1D_6
41 VDDC XTALVDDH C337 0.1u/10V_4_X7R
D D
L21 VDDC

VAUX_12
15mil AVDDL 27 30 AVDDH L20 BLM18AG601SN1D_6
C370 4.7U/6.3V_6 33 AVDDL AVDDH
BLM18AG601SN1D_6 C347
C622
0.1u/10V_4_X7R
4.7U/6.3V_6
39 AVDDL
AVDDL
BCM57780
7mm X 7mm AVDDH
36 C365
C357
0.1u/10V_4_X7R
0.1u/10V_4_X7R
48-Pin QFN C621 4.7U/6.3V_6
L16
15mil GPHY_PLLVDD 24 37
GPHY_PLLVDDL TRD3_N LAN_TRD3N <18>
C343 4.7U/6.3V_6 38
TRD3_P LAN_TRD3P <18>
BLM18AG601SN1D_6 C342 0.1u/10V_4_X7R
35
TRD2_N LAN_TRD2N <18>
L14 34
15mil PCIE_PLLVDD 18 TRD2_P LAN_TRD2P <18>
PCIE_PLLVDDL 31
TRD1_N LAN_TRD1N <18>
BLM18AG601SN1D_6 C335 4.7U/6.3V_6 32
TRD1_P LAN_TRD1P <18>
C341 0.1u/10V_4_X7R 21
PCIE_PLLVDDL 29
TRD0_N LAN_TRD0N <18>
28
TRD0_P LAN_TRD0P <18>

48 LAN_LINKLED#
LINKLED# LAN_LINKLED# <18>
47
SPD100LED# 46
SPD1000LED# 45 LAN_ACTLED#
TRAFFICLED# LAN_ACTLED# <18>
C340 0.1u/10V_4_X7R PCIE_RX3+_R 17
<9> PCIE_RX3+ PCIE_TXDP
C339 0.1u/10V_4_X7R PCIE_RX3-_R 16
<9> PCIE_RX3- PCIE_TXDN
22 5
<9> PCIE_TX3+ PCIE_RXDP MODE
23
<9> PCIE_TX3- PCIE_RXDN
PCIE_LAN_WAKE# 4
C <7> PCIE_LAN_WAKE# WAKE# C
2
<9,19,20,24,25> PLTRST# 20 PERST#
<9> CLK_PCIE_LOM PCIE_REFCLK_P
<9> CLK_PCIE_LOM# 19
PCIE_REFCLK_N
44 BCM_EEC
EECLK
20120201 Change CAP from 27P to 15P. 43 BCM_EED
R286 1K/F_4 VMA_PRES 40 EEDATA VAUX_12
+3V VMAIN_PRSNT
R267 4.7K_4 LOW_PWR 1
LOW_PWR
C334 15p/50V_4 R248 200_4 XTALO 11 L17 4.7uh
SR_LX 8 Don't route under Choke.
SR_VFB
4
3

XTALO 13
Y3 XTALI 12 XTALO 10
XTALI SR_VDDP +3V_LAN
25MHz-LAN 9
R250 1.24K/F_4 RDAC 26 SR_VDD C348 C387 C372 C345
RDAC 10u/6.3V_6
2
1

4.7U/6.3V_6 0.1u/10V_4_X7R 0.1u/10V_4_X7R


C336 15p/50V_4 XTALI
R264 4.7K_4 3 7
+3V_LAN CLK_REQ# NC

BCM_CLKREQ# 2111201 change C6108 power from +3V_S5 to +3V_LAN.


GND

BCM57780
49

B B

+3V_LAN
LAN POWER
EEPROM

2
+3V_LAN
REV:B Q18 R303
6/11 *DTC144EUA *4.7K_4
3 1 PCIE_LAN_WAKE#
<24> WAKE_SRC_2

R326 R306 R298 0_4


20111122 Remove Q44 and change plant to +3V_S5. *1K_4 1K_4
U21 20120305 Stuff R298.
BCM_EED 5 1
BCM_EEC 6 SDA A0 2
SCL A1 3 +3V_LAN
+3V_LAN 7 A2

R291 2.2/F_6 C373 4.7U/6.3V_6


R327 R307
*1K_4 4
WP
8
S5 IOAC
+3V_S5 1K_4 GND VCC +3V_S5
C362 0.1u/10V_4_X7R *AT24C02 C385

2
0.1u/10V_4_X7R
3 1 BCM_CLKREQ#
<9> CLK_PCIE_LAN_REQ#
A A
Q8
VAUX_12 20mil EEPROM Strapping 2N7002K

R251 *0_4
C374 4.7U/6.3V_6 EEPROM Type EECLK EEDATA
C358 0.1u/10V_4_X7R
24LC02 1 1
C338 0.1u/10V_4_X7R Quanta Computer Inc.
C359 0.1u/10V_4_X7R Internal 1 0 PROJECT : Z09
Size Document Number Rev
3A