Sei sulla pagina 1di 46

1 2 3 4 5 6 7 8

V07 BLOCK DIAGRAM


A
DDRIII-SODIMM1 DDRIII 1333/1600 MT/s
CPU A

H=4mm PAGE11 Sandy Bridge(ULV) 17W


BGA 1023 DC
DDRIII-SODIMM2 DDRIII 1333/1600 MT/s 2C GT2
H=4mm PAGE12 31 mm X 24 mm
PAGE 6~10

FDI LINK DMI LINK


2.7GT /s 5GT /s
HDMI CONN
INT HDMI
PAGE21

iGFX Interfaces
INT CRT
SATA0 6Gb /S CRT CONN PAGE23
B
SATA -HDD B

PAGE27 INT Single CHANNEL LVDS


LCD CONN
PAGE20
SATA1 6Gb /S Mobile Intel
m-SATA
Card Reader Fingerprint
PAGE28 Series 7 Chipset PAGE33
USB2.0 USB[10] USB[8]
USB3.0 Port W/P X1 USB3.0
USB3.0 Port x1 USB[12]
PAGE22 PCH IO Board PAGE24
Camera
USB3.0 USB2.0 PAGE20
IO Board USB3.0 Ports x1
HM77
PAGE24 Panther Point USB[4] USB[5]
SMBUS SATA1
3-axis Fall Sensor WLAN/BT WWAN/mSATA
PAGE26 PCB STACK UP
PAGE28 PAGE28
BGA 989 PCI-E PCIE[1] 10L UMA
C LPC 25 mm X 25 mm PCIE[5]
C
Keyboard Conn.
PAGE33 LAYER 1 : TOP
KBC IO Board
Touch Pad ITE 8518 LAN
LAYER 2 : GND
PAGE33
LAYER 3 : IN1
PAGE 13~19 IHDA
PAGE 31 LAYER 4 : GND
Hot key Board SPI 25MHz
LAYER 5 : IN2
25MHz 32.768KHz LAYER 6 : IN3
Hot key RJ45
PWM FAN SPI ROM SPI ROM Audio Codec LAYER 7 : VCC
&Thermal 8MB 8MB
PAGE29 PAGE35 PAGE32 PAGE32 PAGE25 LAYER 8 : IN4
LAYER 9 : GND
D LED Board LAYER 10: BOT D

LED Speaker Como Jack


Quanta Computer Inc.
PAGE24 PROJECT : V07
WWW.MANUALS.CLAN.SU
PAGE38 Size Document Number
BLOCK DIAGRAM
Rev
1A

Date: Monday, January 09, 2012 Sheet 1 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

202
+3.3V_SUS +3.3V_RUN
200
A0
JDIM1A

2.2K 2.2K 2.2K 2.2K 202


+3.3V_RUN
H14 SMBCLK WLAN_SCLK 200 JDIM2A A4
N-MOSFET
C9 SMBDATA WLAN_SDATA
N-MOSFET
+3.3V_SUS +3.3V_RUN
A
+3.3V_RUN A

PCH 2.2K
+3.3V_RUN
2.2K 2.2K 4
FALL SENSOR
C8 SML0CLK CODEC_SCLK 1 6
50
N-MOSFET LNG3DM
G12 SML0DATA CODEC_SDATA 2 TS3A225ERTER
N-MOSFET
+3.3V_SUS +3.3V_RUN

2.2K 2.2K
E14 SMB_CLK_ME1

M16 SMB_DATA_ME1

+3.3V_SUS

+3.3V_SUS
+3.3V_ALW

N-MOS

N-MOS
B B
2.2K 2.2K
116 SMBDAT1

115 SMBCLK1

+3.3V_ALW
Check!!
100
3

4 Battery
2.2K 2.2K
SIO 100 Function IC SMBus Address
110 SMBCLK0 9
JDIM1A A0
ITE8518E 111 SMBDAT0 8 Charger DDR3
JDIM2A A4
+3.3V_RUN
Thermal IC EMC1422 0101_111xb (2Eh)
Charge IC BQ24707RGRR 0b0001001x (0x12)
Battery Battery
2.2K 2.2K Fall Sensor LNG3DM
94 SMBCLK3 15
WLAN WLAN Module X
C C

95 SMBDAT3 14 THERMAL(EMC2112) 2Eh

MB
SCREW PAD 0704 Delet H1~H10, H12~H25
H5 H4
*H-T276X292B315X331D118X142P2 *H-TC276BC315D118P2 H17 H2 H11
For CPU Use
H-T276X292B315X331D118X142P2 H-TC276BC315D118P2 *H-C236D91P2 *H-C236D91P2 *H-C236D91P2
H-C236D91P2 H-C236D91P2 H-C236D91P2
CPU PCH GPU
H20
*H-C43D43N
1

H-C43D43N
1

1
H19 H10 H21
*H-C197D91P2 H-TC158I142BC102D102PT H15 *H-C43D43N
H-C197D91P2 H-TC158I142BC102D102PT H-TC158I142BC102D102PT H-C43D43N
H-TC158I142BC102D102PT H18
*H-C118D63P2
H-C118D63P2
0704 Modify footprint from
"INTEL-CPU-BRACKET" to "intel-cpu-bkt2"
1

1
1

D D
1

H12
*H-O114X95D114X95N
H14 H-O114X95D114X95N
H-TC158I142BC102D102PT H9
H-TC158I142BC102D102PT
H-TC158I142BC102D102PT
H-TC158I142BC102D102PT
1

H16 H7
H1 H-TC158I142BC102D102PT H-TC158I142BC102D102PT
1

*H-O114X95D114X95N H-TC158I142BC102D102PT H-TC158I142BC102D102PT


Quanta Computer Inc.
1

H-O114X95D114X95N

PROJECT : V07
1

Size Document Number Rev


1

1A
SMB/SCREW PAD
Date: Monday, January 09, 2012 Sheet 2 of 46

WWW.MANUALS.CLAN.SU
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

USB Master Port Assignment SATA Master Port Assignment PCIE Master Port Assignment
A A

USB0 External port#1 (USB3.0) SATA0 HDD PCIE 1 WLAN

External port#2 (USB3.0/eSATA/ SATA1 mSATA PCIE 2 WWAN (NC)


USB1
Power share/ debug port)
SATA2 NC PCIE 3 Card reader (NC)
USB2 External port#3 (USB3.0)
SATA3 ODD (NC) PCIE 4 NC
USB3 External port#4 (USB3.0) (NC)
SATA4 eSATA (NC) PCIE 5 LAN
USB4 MiniCard 1 (WLAN/BT/WiMAX)
SATA5 NC PCIE 6 Express card (NC)
USB5 MiniCard 2 (WWAN)
PCIE 7 NC
B B
USB6 X(FOR HM77)
PCIE 8 NC
USB7 X(FOR HM77)

USB8 Fingerprint

USB9 Touch panel (NC, for debug)

USB10 Card Reader

USB11 Express Card (NC)

USB12 Camera

C USB13 NC C

D D

Quanta Computer Inc.


PROJECT : R11
WWW.MANUALS.CLAN.SU Size Document Number
PORT ASSIGNMENT
Rev
1A

Date: Monday, January 09, 2012 Sheet 3 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

Adapter 65W
VER : 1A
Charger
D PWR_SRC D
BQ24707RGRR
Shapes:
Via:

Battery 4S1P

+3.3V_EN2 ALW_ON
SIO_SLP_S5# SIO_SLP_S3# VCCSA_EN +3.3V_RUN IMVP_VR_ON

TI
TI RichTek RichTek ON
TPS51125ARGER ISL95837HRZ-T
TPS51216RUKR LDO RT8241DGQW RT8240BGQW

+1.5V_SUS
+3.3V_ALW +5V_ALW +15V_ALW
+1.5V_SUS +0.75V_DDR_VTT +VCCSA_CORE +1.05V_PCH +VCC_CORE +VCC_iGFX_CORE
C
TDC: 3A TDC: 6.52A C

Shapes: Shapes: TDC: 7.9A TDC: 1A TDC: 4.2A TDC: 10.39A TDC: 33A TDC: 29A
Via: Via: Shapes: Shapes: Shapes: 168mil Shapes: 415.6mil Shapes: Shapes:
Via: Via: Via: 6 Via: 15 Via: Via:

SUS_ON SUS_ON RUN_ON RUN_ON SIO_SLP_S3#

Load Switch Load Switch Load Switch Load Switch Load Switch
FDC655BN FDC655BN TPCC8065-H FDC655BN AON7410

+3.3V_SUS +5V_SUS +5V_RUN +1.5V_RUN +1.5V_CPU


TDC: 0.1A TDC: 0.1A TDC: 2.415A TDC: 0.817A TDC: 5A
B
Shapes: Shapes: Shapes: Shapes: Shapes: B

Via: Via: Via: Via: Via:

RUN_ON 1.05V_PCH_PWRGD

Load Switch RichTek


FDC655BN RT8068AZQW

+3.3V_RUN +1.8V_RUN
TDC: 1.224A TDC: 0.921A
Shapes: Shapes:
Via: Via:

A A

Quanta Computer Inc.


PROJECT : V04
Size Document Number Rev
1A
Power Block Diagram
Date: Monday, January 09, 2012 Sheet 4 of 46
5 4 3 2 1

WWW.MANUALS.CLAN.SU
1 2 3 4 5 6 7 8

Battery Mode IMVP_VR_ON


+VCC_CORE

EN

22 HWG after 120ms ECPOWROK


+VCC_CORE
SWITCH 28
23
+5V_SUS +3.3V_SUS IMVP_PWRGD
A A
+3.3V_ALW
6 7 29
SYS_PWR_SW# EN SUS_ON EN AND
+3.3V_ALW 2 5 +5V_SUS 27 SVID
1 SWITCH +3.3V_SUS SYS_PWROK
SWITCH
30
SUS_ON after 20ms RSMRST#
SYS_PWR_SW#
+5V_ALW 8
SIO_PWRBTN#
ALW_ON

4
EN EC 9
+5V_ALW 3 SLP_S5# ECPOWROK
SWITCH
+5V_RUN SM_DRAMPWROK
10 AND
B
RUN_ON PCH PM_DRAM_PWRGD
25
B

+5V_RUN EN SLP_S3#
+3.3V_RUN
16 +3.3V_RUN 15 HWPG
12 24 CPU
SWITCH
+1.5V_SUS
17
EN
+1.05V_PCH HWPG
11 +1.5V_SUS UNCOREPWRGOOD
SWITCH 26
EN +O.75V_DDR_VTT
+CPU_VTT +1.05V_PCH PLTRST#
18 +CPU_VTT
EN
SWITCH POK
13 +0.75V 31
SWITCH
+1.8V_RUN
+1.5V_CPU
C C
EN
EN
19 +1.8V_RUN 14 +1.5V_CPU
SWITCH
POK SWITCH
+VCCSA_CORE

EN
20 +VCCSA
SWITCH
HWPG
POK

21

D D

Quanta Computer Inc.


PROJECT :
WWW.MANUALS.CLAN.SU Size Document Number
POWER SEQUENCE
Rev
1A

Date: Monday, January 09, 2012 Sheet 5 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

DP & PEG Compensation


Ivy Bridge Processor (RESERVED, CFG)
+1.05V_PCH

D PEG_ICOMPO 12mil eDP_COMP R2181


D
2 24.9/F_4
PEG_ICOMPI, PEG_RCOMPO 4mil,
U17A eDP_COMPIO and ICOMPO signals should
G3 PEG_COMP be shorted near balls and
PEG_ICOMPI
G1
DMI_TXN0 M2
PEG_ICOMPO
G4
routed within 500 mils
13 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
DMI_TXN1 P6
13 DMI_TXN1 DMI_RX#[1]
DMI_TXN2 P1
13 DMI_TXN2 DMI_RX#[2]
DMI_TXN3 P10 H22
13 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
PEG_RX#[1] J21
DMI_TXP0 N3 B22 +1.05V_PCH
13 DMI_TXP0 DMI_RX[0] PEG_RX#[2]
DMI_TXP1 P7 D21
13 DMI_TXP1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_TXP2 P3 A19
13 DMI_TXP2 DMI_RX[2] PEG_RX#[4]
DMI_TXP3 P11 D17
13 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6] B14
DMI_RXN0 K1 D13
13 DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
DMI_RXN1 M8 A11
13 DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
DMI_RXN2 N4 B10 PEG_COMP R72 1 2 24.9/F_4
13 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
DMI_RXN3 R2 G8
13 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
PEG_RX#[11] A8 PEG_ICOMPI and RCOMPO signals should
DMI_RXP0 K3 B6 be routed within 500 mils
13 DMI_RXP0 DMI_TX[0] PEG_RX#[12]
DMI_RXP1 M7 H8
13 DMI_RXP1 DMI_TX[1] PEG_RX#[13]
DMI_RXP2 P4 E5
13 DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_ICOMPO signals should
DMI_RXP3 T3 K7
13 DMI_RXP3 DMI_TX[3] PEG_RX#[15]
be routed within 500 mils
PEG_RX[0] K22
PEG_RX[1] K19
PEG_RX[2] C21
C FDI_TXN0 U7 D19 C
13 FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
FDI_TXN1 W11 C19
13 FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
FDI_TXN2 W1 D16
13 FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
FDI_TXN3 AA6 C13
13 FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
FDI_TXN4 W6 D12

PCI EXPRESS -- GRAPHICS


13 FDI_TXN4 FDI1_TX#[0] PEG_RX[7]
FDI_TXN5 V4 C11
13 FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
FDI_TXN6 Y2 C9
13 FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
FDI_TXN7 AC9 F8
13 FDI_TXN7 FDI1_TX#[3] PEG_RX[10]

Intel(R) FDI
PEG_RX[11] C8
PEG_RX[12] C5
FDI_TXP0 U6 H6
13 FDI_TXP0 FDI0_TX[0] PEG_RX[13]
FDI_TXP1 W10 F6
13 FDI_TXP1 FDI0_TX[1] PEG_RX[14]
FDI_TXP2 W3 K6
13 FDI_TXP2 FDI0_TX[2] PEG_RX[15]
FDI_TXP3 AA7
13 FDI_TXP3 FDI0_TX[3]
FDI_TXP4 W7 G22
13 FDI_TXP4 FDI1_TX[0] PEG_TX#[0]
FDI_TXP5 T4 C23
13 FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
FDI_TXP6 AA3 D23
13 FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
FDI_TXP7 AC8 F21
13 FDI_TXP7 FDI1_TX[3] PEG_TX#[3]
PEG_TX#[4] H19
FDI_FSYNC0 AA11 C17
13 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 AC12 K15
13 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
PEG_TX#[7] F17
FDI_INT U11 F14
13 FDI_INT FDI_INT PEG_TX#[8]
PEG_TX#[9] A15
FDI_LSYNC0 AA10 J14
13 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI_LSYNC1 AG8 H13
13 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
PEG_TX#[12] M10
PEG_TX#[13] F10
PEG_TX#[14] D9
B B
PEG_TX#[15] J4
AF3 eDP_COMPIO
eDP_ICOMPO 12mil eDP_COMP AD2 F22
eDP_ICOMPO PEG_TX[0]
AG11 eDP_HPD# PEG_TX[1] A23
eDP_COMPIO 4mil D24
PEG_TX[2]
Programing Disable eDP interface(BIOS) PEG_TX[3] E21
AG4 eDP_AUX# PEG_TX[4] G19
AF4 eDP_AUX PEG_TX[5] B18
PEG_TX[6] K17
eDP

PEG_TX[7] G17
AC3 eDP_TX#[0] PEG_TX[8] E14
AC4 eDP_TX#[1] PEG_TX[9] C15
AE11 eDP_TX#[2] PEG_TX[10] K13
AE7 eDP_TX#[3] PEG_TX[11] G13
PEG_TX[12] K10
AC1 eDP_TX[0] PEG_TX[13] G10
AA4 eDP_TX[1] PEG_TX[14] D8
AE10 eDP_TX[2] PEG_TX[15] K4
AE6 eDP_TX[3]

IC,IVB_2CBGA,0P7

A A

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Ivy Bridge 1/5
Rev
1A

Date: Monday, January 09, 2012 Sheet 6 of 46


5 4 3 2 1
5 4 3 2 1

Ivy Bridge Processor (CLK,MISC,JTAG)


U17B

J3 CLK_CPU_BCLKP
BCLK CLK_CPU_BCLKP 17
SNB_IVB# N.A at SNB EDS #27637 0.7v1 H2 CLK_CPU_BCLKN
BCLK# CLK_CPU_BCLKN 17

MISC

CLOCKS
H_SNB_IVB# F49
16 H_SNB_IVB# PROC_SELECT#
DPLL_REF_CLK AG3 CLK_DP_P_R R2161 2 1K_4
DPLL_REF_CLK# AG1 CLK_DP_N_R R2171 2 1K_4 +1.05V_PCH
D H_CPUDET# C57 D
31 H_CPUDET# PROC_DETECT#

CATERR# C49
TP26 CATERR#

THERMAL
PECI_EC R21 1 2 43_4 PECI_EC_R A48 AT30 CPU_DRAMRST#
31 PECI_EC PECI SM_DRAMRST#

DDR3
MISC
SM_RCOMP[0] BF44 SM_RCOMP_0 R110 1 2 140/F_4
IMVP7_PROCHOT# R2551 2 56_4 H_PROCHOT# C45 BE43 SM_RCOMP_1 R111 1 2 25.5/F_4
31,45,46 IMVP7_PROCHOT# PROCHOT# SM_RCOMP[1]
SM_RCOMP[2] BG43 SM_RCOMP_2 R112 1 2 200/F_4

Over 130 degree C will PM_THRMTRIP# D45 SM_RCOMP_0, SM_RCOMP_1 20mil / SM_RCOMP_2 15mil.
18 PM_THRMTRIP# THERMTRIP#
drive low
PRDY# N53
PREQ# N55

L56 XDP_TCLK
TCK XDP_TMS +1.05V_PCH
TMS L55

PWR MANAGEMENT
J58 XDP_TRST#
TRST#

JTAG & BPM


H_PM_SYNC C48 M60 XDP_TDI XDP_TMS R268 2 1 *51_4_NC
13 H_PM_SYNC PM_SYNC TDI
L59 XDP_TDO XDP_TDI R261 2 1 *51_4_NC
C TDO +3.3V_RUN XDP_TDO R262 *51_4_NC C
2 1
IMVP7_PROCHOT# R258 2 1 62_4
H_PW RGOOD B46
18 H_PW RGOOD UNCOREPWRGOOD
K58 XDP_DBRST# 1 2
10K_4 2 R259 DBR# R267 1K_4 XDP_TCLK R266 1 *51_4_NC
1 2
XDP_TRST# R263 1 2 *51_4_NC
SM_DRAMPW ROK BE45 G58
SM_DRAMPWROK BPM#[0]
BPM#[1] E55
BPM#[2] E59
1.1V BPM#[3] G55
G59
PLTRST# CPU_PLTRST#_R BPM#[4]
16,24,28,31 PLTRST# 2 1 D44 RESET# BPM#[5] H60
R254 1.5K/F_4 J59
BPM#[6]
BPM#[7] J61
1

R251
750/F_4
2

IC,IVB_2CBGA,0P7

Intel spec VinH min =VCCIO X 0.7 Boot S3 S3 RSM

B
+1.5V_CPU B

DRAM_PWRGD
100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
Follow #DG1.0 436735 P107
SM_DRAMPWROK DRAMRST# Routing Illustration
+1.5V_SUS

2
Follow #DG1.0 436735 P105
R22 near the SODIMMs R34 Q1
1K_4 2N7002W
DDR Power Gating Topology

1
DDR3_DRAMRST# 2 1 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
11,12 DDR3_DRAMRST#
R36 1K_4
+3.3V_SUS

1
+1.5V_CPU DDR_HVREF_RST_PCH
9,17 DDR_HVREF_RST_PCH
1

R42

1
R118 C178 4.99K/F_4
2

200/F_4 0.1U/16V_4 C17


2

2
R108 +3.3V_SUS 1 2 0.047U/10V_4

2
A A
200/F_4 R41 1K_4
2

U5
PM_DRAM_PW RGD 2
13 PM_DRAM_PW RGD
1

4 SM_DRAMPW ROK_R 1 2 SM_DRAMPW ROK


EC_PW ROK 1 R109 130/F_4
13,31 EC_PW ROK
74AHC1G09GW Quanta Computer Inc.
3

PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Ivy Bridge 2/5
Rev
1A

Date: Monday, January 09, 2012 Sheet 7 of 46


5 4 3 2 1
5 4 3 2 1

Ivy Bridge Processor (DDR3)


U17D
U17C
12 M_B_DQ[63..0]
D D
M_B_DQ0 AL4
11 M_A_DQ[63..0] M_A_DQ0 M_B_DQ1 SB_DQ[0] M_B_CLKP0
AG6 SA_DQ[0] AL1 SB_DQ[1] SB_CK[0] BA34 M_B_CLKP0 12
M_A_DQ1 AJ6 AU36 M_A_CLKP0 M_B_DQ2 AN3 AY34 M_B_CLKN0
SA_DQ[1] SA_CK[0] M_A_CLKP0 11 SB_DQ[2] SB_CK#[0] M_B_CLKN0 12
M_A_DQ2 AP11 AV36 M_A_CLKN0 M_B_DQ3 AR4 AR22 M_B_CKE0
SA_DQ[2] SA_CK#[0] M_A_CLKN0 11 SB_DQ[3] SB_CKE[0] M_B_CKE0 12
M_A_DQ3 AL6 AY26 M_A_CKE0 M_B_DQ4 AK4
SA_DQ[3] SA_CKE[0] M_A_CKE0 11 SB_DQ[4]
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ[4] M_B_DQ6 SB_DQ[5]
AJ8 SA_DQ[5] AN4 SB_DQ[6]
M_A_DQ6 AL8 M_B_DQ7 AR1
M_A_DQ7 SA_DQ[6] M_B_DQ8 SB_DQ[7]
AL7 SA_DQ[7] AU4 SB_DQ[8]
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36 M_B_CLKP1
SA_DQ[8] SB_DQ[9] SB_CK[1] M_B_CLKP1 12
M_A_DQ9 AP6 AT40 M_A_CLKP1 M_B_DQ10 AV4 BB36 M_B_CLKN1
SA_DQ[9] SA_CK[1] M_A_CLKP1 11 SB_DQ[10] SB_CK#[1] M_B_CLKN1 12
M_A_DQ10 AU6 AU40 M_A_CLKN1 M_B_DQ11 BA4 BF27 M_B_CKE1
SA_DQ[10] SA_CK#[1] M_A_CLKN1 11 SB_DQ[11] SB_CKE[1] M_B_CKE1 12
M_A_DQ11 AV9 BB26 M_A_CKE1 M_B_DQ12 AU3
SA_DQ[11] SA_CKE[1] M_A_CKE1 11 SB_DQ[12]
M_A_DQ12 AR6 M_B_DQ13 AR3
M_A_DQ13 SA_DQ[12] M_B_DQ14 SB_DQ[13]
AP8 SA_DQ[13] AY2 SB_DQ[14]
M_A_DQ14 AT13 M_B_DQ15 BA3
M_A_DQ15 SA_DQ[14] M_B_DQ16 SB_DQ[15]
AU13 SA_DQ[15] BE9 SB_DQ[16]
M_A_DQ16 BC7 M_B_DQ17 BD9 BE41 M_B_CS#0
SA_DQ[16] SB_DQ[17] SB_CS#[0] M_B_CS#0 12
M_A_DQ17 BB7 BB40 M_A_CS#0 M_B_DQ18 BD13 BE47 M_B_CS#1
SA_DQ[17] SA_CS#[0] M_A_CS#0 11 SB_DQ[18] SB_CS#[1] M_B_CS#1 12
M_A_DQ18 BA13 BC41 M_A_CS#1 M_B_DQ19 BF12
SA_DQ[18] SA_CS#[1] M_A_CS#1 11 SB_DQ[19]
M_A_DQ19 BB11 M_B_DQ20 BF8
M_A_DQ20 SA_DQ[19] M_B_DQ21 SB_DQ[20]
BA7 SA_DQ[20] BD10 SB_DQ[21]
M_A_DQ21 BA9 M_B_DQ22 BD14
M_A_DQ22 SA_DQ[21] M_B_DQ23 SB_DQ[22]
BB9 SA_DQ[22] BE13 SB_DQ[23]
M_A_DQ23 AY13 M_B_DQ24 BF16 AT43 M_B_ODT0
SA_DQ[23] SB_DQ[24] SB_ODT[0] M_B_ODT0 12
M_A_DQ24 AV14 AY40 M_A_ODT0 M_B_DQ25 BE17 BG47 M_B_ODT1
SA_DQ[24] SA_ODT[0] M_A_ODT0 11 SB_DQ[25] SB_ODT[1] M_B_ODT1 12
M_A_DQ25 AR14 BA41 M_A_ODT1 M_B_DQ26 BE18
SA_DQ[25] SA_ODT[1] M_A_ODT1 11 SB_DQ[26]
M_A_DQ26 AY17 M_B_DQ27 BE21
C M_A_DQ27 SA_DQ[26] M_B_DQ28 SB_DQ[27] C
AR19 SA_DQ[27] BE14 SB_DQ[28]
M_A_DQ28 BA14 M_B_DQ29 BG14
M_A_DQ29 SA_DQ[28] M_B_DQ30 SB_DQ[29]
AU14 SA_DQ[29] BG18 SB_DQ[30] M_B_DQSN[7..0] 12
M_A_DQ30 BB14 M_B_DQ31 BF19 AL3 M_B_DQSN0
M_A_DQ31 SA_DQ[30] M_A_DQSN0 M_A_DQSN[7..0] 11 M_B_DQ32 SB_DQ[31] SB_DQS#[0] M_B_DQSN1
BB17 SA_DQ[31] SA_DQS#[0] AL11 BD50 SB_DQ[32] SB_DQS#[1] AV3
M_A_DQ32 BA45 AR8 M_A_DQSN1 M_B_DQ33 BF48 BG11 M_B_DQSN2
M_A_DQ33 SA_DQ[32] SA_DQS#[1] M_A_DQSN2 M_B_DQ34 SB_DQ[33] SB_DQS#[2] M_B_DQSN3
AR43 SA_DQ[33] SA_DQS#[2] AV11 BD53 SB_DQ[34] SB_DQS#[3] BD17
M_A_DQ34 AW48 AT17 M_A_DQSN3 M_B_DQ35 BF52 BG51 M_B_DQSN4
M_A_DQ35 SA_DQ[34] SA_DQS#[3] M_A_DQSN4 M_B_DQ36 SB_DQ[35] SB_DQS#[4] M_B_DQSN5
BC48 SA_DQ[35] SA_DQS#[4] AV45 BD49 SB_DQ[36] SB_DQS#[5] BA59

DDR SYSTEM MEMORY B


M_A_DQ36 BC45 AY51 M_A_DQSN5 M_B_DQ37 BE49 AT60 M_B_DQSN6
SA_DQ[36] SA_DQS#[5] SB_DQ[37] SB_DQS#[6]
DDR SYSTEM MEMORY A

M_A_DQ37 AR45 AT55 M_A_DQSN6 M_B_DQ38 BD54 AK59 M_B_DQSN7


M_A_DQ38 SA_DQ[37] SA_DQS#[6] M_A_DQSN7 M_B_DQ39 SB_DQ[38] SB_DQS#[7]
AT48 SA_DQ[38] SA_DQS#[7] AK55 BE53 SB_DQ[39]
M_A_DQ39 AY48 M_B_DQ40 BF56
M_A_DQ40 SA_DQ[39] M_B_DQ41 SB_DQ[40]
BA49 SA_DQ[40] BE57 SB_DQ[41]
M_A_DQ41 AV49 M_B_DQ42 BC59
M_A_DQ42 SA_DQ[41] M_B_DQ43 SB_DQ[42]
BB51 SA_DQ[42] AY60 SB_DQ[43]
M_A_DQ43 AY53 M_B_DQ44 BE54
M_A_DQ44 SA_DQ[43] M_B_DQ45 SB_DQ[44]
BB49 SA_DQ[44] M_A_DQSP[7..0] 11 BG54 SB_DQ[45] M_B_DQSP[7..0] 12
M_A_DQ45 AU49 AJ11 M_A_DQSP0 M_B_DQ46 BA58 AM2 M_B_DQSP0
M_A_DQ46 SA_DQ[45] SA_DQS[0] M_A_DQSP1 M_B_DQ47 SB_DQ[46] SB_DQS[0] M_B_DQSP1
BA53 SA_DQ[46] SA_DQS[1] AR10 AW59 SB_DQ[47] SB_DQS[1] AV1
M_A_DQ47 BB55 AY11 M_A_DQSP2 M_B_DQ48 AW58 BE11 M_B_DQSP2
M_A_DQ48 SA_DQ[47] SA_DQS[2] M_A_DQSP3 M_B_DQ49 SB_DQ[48] SB_DQS[2] M_B_DQSP3
BA55 SA_DQ[48] SA_DQS[3] AU17 AU58 SB_DQ[49] SB_DQS[3] BD18
M_A_DQ49 AV56 AW45 M_A_DQSP4 M_B_DQ50 AN61 BE51 M_B_DQSP4
M_A_DQ50 SA_DQ[49] SA_DQS[4] M_A_DQSP5 M_B_DQ51 SB_DQ[50] SB_DQS[4] M_B_DQSP5
AP50 SA_DQ[50] SA_DQS[5] AV51 AN59 SB_DQ[51] SB_DQS[5] BA61
M_A_DQ51 AP53 AT56 M_A_DQSP6 M_B_DQ52 AU59 AR59 M_B_DQSP6
M_A_DQ52 SA_DQ[51] SA_DQS[6] M_A_DQSP7 M_B_DQ53 SB_DQ[52] SB_DQS[6] M_B_DQSP7
AV54 SA_DQ[52] SA_DQS[7] AK54 AU61 SB_DQ[53] SB_DQS[7] AK61
M_A_DQ53 AT54 M_B_DQ54 AN58
M_A_DQ54 SA_DQ[53] M_B_DQ55 SB_DQ[54]
AP56 SA_DQ[54] AR58 SB_DQ[55]
M_A_DQ55 AP52 M_B_DQ56 AK58
B M_A_DQ56 SA_DQ[55] M_B_DQ57 SB_DQ[56] B
AN57 SA_DQ[56] AL58 SB_DQ[57]
M_A_DQ57 AN53 M_B_DQ58 AG58
M_A_DQ58 SA_DQ[57] M_B_DQ59 SB_DQ[58]
AG56 SA_DQ[58] AG59 SB_DQ[59]
M_A_DQ59 AG53 M_B_DQ60 AM60
SA_DQ[59] SB_DQ[60] M_B_A[15..0] 12
M_A_DQ60 AN55 M_B_DQ61 AL59 BF32 M_B_A0
SA_DQ[60] M_A_A[15..0] 11 SB_DQ[61] SB_MA[0]
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ63 SB_DQ[62] SB_MA[1] M_B_A2
AG55 SA_DQ[62] SA_MA[1] BB34 AH60 SB_DQ[63] SB_MA[2] BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ[63] SA_MA[2] M_A_A3 SB_MA[3] M_B_A4
SA_MA[3] BD35 SB_MA[4] BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA[4] M_A_A5 SB_MA[5] M_B_A6
SA_MA[5] AU34 SB_MA[6] BG30
BB32 M_A_A6 M_B_BS0 BG39 BD29 M_B_A7
SA_MA[6] 12 M_B_BS0 SB_BS[0] SB_MA[7]
M_A_BS0 BD37 AT32 M_A_A7 M_B_BS1 BD42 BE30 M_B_A8
11 M_A_BS0 SA_BS[0] SA_MA[7] 12 M_B_BS1 SB_BS[1] SB_MA[8]
M_A_BS1 BF36 AY32 M_A_A8 M_B_BS2 AT22 BE28 M_B_A9
11 M_A_BS1 SA_BS[1] SA_MA[8] 12 M_B_BS2 SB_BS[2] SB_MA[9]
M_A_BS2 BA28 AV32 M_A_A9 BD43 M_B_A10
11 M_A_BS2 SA_BS[2] SA_MA[9] SB_MA[10]
BE37 M_A_A10 AT28 M_B_A11
SA_MA[10] M_A_A11 SB_MA[11] M_B_A12
SA_MA[11] BA30 SB_MA[12] AV28
BC30 M_A_A12 M_B_CAS# AV43 BD46 M_B_A13
SA_MA[12] 12 M_B_CAS# SB_CAS# SB_MA[13]
M_A_CAS# BE39 AW41 M_A_A13 M_B_RAS# BF40 AT26 M_B_A14
11 M_A_CAS# SA_CAS# SA_MA[13] 12 M_B_RAS# SB_RAS# SB_MA[14]
M_A_RAS# BD39 AY28 M_A_A14 M_B_W E# BD45 AU22 M_B_A15
11 M_A_RAS# SA_RAS# SA_MA[14] 12 M_B_W E# SB_WE# SB_MA[15]
M_A_W E# AT41 AU26 M_A_A15
11 M_A_W E# SA_WE# SA_MA[15]

IC,IVB_2CBGA,0P7
IC,IVB_2CBGA,0P7

A A

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Ivy Bridge 3/5
Rev
1A

Date: Monday, January 09, 2012 Sheet 8 of 46


5 4 3 2 1
5 4 3 2 1

Ivy Bridge Processor Ivy Bridge Processor (GRAPHIC POWER)


1.05V_PCH CPU VGT
CPU Core Power SNB: 8.5A
SNB: 29A U17G POWER CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
SNB: 33A U17F POWER IVY: 8.5A
10uF x12
IVY: 29A
10uF x 12
IVY: 33A AY43 +VDDR_REF_CPU +VDDR_REF_CPU
SM_VREF
10uF x 11 AA46

VREF
+1.05V_PCH +VCC_GFX_CORE VAXG[1]
+VCC_CORE AB47
1uF x15 VAXG[2] SMDDR_VREF_DQ0_M3_C
VCCIO[1] AF46 AB50 VAXG[3] SA_DIMM_VREFDQ BE7
AG48 AB51 BG7 SMDDR_VREF_DQ1_M3_C
VCCIO[3] C35 C43 C82 C85 C95 C34 VAXG[4] SB_DIMM_VREFDQ
VCCIO[4] AG50 AB52 VAXG[5]

2
C92 C130 C147 C90 A26 AG51 10U/6.3V_8 AB53
VCC[1] VCCIO[5] VAXG[6]

1
A29 AJ17 EC54 EC53 EC52 AB55
VCC[2] VCCIO[6] VAXG[7]
1

1
A31 AJ21 330P/50V_4 33P/50V_4 3.3P/50V_4 AB56 R58 R52

1
VCC[3] VCCIO[7] 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 VAXG[8] *1K_4_NC
A34 AJ25 AB58 *1K_4_NC

2
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 VCC[4] VCCIO[8] 10U/6.3V_8 10U/6.3V_8 VAXG[9]
A35 AJ43 AB59
2

1
VCC[5] VCCIO[9] VAXG[10]
A38 VCC[6] VCCIO[10] AJ47 AC61 VAXG[11]
D A39 AK50 C170 C176 C171 C169 AD47 D
VCC[7] VCCIO[11] VAXG[12]
A42 VCC[8] VCCIO[12] AK51 AD48 VAXG[13]

1
C26 VCC[9] VCCIO[13] AL14 AD50 VAXG[14]
C27 AL15 AD51 AJ28

- 1.5V RAILS
C91 C153 C122 C97 VCC[10] VCCIO[14] VAXG[15] VDDQ[1]
C32 AL16 AD52 AJ33

2
VCC[11] VCCIO[15] 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 VAXG[16] VDDQ[2]
C34 VCC[12] VCCIO[16] AL20 AD53 VAXG[17] VDDQ[3] AJ36
1

C37 VCC[13] VCCIO[17] AL22 AD55 VAXG[18] VDDQ[4] AJ40


C39 AL26 AD56 AL30
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 C42
VCC[14] VCCIO[18]
AL45 C172 C163 C162 C177 AD58
VAXG[19] VDDQ[5]
AL34
CPU MCH
2

VCC[15] VCCIO[19] VAXG[20] VDDQ[6]


D27 VCC[16] VCCIO[20] AL48 AD59 VAXG[21] VDDQ[7] AL38

1
D32 VCC[17] VCCIO[21] AM16
C98 C77 C83 C72 C174 C173
AE46 VAXG[22] VDDQ[8] AL42 SNB: 5A
D34 VCC[18] VCCIO[22] AM17 N45 VAXG[23] VDDQ[9] AM33
D37 AM21 P47 AM36 IVY: 5A

2
VCC[19] VCCIO[23] VAXG[24] VDDQ[10]

1
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
10uF x 6

PEG IO AND DDR IO


D39 VCC[20] VCCIO[24] AM43 P48 VAXG[25] VDDQ[11] AM40
D42 VCC[21] VCCIO[25] AM47 P50 VAXG[26] VDDQ[12] AN30
C152 C109 C141 E26 AN20 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 P51 AN34

2
VCC[22] VCCIO[26] 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 C188 C189 C190 C264 VAXG[27] VDDQ[13] C134 C93 C157 C158
E28 VCC[23] VCCIO[27] AN42 P52 VAXG[28] VDDQ[14] AN38 +1.5V_CPU
1

E32 AN45 P53 AR26

DDR3
VCC[24] VCCIO[28] VAXG[29] VDDQ[15]

1
E34 AN48 P55 AR28

GRAPHICS
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 VCC[25] VCCIO[29] VAXG[30] VDDQ[16]
E37 P56 AR30
2

VCC[26] VAXG[31] VDDQ[17] 10U/6.3V_6 10U/6.3V_6 *10U/6.3V_6_NC


*10U/6.3V_6_NC
E38 P61 AR32

2
VCC[27] VAXG[32] VDDQ[18]

CORE SUPPLY
F25 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 T48 AR34
VCC[28] VAXG[33] VDDQ[19]
F26 VCC[29] T58 VAXG[34] VDDQ[20] AR36
F28 VCC[30] T59 VAXG[35] VDDQ[21] AR40
F32 T61 AV41 C145 C132
C138 C149 C112 C150 VCC[31] VAXG[36] VDDQ[22]
F34 VCC[32] U46 VAXG[37] VDDQ[23] AW26

1
F37 VCC[33] VCCIO[30] AA14 V47 VAXG[38] VDDQ[24] BA40
1

F38 VCC[34] VCCIO[31] AA15 V48 VAXG[39] VDDQ[25] BB28


F42 AB17 V50 BG33 10U/6.3V_6 10U/6.3V_6

2
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 VCC[35] VCCIO[32] VAXG[40] VDDQ[26]
G42 AB20 V51
2

VCC[36] VCCIO[33] VAXG[41]


H25 VCC[37] VCCIO[34] AC13 V52 VAXG[42]
H26 VCC[38] VCCIO[35] AD16 V53 VAXG[43]
H28 VCC[39] VCCIO[36] AD18 V55 VAXG[44]
H29 VCC[40] VCCIO[37] AD21 V56 VAXG[45]
H32 VCC[41] VCCIO[38] AE14 V58 VAXG[46]
H34 VCC[42] VCCIO[39] AE15 V59 VAXG[47]
C116 C139 C140 C121 H35 AF16 W50
VCC[43] VCCIO[40] VAXG[48]
H37 VCC[44] VCCIO[41] AF18 W51 VAXG[49]
1

H38 VCC[45] VCCIO[42] AF20 W52 VAXG[50]


H40 VCC[46] VCCIO[43] AG15 W53 VAXG[51]
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 J25 AG16 W55
2

VCC[47] VCCIO[44] VAXG[52]


J26 VCC[48] VCCIO[45] AG17 W56 VAXG[53]
J28 VCC[49] VCCIO[46] AG20 W61 VAXG[54]
J29 VCC[50] VCCIO[47] AG21 Y48 VAXG[55]
C
J32 VCC[51] VCCIO[48] AJ14 Y61 VAXG[56] C
J34 VCC[52] VCCIO[49] AJ15
C114 C115 C94 C133 J35 VCC[53]
J37 VCC[54]
1

J38 +3.3V_RUN 2 1
VCC[55] +VCC_GFX_CORE
J40 100/F_4 R102
VCC[56]

QUIET RAILS
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 J42 AM28

SENSE
LINES
+1.5V_CPU
2

VCC[57] VCC_AXG_SENSE VCCDQ[1]


K26 VCC[58] VCCIO50 W16 45 VCC_AXG_SENSE F45 VAXG_SENSE VCCDQ[2] AN26

1
K27 W17 VSS_AXG_SENSE G45 C120 1 2 1U/6.3V_4
VCC[59] VCCIO51 45 VSS_AXG_SENSE VSSAXG_SENSE
K29 R222
VCC[60]
K32 VCC[61] 10K_4 2 1
K34 100/F_4 R105
C113 C135 C151 VCC[62]
K35

2
VCC[63]
K37

1.8V RAIL
VCC[64]
2

K39 VCC[66]
EC55 K42 BC22 1 2 H_VTTVID1 +1.8V_RUN C241 C242 C243 BB3
VCC[67] VCCIO_SEL H_VTTVID1 43 VCCPLL[1]
220P/50V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 L25 *0_4_NC R226 BC1
1

VCC[68] VCCPLL[2]
L28 BC4
VCC[69] CPU VCCPL VCCPLL[3]

1
L33 VCC[70]
L36 VCC[71] SNB: 1.2A *10U/6.3V_6_NC
1U/6.3V_4 1U/6.3V_4
L40

2
VCC[72] IVY: 1.2A R107 *51_4_NC
N26 VCC[73] VDDQ_SENSE BC43 2 1 +1.5V_CPU
10uF x 1 R106 *51_4_NC
QUIET
RAILS

N30 VCC[74] VCCPQE[1] AM25 +1.05V_PCH VSS_SENSE_VDDQ BA43 2 1

SENSE LINES
N34 VCC[75] VCCPQE[2] AN22
C175 1 1U/6.3V_4
1uF x 2
N38 VCC[76] 2 L17 VCCSA[1]
L21 VCCSA[2]
N16 VCCSA[3]
10uF x 3 N20 VCCSA[4]
N22 1 2

SA RAIL
+VCCSA_CORE VCCSA[5] +VCCSA_CORE
P17 R71 100/F_4
VCCSA[6]

1
P20 U10 VCCSA_SENSE
VCCSA[7] VCCSA_SENSE VCCSA_SENSE 44
A44 H_CPU_SVIDALRT# C84 C78 C88 R16
VIDALERT#
B43 VR_SVID_CLK CPU SA *10U/6.3V_6_NC
*10U/6.3V_6_NC 10U/6.3V_6 R18
VCCSA[8]

2
VIDSCLK VCCSA[9]
SVID

C44 VR_SVID_DATA SNB: 6A R21


VIDSOUT VCCSA[10]
U15

VCCSA VID
IVY: 6A VCCSA[11]
V16 VCCSA[12]
V17 D48 VCCSA_VID0
VCCSA[13] VCCSA_VID[0] VCCSA_VID0 44

lines
V18 D49 VCCSA_VID1
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 44
V21 VCCSA[15]
W20 VCCSA[16]

1 2 +VCC_CORE
F43 R98 100/F_4 VCCSENSE VCCSA_VID0 1 2
VCC_SENSE VCCSENSE 45
SENSE LINES

G43 VSSSENSE IC,IVB_2CBGA,0P7 R113 1K_4


VSS_SENSE VSSSENSE 45
B 1 2 VCCSA_VID1 1 2 +1.05V_PCH B
R95 100/F_4 R1141 2*1K_4_NC
R115 1K_4
1 2 +1.05V_PCH
AN16 R44 10/F_4 VCCIO_SENSE
VCCIO_SENSE VCCIO_SENSE 43
AN17 VSSIO_SENSE
VSS_SENSE_VCCIO VSSIO_SENSE 43
1 2
R45 10/F_4

IC,IVB_2CBGA,0P7
+5V_ALW +15V_ALW +1.5V_SUS +1.5V_CPU
5A
M3 VREF
S3 Power reduce

1
Q11
R99 AON7410
Q4 10K_4 R91 8 3
100K_4 7 2
SMDDR_VREF_DQ0_M3_C 1 3 SMDDR_VREF_DQ0_M3 6 1
SMDDR_VREF_DQ0_M3 11

2
PS_S3CNTRL 5
PS_S3CNTRL 11
*AP2302GN_NC
2

4
DDR_HVREF_RST_PCH
DDR_HVREF_RST_PCH 7,17
PS_S3CNTRL_S
2

6
Q14A Q14B

1
SMDDR_VREF_DQ1_M3_C 1 3 SMDDR_VREF_DQ1_M3 SIO_SLP_S3# 5 2
SMDDR_VREF_DQ1_M3 12 13,25,31,41 SIO_SLP_S3#
C144
*AP2302GN_NC DMN66D0LDW-7 DMN66D0LDW-7
Vgs=2.5V Rds=115m

2
Q2 *4700P/25V_4_NC

Take care Q3 Vgs(MAX)=2.5


+1.5V_CPU +VDDR_REF_CPU
+1.5V_SUS C86 1 2 0.1U/16V_4 +1.5V_CPU
C89 1 2 0.1U/16V_4
C96 1 2 0.1U/16V_4

2
C106 1 2 0.1U/16V_4
R101
1K/F_4
A A

1
2

1
R93 0.1U/16V_4
1K/F_4 C156
Place PU resistor close to CPU
Place PU resistor close to CPU

2
Layout note: need routing

1
+1.05V_PCH +1.05V_PCH

together and ALERT need SVID CLK SVID DATA SVID ALERT
1

between CLK and DATA


R94 R103
130/F_4 75/F_4 Quanta Computer Inc.
VR_SVID_CLK
VR_SVID_CLK 45
2

VR_SVID_DATA H_CPU_SVIDALRT# VR_SVID_ALERT#

WWW.MANUALS.CLAN.SU
1 2
VR_SVID_DATA 45 VR_SVID_ALERT# 45 PROJECT :V07
R104 43_4 Size Document Number Rev
1A
Ivy Bridge 4/5
Date: Monday, January 09, 2012 Sheet 9 of 46
5 4 3 2 1
5 4 3 2 1

Ivy Bridge Processor (GND) Ivy Bridge Processor (RESERVED, CFG)


U17H U17I
U17E

BG17 VSS[181] VSS[250] M4


A13 VSS[1] VSS[91] AM38 BG21 VSS[182] VSS[251] M58 B50 CFG[0] BCLK_ITP N59 TP31
A17 VSS[2] VSS[92] AM4 BG24 VSS[183] VSS[252] M6 C51 CFG[1] BCLK_ITP# N58 TP19
A21 AM42 BG28 N1 CFG2 B54
VSS[3] VSS[93] VSS[184] VSS[253] TP29 CFG[2]
A25 VSS[4] VSS[94] AM45 BG37 VSS[185] VSS[254] N17 TP28 D53 CFG[3]
A28 VSS[5] VSS[95] AM48 BG41 VSS[186] VSS[255] N21 TP25 A51 CFG[4] RSVD30 N42
D A33 VSS[6] VSS[96] AM58 BG45 VSS[187] VSS[256] N25 TP27 C53 CFG[5] RSVD31 L42 D
A37 VSS[7] VSS[97] AN1 BG49 VSS[188] VSS[257] N28 TP30 C55 CFG[6] RSVD32 L45
A40 VSS[8] VSS[98] AN21 BG53 VSS[189] VSS[258] N33 H49 CFG[7] RSVD33 L47
A45 VSS[9] VSS[99] AN25 BG9 VSS[190] VSS[259] N36 A55 CFG[8]
A49 VSS[10] VSS[100] AN28 C29 VSS[191] VSS[260] N40 H51 CFG[9]
A53 VSS[11] VSS[101] AN33 C35 VSS[192] VSS[261] N43 K49 CFG[10] RSVD34 M13
A9 VSS[12] VSS[102] AN36 C40 VSS[193] VSS[262] N47 K53 CFG[11] RSVD35 M14
AA1 VSS[13] VSS[103] AN40 D10 VSS[194] VSS[263] N48 F53 CFG[12] RSVD36 U14
AA13 VSS[14] VSS[104] AN43 D14 VSS[195] VSS[264] N51 G53 CFG[13] RSVD37 W14
AA50 VSS[15] VSS[105] AN47 D18 VSS[196] VSS[265] N52 L51 CFG[14] RSVD38 P13
AA51 VSS[16] VSS[106] AN50 D22 VSS[197] VSS[266] N56 F51 CFG[15]
AA52 VSS[17] VSS[107] AN54 D26 VSS[198] VSS[267] N61 D52 CFG[16]
AA53 VSS[18] VSS[108] AP10 D29 VSS[199] VSS[268] P14 L53 CFG[17] RSVD39 AT49
AA55 VSS[19] VSS[109] AP51 D35 VSS[200] VSS[269] P16 RSVD40 K24
AA56 VSS[20] VSS[110] AP55 D4 VSS[201] VSS[270] P18

RESERVED
AA8 VSS[21] VSS[111] AP7 D40 VSS[202] VSS[271] P21 TP15 H43 VCC_VAL_SENSE
AB16 AR13 D43 P58 K43 AH2
AB18
AB21
VSS[22]
VSS[23]
VSS[24]
VSS[112]
VSS[113]
VSS[114]
AR17
AR21
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
TP14 VSS_VAL_SENSE RSVD41
RSVD42
RSVD43
AG13
AM14
AB48 VSS[25] VSS[115] AR41 D54 VSS[206] VSS[275] R17 TP16 H45 VAXG_VAL_SENSE RSVD44 AM15
AB61 VSS[26] VSS[116] AR48 D58 VSS[207] VSS[276] R20 TP17 K45 VSSAXG_VAL_SENSE
AC10 VSS[27] VSS[117] AR61 D6 VSS[208] VSS[277] R4
AC14 VSS[28] VSS[118] AR7 E25 VSS[209] VSS[278] R46 RSVD45 N50
AC46 VSS[29] VSS[119] AT14 E29 VSS[210] VSS[279] T1 F48 VCC_DIE_SENSE
AC6 VSS[30] VSS[120] AT19 E3 VSS[211] VSS[280] T47 G48 RSVD47
AD17 VSS[31] VSS[121] AT36 E35 VSS[212] VSS[281] T50
AD20 VSS[32] VSS[122] AT4 E40 VSS[213] VSS[282] T51 H48 RSVD6
AD4 AT45 F13 T52 K48
C
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F15
F19
VSS[214]
VSS[215]
VSS[216]
VSS[283]
VSS[284]
VSS[285]
T53
T55
RSVD7
DC_TEST_A4
DC_TEST_C4
A4
C4 C
AE8 VSS[36] VSS[126] AU1 F29 VSS[217] VSS[286] T56 BA19 RSVD8 DC_TEST_D3 D3
AF1 VSS[37] VSS[127] AU11 F35 VSS[218] VSS[287] U13 AV19 RSVD9 DC_TEST_D1 D1
AF17 VSS[38] VSS[128] AU28 F40 VSS[219] VSS[288] U8 AT21 RSVD10 DC_TEST_A58 A58
AF21 VSS[39] VSS[129] AU32 F55 VSS[220] VSS[289] V20 BB21 RSVD11 DC_TEST_A59 A59
AF47 VSS[40] VSS[130] AU51 G51 VSS[221] VSS[290] V61 BB19 RSVD12 DC_TEST_C59 C59
AF48 VSS[41] VSS[131] AU7 G6 VSS[222] VSS[291] W13 AY21 RSVD13 DC_TEST_A61 A61
AF50 VSS[42] VSS[132] AV17 G61 VSS[223] VSS[292] W15 BA22 RSVD14 DC_TEST_C61 C61
AF51 VSS[43] VSS[133] AV21 H10 VSS[224] VSS[293] W18 AY22 RSVD15 DC_TEST_D61 D61
AF52 VSS[44] VSS[134] AV22 H14 VSS[225] VSS[294] W21 AU19 RSVD16 DC_TEST_BD61 BD61
AF53 VSS[45] VSS[135] AV34 H17 VSS[226] VSS[295] W46 AU21 RSVD17 DC_TEST_BE61 BE61
AF55 VSS[46] VSS[136] AV40 H21 VSS[227] VSS[296] W8 BD21 RSVD18 DC_TEST_BE59 BE59
AF56 VSS[47] VSS[137] AV48 H4 VSS[228] VSS[297] Y4 BD22 RSVD19 DC_TEST_BG61 BG61
AF58 VSS[48] VSS[138] AV55 H53 VSS[229] VSS[298] Y47 BD25 RSVD20 DC_TEST_BG59 BG59
AF59 VSS[49] VSS[139] AW13 H58 VSS[230] VSS[299] Y58 BD26 RSVD21 DC_TEST_BG58 BG58
AG10 VSS[50] VSS[140] AW43 J1 VSS[231] VSS[300] Y59 BG22 RSVD22 DC_TEST_BG4 BG4
AG14 VSS[51] VSS[141] AW61 J49 VSS[232] BE22 RSVD23 DC_TEST_BG3 BG3
AG18 VSS[52] VSS[142] AW7 J55 VSS[233] BG26 RSVD24 DC_TEST_BE3 BE3
AG47 VSS[53] VSS[143] AY14 K11 VSS[234] BE26 RSVD25 DC_TEST_BG1 BG1
AG52 VSS[54] VSS[144] AY19 K21 VSS[235] BF23 RSVD26 DC_TEST_BE1 BE1
AG61 VSS[55] VSS[145] AY30 K51 VSS[236] BE24 RSVD27 DC_TEST_BD1 BD1
AG7 VSS[56] VSS[146] AY36 K8 VSS[237] VSS_NCTF_1 A5
AH4 VSS[57] VSS[147] AY4 L16 VSS[238] VSS_NCTF_2 A57
AH58 VSS[58] VSS[148] AY41 L20 VSS[239] VSS_NCTF_3 BC61
AJ13 VSS[59] VSS[149] AY45 L22 VSS[240] VSS_NCTF_4 BD3
AJ16 AY49 L26 BD59 IC,IVB_2CBGA,0P7
VSS[60] VSS[150] VSS[241] VSS_NCTF_5
AJ20 AY55 L30 BE4
NCTF

VSS[61] VSS[151] VSS[242] VSS_NCTF_6


AJ22 VSS[62] VSS[152] AY58 L34 VSS[243] VSS_NCTF_7 BE58
AJ26 VSS[63] VSS[153] AY9 L38 VSS[244] VSS_NCTF_8 BG5
B B
AJ30 VSS[64] VSS[154] BA1 L43 VSS[245] VSS_NCTF_9 BG57
AJ34 VSS[65] VSS[155] BA11 L48 VSS[246] VSS_NCTF_10 C3
AJ38 VSS[66] VSS[156] BA17 L61 VSS[247] VSS_NCTF_11 C58
AJ42 VSS[67] VSS[157] BA21 M11 VSS[248] VSS_NCTF_12 D59
AJ45 VSS[68] VSS[158] BA26 M15 VSS[249] VSS_NCTF_13 E1
AJ48 VSS[69] VSS[159] BA32 VSS_NCTF_14 E61
AJ7 VSS[70] VSS[160] BA48
AK1 VSS[71] VSS[161] BA51
AK52 VSS[72] VSS[162] BB53
AL10 VSS[73] VSS[163] BC13
AL13 VSS[74] VSS[164] BC5
AL17 BC57 IC,IVB_2CBGA,0P7
VSS[75] VSS[165]
AL21 VSS[76] VSS[166] BD12
AL25 VSS[77] VSS[167] BD16
AL28 VSS[78] VSS[168] BD19
AL33 VSS[79] VSS[169] BD23
AL36 VSS[80] VSS[170] BD27
AL40 VSS[81] VSS[171] BD32
AL43 VSS[82] VSS[172] BD36
AL47 VSS[83] VSS[173] BD40
AL61 VSS[84] VSS[174] BD44
AM13 VSS[85] VSS[175] BD48
AM20 VSS[86] VSS[176] BD52
AM22 VSS[87] VSS[177] BD56
AM26 VSS[88] VSS[178] BD8
AM30 VSS[89] VSS[179] BE5
AM34 VSS[90] VSS[180] BG13

A A

IC,IVB_2CBGA,0P7

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Ivy Bridge 5/5
Rev
1A

Date: Monday, January 09, 2012 Sheet 10 of 46


5 4 3 2 1
1 2 3 4 5 6 7 8

+1.5V_SUS

8 M_A_A[15..0]
M_A_A0
M_A_A1
M_A_A2
98
97
96
JDIM2A

A0
A1
12
DQ0
DQ1
5
7
15
M_A_DQ0
M_A_DQ4
M_A_DQ3
M_A_DQ[63..0] 8
H=4mm,STD 75
76
JDIM2B

VDD1 VSS16
12
44
48
M_A_A3 A2 DQ2 M_A_DQ7 VDD2 VSS17
95 A3 DQ3 17 81 VDD3 VSS18 49
M_A_A4 92 4 M_A_DQ1 82 54
M_A_A5 A4 DQ4 M_A_DQ5 VDD4 VSS19
91 A5 DQ5 6 87 VDD5 VSS20 55
M_A_A6 90 16 M_A_DQ2 88 60
M_A_A7 A6 DQ6 M_A_DQ6 VDD6 VSS21
86 A7 DQ7 18 93 VDD7 VSS22 61
A M_A_A8 89 21 M_A_DQ13 94 65 A
M_A_A9 A8 DQ8 M_A_DQ9 VDD8 VSS23
85 A9 DQ9 23 99 VDD9 VSS24 66
M_A_A10 107 33 M_A_DQ10 100 71
M_A_A11 A10/AP DQ10 M_A_DQ14 VDD10 VSS25
84 A11 DQ11 35 105 VDD11 VSS26 72
M_A_A12 83 22 M_A_DQ12 106 127
A12/BC# DQ12 +3.3V_RUN VDD12 VSS27

PC2100 DDR3 SDRAM SO-DIMM


SO-DIMMA SPD Address is 0XA0 M_A_A13 119 24 M_A_DQ8 111 128
M_A_A14 A13 DQ13 M_A_DQ11 VDD13 VSS28
SO-DIMMA TS Address is 0X30 80 A14 DQ14 34 112 VDD14 VSS29 133
M_A_A15 78 36 M_A_DQ15 117 134
A15 DQ15 M_A_DQ20 VDD15 VSS30
DQ16 39 118 VDD16 VSS31 138

1
PC2100 DDR3 SDRAM SO-DIMM
M_A_BS0 109 41 M_A_DQ21 123 139
8 M_A_BS0 BA0 DQ17 VDD17 VSS32
M_A_BS1 108 51 M_A_DQ23 C212 124 144
8 M_A_BS1 BA1 DQ18 VDD18 VSS33
M_A_BS2 79 53 M_A_DQ19 0.1U/16V_4 145
8 M_A_BS2

2
M_A_CS#0 BA2 DQ19 M_A_DQ16 VSS34
8 M_A_CS#0 114 S0# DQ20 40 199 VDDSPD VSS35 150
M_A_CS#1 121 42 M_A_DQ17 151
8 M_A_CS#1 S1# DQ21 VSS36
M_A_CLKP0 101 50 M_A_DQ22 77 155
8 M_A_CLKP0 CK0 DQ22 NC1 VSS37
M_A_CLKN0 103 52 M_A_DQ18 122 156
8 M_A_CLKN0 CK0# DQ23 NC2 VSS38
M_A_CLKP1 102 57 M_A_DQ30 125 161
8 M_A_CLKP1 CK1 DQ24 NCTEST VSS39
M_A_CLKN1 104 59 M_A_DQ28 162
8 M_A_CLKN1 CK1# DQ25 VSS40
M_A_CKE0 73 67 M_A_DQ25 +3.3V_RUN R152 1 2 *10K_4_NC 198 167
8 M_A_CKE0 CKE0 DQ26 EVENT# VSS41
M_A_CKE1 74 69 M_A_DQ27 DDR3_DRAMRST# 30 168
8 M_A_CKE1 CKE1 DQ27 7,12 DDR3_DRAMRST# RESET# VSS42
M_A_CAS# 115 56 M_A_DQ29 172
8 M_A_CAS# CAS# DQ28 VSS43
M_A_RAS# 110 58 M_A_DQ24 173
8 M_A_RAS# RAS# DQ29 VSS44
M_A_W E# 113 68 M_A_DQ31 +SMDDR_VREF_DQ0 1 178
8 M_A_W E# WE# DQ30 VREF_DQ VSS45
R323 1 2 10K_4 DIMM0_SA0 197 70 M_A_DQ26 +SMDDR_VREF_DIMM0 126 179
R322 1 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ33 VREF_CA VSS46
2 201 SA1 DQ32 129 VSS47 184
W LAN_SCLK 202 131 M_A_DQ36 185
12,17,25,26 W LAN_SCLK W LAN_SDATA SCL DQ33 M_A_DQ38 VSS48
12,17,25,26 W LAN_SDATA 200 SDA DQ34 141 2 VSS1 VSS49 189
143 M_A_DQ34 3 190
M_A_ODT0 DQ35 M_A_DQ37 VSS2 VSS50
8 M_A_ODT0 116 ODT0 DQ36 130 8 VSS3 VSS51 195
B M_A_ODT1 M_A_DQ32 B

(204P)
8 M_A_ODT1 120 ODT1 DQ37 132 9 VSS4 VSS52 196
140 M_A_DQ35 13
DQ38 M_A_DQ39 VSS5
11 142 14
28
DM0 DQ39
147 M_A_DQ41 S3 Power reduce 19
VSS6
DM1 DQ40 M_A_DQ40 VSS7
46 DM2 DQ41 149 20 VSS8
M_A_DQ47
63
136
DM3
DM4
(204P) DQ42
DQ43
157
159 M_A_DQ42 +0.75V_DDR_VTT
25
26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
153 146 M_A_DQ44 31 204
DM5 DQ44 M_A_DQ45 VSS11 VTT2
170 DM6 DQ45 148 32 VSS12
187 158 M_A_DQ43 37
DM7 DQ46 M_A_DQ46 VSS13
8 M_A_DQSP[7..0] DQ47 160 38 VSS14

2
M_A_DQSP0 12 163 M_A_DQ49 R151 43

GND

GND
M_A_DQSP1 DQS0 DQ48 M_A_DQ53 22_4 VSS15
29 DQS1 DQ49 165
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ50
64 177

205

206
M_A_DQSP4 DQS3 DQ51 M_A_DQ48 SODIMM(204P,H4.0,STD)
137 164

1
M_A_DQSP5 DQS4 DQ52 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ51
M_A_DQSP7 DQS6 DQ54 M_A_DQ55
8 M_A_DQSN[7..0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ60 Q19
DQS#0 DQ56

3
M_A_DQSN1 27 183 M_A_DQ56
M_A_DQSN2 DQS#1 DQ57 M_A_DQ59 PS_S3CNTRL
45 DQS#2 DQ58 191 2 PS_S3CNTRL 9
M_A_DQSN3 62 193 M_A_DQ63
M_A_DQSN4 DQS#3 DQ59 M_A_DQ57
135 180

1
M_A_DQSN5 DQS#4 DQ60 M_A_DQ61 2N7002W
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ58
M_A_DQSN7 DQS#6 DQ62 M_A_DQ62
186 DQS#7 DQ63 194

C SODIMM(204P,H4.0,STD) C

Place these Caps near So-Dimm0.


+1.5V_SUS +0.75V_DDR_VTT
M1 VREF
C57 C128 C159 C137 C208
C142 +1.5V_SUS +1.5V_SUS
1

C107 C100 C127 C214 C211 C213 C202 +SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM0


47P/50V_447P/50V_4
2

2
0.1U/16V_4 0.1U/16V_4 1U/6.3V_4
2

10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 R11 R90


0.1U/16V_4 0.1U/16V_4 1U/6.3V_4 1K/F_4 1K/F_4
1

1
SMDDR_VREF_DQ0_M3 R14 1 2 *0_4_NC
9 SMDDR_VREF_DQ0_M3
+1.5V_SUS
1

1
C168 C164
M3 VREF
1

R13 C3 C8 R92 47P/50V_4


EC14 1 2 47P/50V_4 1K/F_4 47P/50V_4 1K/F_4

2
EC8 1 2 47P/50V_4
2

EC13 1 2 47P/50V_4
2

EC10 1 2 47P/50V_4 0.1U/16V_4 0.1U/16V_4


EC16 1 2 47P/50V_4

D D
Place these Caps near So-Dimm0.

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
DDR3 DIMM-0
Rev
1A

Date: Monday, January 09, 2012 Sheet 11 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

JDIM1A M_B_DQ[63..0] 8 +1.5V_SUS


8 M_B_A[15..0]
M_B_A0 98 5 M_B_DQ5
M_B_A1 A0 DQ0 M_B_DQ4
97 A1 DQ1 7 JDIM1B

H=4mm,STD
M_B_A2 96 15 M_B_DQ7
M_B_A3 A2 DQ2 M_B_DQ3
95 A3 DQ3 17 75 VDD1 VSS16 44
M_B_A4 92 4 M_B_DQ0 76 48
M_B_A5 A4 DQ4 M_B_DQ1 VDD2 VSS17
91 A5 DQ5 6 81 VDD3 VSS18 49
M_B_A6 90 16 M_B_DQ2 82 54
M_B_A7 A6 DQ6 M_B_DQ6 VDD4 VSS19
86 A7 DQ7 18 87 VDD5 VSS20 55
A M_B_A8 89 21 M_B_DQ8 88 60 A
M_B_A9 A8 DQ8 M_B_DQ10 VDD6 VSS21
85 A9 DQ9 23 93 VDD7 VSS22 61
M_B_A10 107 33 M_B_DQ14 94 65
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD8 VSS23
84 A11 DQ11 35 99 VDD9 VSS24 66
M_B_A12 83 22 M_B_DQ13 100 71
M_B_A13 A12/BC# DQ12 M_B_DQ9 VDD10 VSS25
119 A13 DQ13 24 105 VDD11 VSS26 72
M_B_A14 80 34 M_B_DQ15 +3.3V_RUN 106 127
A14 DQ14 VDD12 VSS27

PC2100 DDR3 SDRAM SO-DIMM


M_B_A15 78 36 M_B_DQ12 111 128
A15 DQ15 M_B_DQ21 VDD13 VSS28
DQ16 39 112 VDD14 VSS29 133

PC2100 DDR3 SDRAM SO-DIMM


M_B_BS0 109 41 M_B_DQ17 117 134
8 M_B_BS0 BA0 DQ17 VDD15 VSS30
M_B_BS1 108 51 M_B_DQ19 118 138
8 M_B_BS1 BA1 DQ18 VDD16 VSS31
M_B_BS2 79 53 M_B_DQ23 123 139
8 M_B_BS2 BA2 DQ19 VDD17 VSS32

1
M_B_CS#0 114 40 M_B_DQ16 124 144
8 M_B_CS#0 S0# DQ20 VDD18 VSS33
M_B_CS#1 121 42 M_B_DQ20 C201 145
8 M_B_CS#1 S1# DQ21 VSS34
M_B_CLKP0 101 50 M_B_DQ18 0.1U/16V_4 199 150
8 M_B_CLKP0

2
M_B_CLKN0 CK0 DQ22 M_B_DQ22 VDDSPD VSS35
8 M_B_CLKN0 103 CK0# DQ23 52 VSS36 151
M_B_CLKP1 102 57 M_B_DQ25 77 155
8 M_B_CLKP1 CK1 DQ24 NC1 VSS37
M_B_CLKN1 104 59 M_B_DQ24 122 156
8 M_B_CLKN1 CK1# DQ25 NC2 VSS38
M_B_CKE0 73 67 M_B_DQ30 125 161
8 M_B_CKE0 CKE0 DQ26 NCTEST VSS39
M_B_CKE1 74 69 M_B_DQ31 162
8 M_B_CKE1 CKE1 DQ27 VSS40
M_B_CAS# 115 56 M_B_DQ29 +3.3V_RUN R153 1 2 *10K_4_NC 198 167
8 M_B_CAS# CAS# DQ28 EVENT# VSS41
M_B_RAS# 110 58 M_B_DQ28 DDR3_DRAMRST# 30 168
8 M_B_RAS# RAS# DQ29 7,11 DDR3_DRAMRST# RESET# VSS42
M_B_W E# 113 68 M_B_DQ26 172
8 M_B_W E# WE# DQ30 VSS43
R154 1 2 10K_4 DIMM1_SA0 197 70 M_B_DQ27 173
R155 1 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS44
2 201 SA1 DQ32 129 +SMDDR_VREF_DQ1 1 VREF_DQ VSS45 178
+3.3V_RUN W LAN_SCLK 202 131 M_B_DQ37 126 179
11,17,25,26 W LAN_SCLK SCL DQ33 +SMDDR_VREF_DIMM1 VREF_CA VSS46
W LAN_SDATA 200 141 M_B_DQ39 184
11,17,25,26 W LAN_SDATA SDA DQ34 M_B_DQ35 VSS47
DQ35 143 VSS48 185
M_B_ODT0 116 130 M_B_DQ36 2 189
8 M_B_ODT0 ODT0 DQ36 VSS1 VSS49
B M_B_ODT1 120 132 M_B_DQ33 3 190 B
8 M_B_ODT1 ODT1 DQ37 VSS2 VSS50
140 M_B_DQ38 8 195
DQ38 M_B_DQ34 VSS3 VSS51

(204P)
11 DM0 DQ39 142 9 VSS4 VSS52 196
SO-DIMMB SPD Address is 0XA4 28 147 M_B_DQ45 13
DM1 DQ40 M_B_DQ41 VSS5
SO-DIMMB TS Address is 0X34 46 DM2 DQ41 149 14 VSS6
M_B_DQ44

(204P)
63 DM3 DQ42 157 19 VSS7
136 159 M_B_DQ40 20
DM4 DQ43 M_B_DQ42 VSS8
153 DM5 DQ44 146 25 VSS9
170 148 M_B_DQ46 26 203 +0.75V_DDR_VTT
DM6 DQ45 M_B_DQ47 VSS10 VTT1
187 DM7 DQ46 158 31 VSS11 VTT2 204
160 M_B_DQ43 32
8 M_B_DQSP[7..0] M_B_DQSP0 DQ47 M_B_DQ48 VSS12
12 DQS0 DQ48 163 37 VSS13
M_B_DQSP1 29 165 M_B_DQ49 38
M_B_DQSP2 DQS1 DQ49 M_B_DQ50 VSS14
47 175 43

GND

GND
M_B_DQSP3 DQS2 DQ50 M_B_DQ51 VSS15
64 DQS3 DQ51 177
M_B_DQSP4 137 164 M_B_DQ53
M_B_DQSP5 DQS4 DQ52 M_B_DQ55
154 166

205

206
M_B_DQSP6 DQS5 DQ53 M_B_DQ54 SODIMM(204P,H4.0,STD)
171 DQS6 DQ54 174
M_B_DQSP7 188 176 M_B_DQ52
8 M_B_DQSN[7..0] M_B_DQSN0 DQS7 DQ55 M_B_DQ61
10 DQS#0 DQ56 181
M_B_DQSN1 27 183 M_B_DQ60
M_B_DQSN2 DQS#1 DQ57 M_B_DQ63
45 DQS#2 DQ58 191
M_B_DQSN3 62 193 M_B_DQ62
M_B_DQSN4 DQS#3 DQ59 M_B_DQ57
135 DQS#4 DQ60 180
M_B_DQSN5 152 182 M_B_DQ56
M_B_DQSN6 DQS#5 DQ61 M_B_DQ59
169 DQS#6 DQ62 192
M_B_DQSN7 186 194 M_B_DQ58
DQS#7 DQ63

C SODIMM(204P,H4.0,STD) C

M1 VREF
Place these Caps near So-Dimm1.
+1.5V_SUS +0.75V_DDR_VTT

C60 C124 C165 C58 C203


+1.5V_SUS +SMDDR_VREF_DQ1 +1.5V_SUS +SMDDR_VREF_DIMM1
1

C136 C101 C99 C131 C216 C204 C210 C215


47P/50V_447P/50V_4

2
0.1U/16V_4 0.1U/16V_4 1U/6.3V_4
2

10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 R9 R87


0.1U/16V_4 0.1U/16V_4 1U/6.3V_4 1K/F_4 1K/F_4

1
+1.5V_SUS SMDDR_VREF_DQ1_M3 R15 1 2 *0_4_NC
9 SMDDR_VREF_DQ1_M3
C166
2

2
C4

1
EC15 1 2 47P/50V_4 R10 C1 R88 C155
EC11 1 2 47P/50V_4 M3 REF 1K/F_4 47P/50V_4 1K/F_4 47P/50V_4
EC6 1 2 47P/50V_4

2
EC12 1 2 47P/50V_4
1

1
EC17 1 2 47P/50V_4 0.1U/16V_4 0.1U/16V_4

D Place these Caps near So-Dimm0. D

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
DDR3 DIMM-1
Rev
1A

Date: Monday, January 09, 2012 Sheet 12 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

Cougar Point/Panther Point (DMI,FDI,PM) PCH Pull-high/low(CLG)


U16C

+3.3V_SUS
DMI_RXN0 BC24 BJ14 FDI_TXN0
6 DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 6
DMI_RXN1 BE20 AY14 FDI_TXN1 RP27 10KX8
6 DMI_RXN1 DMI1RXN FDI_RXN1 FDI_TXN1 6
DMI_RXN2 BG18 BE14 FDI_TXN2 PM_RI# 1 2
6 DMI_RXN2 DMI2RXN FDI_RXN2 FDI_TXN2 6
DMI_RXN3 BG20 BH13 FDI_TXN3 PCIE_W AKE# 3 4
6 DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 6
BC12 FDI_TXN4 ME_SUS_PW R_ACK 5 6
FDI_RXN4 FDI_TXN4 6
DMI_RXP0 BE24 BJ12 FDI_TXN5 AC_PRESENT 7 8
6 DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 6
D DMI_RXP1 BC20 BG10 FDI_TXN6 D
6 DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 6
DMI_RXP2 BJ18 BG9 FDI_TXN7
6 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 6
DMI_RXP3 BJ20
6 DMI_RXP3 DMI3RXP
BG14 FDI_TXP0
FDI_RXP0 FDI_TXP0 6
DMI_TXN0 AW24 BB14 FDI_TXP1 PM_BATLOW # R39 1 2 10K_4
6 DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 6
DMI_TXN1 AW20 BF14 FDI_TXP2
6 DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 6
DMI_TXN2 BB18 BG13 FDI_TXP3
6 DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 6
DMI_TXN3 AV18 BE12 FDI_TXP4
6 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 6

DMI
FDI
BG12 FDI_TXP5 +3.3V_RUN
FDI_RXP5 FDI_TXP5 6
DMI_TXP0 AY24 BJ10 FDI_TXP6
6 DMI_TXP0 DMI0TXP FDI_RXP6 FDI_TXP6 6
DMI_TXP1 AY20 BH9 FDI_TXP7
6 DMI_TXP1 DMI1TXP FDI_RXP7 FDI_TXP7 6
DMI_TXP2 AY18 SYS_RESET# R313 1 2 10K_4
6 DMI_TXP2 DMI2TXP
DMI_TXP3 AU18 CLKRUN# R312 1 2 10K_4
6 DMI_TXP3 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT 6

DMI_ZCOMP, DMI_IRCOMP 4mil BJ24 AV12 FDI_FSYNC0


DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6

+1.05V_PCH R223 1 2 49.9/F_4 DMI_COMP BG25 BC10 FDI_FSYNC1


DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
RSMRST# R315 1 2 10K_4
R221 2 1 750/F_4 DMI2RBIAS BH21 AV14 FDI_LSYNC0 SYS_PW ROK R314 1 2 10K_4
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 6

DSWVRMEN A18 DSW VRMEN

System Power Management


ME_SUS_PW R_ACK C12 E22 RSMRST#
C SUSACK# DPWROK C

SYS_RESET# K3 B9 PCIE_W AKE#


SYS_RESET# WAKE#

SYS_PW ROK P12 +3V N3 CLKRUN#


SYS_PWROK CLKRUN# / GPIO32 CLKRUN# 31

EC_PW ROK L22 +3V_S5 G8


7,31 EC_PW ROK PWROK SUS_STAT# / GPIO61
+RTC_CELL
HW PG L10 +3V_S5 N14 SUSCLK
31,36 HW PG APWROK SUSCLK / GPIO62 TP7

2
TP6
PM_DRAM_PW RGD B13 +3V_S5 D10 SIO_SLP_S5# R214
7 PM_DRAM_PW RGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# 31
330K_4

RSMRST# C21 H4 SIO_SLP_S4#


31 RSMRST# SIO_SLP_S4# 31,41

1
RSMRST# SLP_S4# DSW VRMEN

ME_SUS_PW R_ACK K16 +3V_S5 F4 SIO_SLP_S3#


31 ME_SUS_PW R_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# 9,25,31,41

SIO_PW RBTN# E20 DSW G10 W/O support iAMT


31 SIO_PW RBTN# PWRBTN# SLP_A#

AC_PRESENT H20 DSW G16


31 AC_PRESENT ACPRESENT / GPIO31 SLP_SUS#
W/O support Deep Sx
On Die DSW VR Enable
B PM_BATLOW # H_PM_SYNC B
E10 BATLOW# / GPIO72 +3V_S5 PMSYNCH AP14 H_PM_SYNC 7
High = Enable (Default)
PM_RI# A10 RI# +3V_S5 SLP_LAN# / GPIO29 K14 SIO_SLP_LAN# T3 Low = Disable

CPT_PPT_Rev_0p5

+3.3V_SUS

C64
1

0.1U/16V_4
2
5

U2
2 IMVP_PW RGD 31,35,45
SYS_PW ROK 4
1 EC_PW ROK
A A
1

TC7SH08FU
3

R55
100K_4
2

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Panther Point 1/7
Rev
1A

Date: Monday, January 09, 2012 Sheet 13 of 46


5 4 3 2 1
5 4 3 2 1

Cougar Point/Panther Point (LVDS,DDI) Cougar Point/Panther Point (GND)


U16I U16H
H5 VSS[0]
AY4 VSS[159] VSS[259] H46
U16D AY42 K18 AA17 AK38
VSS[160] VSS[260] VSS[1] VSS[80]
AY46 VSS[161] VSS[261] K26 AA2 VSS[2] VSS[81] AK4
PANEL_BKEN J47 AP43 AY8 K39 AA3 AK42
31 PANEL_BKEN L_BKLTEN SDVO_TVCLKINN VSS[162] VSS[262] VSS[3] VSS[82]
ENVDD M45 AP45 B11 K46 AA33 AK46
20 ENVDD L_VDD_EN SDVO_TVCLKINP VSS[163] VSS[263] VSS[4] VSS[83]
D B15 VSS[164] VSS[264] K7 AA34 VSS[5] VSS[84] AK8 D
LCD_PW M P45 AM42 B19 L18 AB11 AL16
20 LCD_PW M L_BKLTCTL SDVO_STALLN VSS[165] VSS[265] VSS[6] VSS[85]
SDVO_STALLP AM40 B23 VSS[166] VSS[266] L2 AB14 VSS[7] VSS[86] AL17
LCD_DDCCLK T40 B27 L20 AB39 AL19
20 LCD_DDCCLK LCD_DDCDAT L_DDC_CLK VSS[167] VSS[267] VSS[8] VSS[87]
20 LCD_DDCDAT K47 L_DDC_DATA SDVO_INTN AP39 B31 VSS[168] VSS[268] L26 AB4 VSS[9] VSS[88] AL2
SDVO_INTP AP40 B35 VSS[169] VSS[269] L28 AB43 VSS[10] VSS[89] AL21
DIS_L_CTRL_CLK T45 B39 L36 AB5 AL23
DIS_L_CTRL_DATA P39 L_CTRL_CLK VSS[170] VSS[270] VSS[11] VSS[90]
L_CTRL_DATA B7 VSS[171] VSS[271] L48 AB7 VSS[12] VSS[91] AL26
F45 VSS[172] VSS[272] M12 AC19 VSS[13] VSS[92] AL27
R74 2 1 2.37K/F_4 LVDS_IBG AF37 P38 HDMI_SCL BB12 P16 AC2 AL31
LVDS_VBG LVD_IBG SDVO_CTRLCLK HDMI_SDA HDMI_SCL 21 VSS[173] VSS[273] VSS[14] VSS[93]
AF36 LVD_VBG SDVO_CTRLDATA M39 HDMI_SDA 21 BB16 VSS[174] VSS[274] M18 AC21 VSS[15] VSS[94] AL33
T7 BB20 M22 AC24 AL34
VSS[175] VSS[275] VSS[16] VSS[95]
AE48 LVD_VREFH BB22 VSS[176] VSS[276] M24 AC33 VSS[17] VSS[96] AL48

INT. HDMI
AE47 LVD_VREFL DDPB_AUXN AT49 BB24 VSS[177] VSS[277] M30 AC34 VSS[18] VSS[97] AM11
DDPB_AUXP AT47 BB28 VSS[178] VSS[278] M32 AC48 VSS[19] VSS[98] AM14
DDPB_HPD AT40 INT_HDMI_HPD INT_HDMI_HPD 21 BB30 VSS[179] VSS[279] M34 AD10 VSS[20] VSS[99] AM36
INT_TXLCLKOUTN AK39 BB38 M38 AD11 AM39
20 INT_TXLCLKOUTN LVDSA_CLK# VSS[180] VSS[280] VSS[21] VSS[100]

LVDS
INT_TXLCLKOUTP AK40 AV42 INT_HDMI_TXN2 BB4 M4 AD12 AM43
20 INT_TXLCLKOUTP LVDSA_CLK DDPB_0N INT_HDMI_TXN2 21 VSS[181] VSS[281] VSS[22] VSS[101]
DDPB_0P AV40 INT_HDMI_TXP2 INT_HDMI_TXP2 21 BB46 VSS[182] VSS[282] M42 AD13 VSS[23] VSS[102] AM45
INT_TXLOUTN0 AN48 AV45 INT_HDMI_TXN1 BC14 M46 AD19 AM46
20 INT_TXLOUTN0 LVDSA_DATA#0 DDPB_1N INT_HDMI_TXN1 21 VSS[183] VSS[283] VSS[24] VSS[103]
INT_TXLOUTN1 AM47 AV46 INT_HDMI_TXP1 BC18 M8 AD24 AM7
20 INT_TXLOUTN1 LVDSA_DATA#1 DDPB_1P INT_HDMI_TXP1 21 VSS[184] VSS[284] VSS[25] VSS[104]

Digital Display Interface


INT_TXLOUTN2 AK47 AU48 INT_HDMI_TXN0 BC2 N18 AD26 AN2
20 INT_TXLOUTN2 LVDSA_DATA#2 DDPB_2N INT_HDMI_TXN0 21 VSS[185] VSS[285] VSS[26] VSS[105]
AJ48 LVDSA_DATA#3 DDPB_2P AU47 INT_HDMI_TXP0 INT_HDMI_TXP0 21 BC22 VSS[186] VSS[286] P30 AD27 VSS[27] VSS[106] AN29
DDPB_3N AV47 INT_HDMI_TXN3 INT_HDMI_TXN3 21 BC26 VSS[187] VSS[287] N47 AD33 VSS[28] VSS[107] AN3
INT_TXLOUTP0 AN47 AV49 INT_HDMI_TXP3 BC32 P11 AD34 AN31
20 INT_TXLOUTP0 LVDSA_DATA0 DDPB_3P INT_HDMI_TXP3 21 VSS[188] VSS[288] VSS[29] VSS[108]
INT_TXLOUTP1 AM49 BC34 P18 AD36 AP12
20 INT_TXLOUTP1 LVDSA_DATA1 VSS[189] VSS[289] VSS[30] VSS[109]
INT_TXLOUTP2 AK49 BC36 T33 AD37 AP19
20 INT_TXLOUTP2 LVDSA_DATA2 VSS[190] VSS[290] VSS[31] VSS[110]
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 BC40 VSS[191] VSS[291] P40 AD38 VSS[32] VSS[111] AP28
DDPC_CTRLDATA P42 BC42 VSS[192] VSS[292] P43 AD39 VSS[33] VSS[112] AP30
C BC48 P47 AD4 AP32 C
VSS[193] VSS[293] VSS[34] VSS[113]
AF40 LVDSB_CLK# BD46 VSS[194] VSS[294] P7 AD40 VSS[35] VSS[114] AP38
AF39 LVDSB_CLK DDPC_AUXN AP47 BD5 VSS[195] VSS[295] R2 AD42 VSS[36] VSS[115] AP4
DDPC_AUXP AP49 BE22 VSS[196] VSS[296] R48 AD43 VSS[37] VSS[116] AP42
AH45 LVDSB_DATA#0 DDPC_HPD AT38 BE26 VSS[197] VSS[297] T12 AD45 VSS[38] VSS[117] AP46
AH47 LVDSB_DATA#1 BE40 VSS[198] VSS[298] T31 AD46 VSS[39] VSS[118] AP8
AF49 LVDSB_DATA#2 DDPC_0N AY47 BF10 VSS[199] VSS[299] T37 AD8 VSS[40] VSS[119] AR2
AF45 LVDSB_DATA#3 DDPC_0P AY49 BF12 VSS[200] VSS[300] T4 AE2 VSS[41] VSS[120] AR48
DDPC_1N AY43 BF16 VSS[201] VSS[301] W34 AE3 VSS[42] VSS[121] AT11
AH43 LVDSB_DATA0 DDPC_1P AY45 BF20 VSS[202] VSS[302] T46 AF10 VSS[43] VSS[122] AT13
AH49 LVDSB_DATA1 DDPC_2N BA47 BF22 VSS[203] VSS[303] T47 AF12 VSS[44] VSS[123] AT18
AF47 LVDSB_DATA2 DDPC_2P BA48 BF24 VSS[204] VSS[304] T8 AD14 VSS[45] VSS[124] AT22
AF43 LVDSB_DATA3 DDPC_3N BB47 BF26 VSS[205] VSS[305] V11 AD16 VSS[46] VSS[125] AT26
DDPC_3P BB49 BF28 VSS[206] VSS[306] V17 AF16 VSS[47] VSS[126] AT28
BD3 VSS[207] VSS[307] V26 AF19 VSS[48] VSS[127] AT30
BF30 VSS[208] VSS[308] V27 AF24 VSS[49] VSS[128] AT32
INT_CRT_BLU N48 M43 BF38 V29 AF26 AT34
23 INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK VSS[209] VSS[309] VSS[50] VSS[129]
INT_CRT_GRE P49 M36 BF40 V31 AF27 AT39
23 INT_CRT_GRE CRT_GREEN DDPD_CTRLDATA VSS[210] VSS[310] VSS[51] VSS[130]
INT_CRT_RED T49 BF8 V36 AF29 AT42
23 INT_CRT_RED CRT_RED VSS[211] VSS[311] VSS[52] VSS[131]
BG17 VSS[212] VSS[312] V39 AF31 VSS[53] VSS[132] AT46
DDPD_AUXN AT45 BG21 VSS[213] VSS[313] V43 AF38 VSS[54] VSS[133] AT7
CRT

INT_DDCCLK T39 AT43 BG33 V7 AF4 AU24


23 INT_DDCCLK INT_DDCDAT CRT_DDC_CLK DDPD_AUXP VSS[214] VSS[314] VSS[55] VSS[134]
23 INT_DDCDAT M40 CRT_DDC_DATA DDPD_HPD BH41 BG44 VSS[215] VSS[315] W17 AF42 VSS[56] VSS[135] AU30
BG8 VSS[216] VSS[316] W19 AF46 VSS[57] VSS[136] AV16
DDPD_0N BB43 BH11 VSS[217] VSS[317] W2 AF5 VSS[58] VSS[137] AV20
INT_CRT_HSYNC M47 BB45 BH15 W27 AF7 AV24
23 INT_CRT_HSYNC CRT_HSYNC DDPD_0P VSS[218] VSS[318] VSS[59] VSS[138]
INT_CRT_VSYNC M49 BF44 BH17 W48 AF8 AV30
23 INT_CRT_VSYNC CRT_VSYNC DDPD_1N VSS[219] VSS[319] VSS[60] VSS[139]
DDPD_1P BE44 BH19 VSS[220] VSS[320] Y12 AG19 VSS[61] VSS[140] AV38
DDPD_2N BF42 H10 VSS[221] VSS[321] Y38 AG2 VSS[62] VSS[141] AV4
B DAC_IREF B
T43 DAC_IREF DDPD_2P BE42 BH27 VSS[222] VSS[322] Y4 AG31 VSS[63] VSS[142] AV43
T42 CRT_IRTN DDPD_3N BJ42 BH31 VSS[223] VSS[323] Y42 AG48 VSS[64] VSS[143] AV8
1

R75 BG42 BH33 Y46 AH11 AW14


DDPD_3P VSS[224] VSS[324] VSS[65] VSS[144]
BH35 VSS[225] VSS[325] Y8 AH3 VSS[66] VSS[145] AW18
1K/F_4 CPT_PPT_Rev_0p5 BH39 BG29 AH36 AW2
VSS[226] VSS[328] VSS[67] VSS[146]
BH43 VSS[227] VSS[329] N24 AH39 VSS[68] VSS[147] AW22
BH7 AJ3 AH40 AW26
2

VSS[228] VSS[330] VSS[69] VSS[148]


D3 VSS[229] VSS[331] AD47 AH42 VSS[70] VSS[149] AW28
D12 VSS[230] VSS[333] B43 AH46 VSS[71] VSS[150] AW32
D16 VSS[231] VSS[334] BE10 AH7 VSS[72] VSS[151] AW34
D18 VSS[232] VSS[335] BG41 AJ19 VSS[73] VSS[152] AW36
D22 VSS[233] VSS[337] G14 AJ21 VSS[74] VSS[153] AW40
D24 VSS[234] VSS[338] H16 AJ24 VSS[75] VSS[154] AW48
R place close to PCH D26 VSS[235] VSS[340] T36 AJ33 VSS[76] VSS[155] AV11
D30 VSS[236] VSS[342] BG22 AJ34 VSS[77] VSS[156] AY12
R243 1 2 150/F_4 INT_CRT_BLU D32 BG24 AK12 AY22
VSS[237] VSS[343] VSS[78] VSS[157]
D34 VSS[238] VSS[344] C22 AK3 VSS[79] VSS[158] AY28
D38 VSS[239] VSS[345] AP13
D42 M14 CPT_PPT_Rev_0p5
R242 1 VSS[240] VSS[346]
2 150/F_4 INT_CRT_GRE D8 VSS[241] VSS[347] AP3
+3.3V_RUN E18 AP1
VSS[242] VSS[348]
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
R241 1 2 150/F_4 INT_CRT_RED LCD_DDCDAT R298 2 1 2.2K_4 G20 BG28
LCD_DDCCLK R299 2.2K_4 VSS[245] VSS[351]
2 1 G26 VSS[246] VSS[352] BJ28
DIS_L_CTRL_CLK R300 2 1 2.2K_4 G28
DIS_L_CTRL_DATA R301 2.2K_4 VSS[247]
2 1 G36 VSS[248]
HDMI_SCL R302 2 1 2.2K_4 G48
HDMI_SDA R303 2.2K_4 VSS[249]
A 2 1 H12 VSS[250] A
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
BOM setup Vostro Inspiron H26
H30
VSS[254]
VSS[255]
H32
H34
VSS[256]
VSS[257]
Quanta Computer Inc.
F3 VSS[258]
R241,R242,R243 POP NC PROJECT : V07
WWW.MANUALS.CLAN.SU CPT_PPT_Rev_0p5
Size Document Number
Panther Point 2/7
Rev
1A

Date: Monday, January 09, 2012 Sheet 14 of 46


5 4 3 2 1
5 4 3 2 1

Cougar Point/Panther Point (HDA,JTAG,SATA) +3.3V_RUN

IRQ_SERIRQ 10K_4 2 1 R17

18P/50V_4 2 1 C244 KB_DET# 10K_4 2 1 R23

1
Y2 U16A
32.768KHZ R219
10M_4 RTC_X1 A20 C38 LPC_LAD0
RTCX1 FWH0 / LAD0 LPC_LAD1 LPC_LAD0 28,31
D A38 D

2
FWH1 / LAD1 LPC_LAD1 28,31

LPC
18P/50V_4 2 1 C240 RTC_X2 C20 B37 LPC_LAD2
RTCX2 FWH2 / LAD2 LPC_LAD3 LPC_LAD2 28,31
FWH3 / LAD3 C37 LPC_LAD3 28,31
RTC_RST# D20 MP remove(Intel)
RTCRST# LPC_LFRAME# +3.3V_SUS
FWH4 / LFRAME# D36 LPC_LFRAME# 28,31
SRTC_RST# G22 SRTCRST#
LDRQ0# E36 LPC_LDRQ0# TP10 PCH_JTAG_TMS R26 1 2 *200_4_NC

RTC
+RTC_CELL R61 1 2 1M_4 SM_INTRUDER# K22 K36 LPC_LDRQ1# TP12 PCH_JTAG_TDI R19 1 2 *200_4_NC
INTRUDER# LDRQ1# / GPIO23 PCH_JTAG_TDO R206 1 2 *200_4_NC
PCH_INTVRMEN C17 +3V V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ 31

AM3 SATA_RXN0 PCH_JTAG_TMS R27 1 2 *100_4_NC


SATA0RXN SATA_RXN0 27
ACZ_BITCLK R224 1 2 33_4 ACZ_BITCLK_R N34 AM1 SATA_RXP0 PCH_JTAG_TDI R20 1 2 *100_4_NC
25 ACZ_BITCLK HDA_BCLK SATA0RXP SATA_RXP0 27
SATA_TXN0 SATA HDD/SSD PCH_JTAG_TDO R204 *100_4_NC

SATA 6G
SATA0TXN AP7 SATA_TXN0 27 1 2
ACZ_SYNC R229 1 2 33_4 ACZ_SYNC_R L34 AP5 SATA_TXP0 PCH_JTAG_TCK R202 1 2 *51_4_NC
25 ACZ_SYNC HDA_SYNC SATA0TXP SATA_TXP0 27
ACZ_SPKR T10 AM10 SATA_RXN1
25 ACZ_SPKR SPKR SATA1RXN SATA_RXN1 28
AM8 SATA_RXP1
SATA1RXP SATA_RXP1 28
ACZ_RST# R227 1 2 33_4 ACZ_RST#_R K34 AP11 SATA_TXN1 mSATA
25 ACZ_RST# HDA_RST# SATA1TXN SATA_TXN1 28
AP10 SATA_TXP1
SATA1TXP SATA_TXP1 28
ACZ_SDIN0 E34 AD7
25 ACZ_SDIN0 HDA_SDIN0 SATA2RXN
SATA2RXP AD5
TP8 G34 HDA_SDIN1 SATA2TXN AH5
AH4 +RTC_CELL
SATA2TXP
C34 HDA_SDIN2

IHDA
SATA3RXN AB8
PCH_MELOCK R231 1 2 1K_4 A34 AB10 RTC_RST# R54 1 2 20K/F_4
C
31 PCH_MELOCK HDA_SDIN3 SATA3RXP C
SATA3TXN AF3
AF1 SRTC_RST# R57 1 2 20K/F_4
ACZ_SDOUT R230 1 SATA3TXP
25 ACZ_SDOUT 2 33_4 ACZ_SDOUT_R A36 HDA_SDO

SATA
SATA4RXN Y7
SATA4RXP Y5

1
W W AN_RADIO_DIS# C36 +3V AD3 C36 C44
16,28 W W AN_RADIO_DIS# HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP AD1
N32 +3V_S5 1U/6.3V_4 1U/6.3V_4

2
HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
PCH_JTAG_TCK J3 AB1
TP3 JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11
TP4 JTAG_TMS SATAICOMPO

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP R40 1 2 37.4/F_4 +1.05V_PCH
TP2 JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1
TP1 JTAG_TDO
SATA3RCOMPO AB12

AB13 SATA3_COMPR46 1 2 49.9/F_4


SATA3COMPI

PCH_SPI_CLK 1 1 2 2 PCH_SPI_CLK_R T3 AH1 SATA3_RBIASR200 1 2 750/F_4


32 PCH_SPI_CLK SPI_CLK SATA3RBIAS
R205 SJ_0402
PCH_SPI_CS0# Y14
32 PCH_SPI_CS0# SPI_CS0#

TP21 T1 SPI_CS1#
SPI

P3 PCH_SATA_LED#
B SATALED# PCH_SATA_LED# 38 B
PCH_SPI_SI V4 +3V V14 KB_DET#
32 PCH_SPI_SI SPI_MOSI SATA0GP / GPIO21 KB_DET# 33
PCH_SPI_SO U3 +3V P1
32 PCH_SPI_SO SPI_MISO SATA1GP / GPIO19

EC41 *10P/50V_4_NC CPT_PPT_Rev_0p5


Take care while using GPIO19 for Hot Plug function
2 1 PCH_SPI_CLK
2 1 ACZ_BITCLK
EC42 *10P/50V_4_NC

PCH Strap Table


Pin Name Strap description Sampled Configuration note
0 = Default (weak pull-down 20K)
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode
0 = Default (weak pull-down 20K)
HDA_SDO Flash Descriptor Security PWROK 1 = Override

A A

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +RTC_CELL R215 1 2 330K_4 PCH_INTVRMEN

0 = Support by 1.8V (weak PD) +3.3V_SUS R67 1 2 1K_4 ACZ_SYNC_R Quanta Computer Inc.
HDA_SYNC On-Die PLL VR Volatge Select RSMRST 1 = Support by 1.5V
PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Panther Point 3/7
Rev
1A

Date: Monday, January 09, 2012 Sheet 15 of 46


5 4 3 2 1
5 4 3 2 1

Cougar Point-M/Panther Point (PCI,USB,NVRAM)


U16E
RSVD1 AY7
+3.3V_SUS AV7
RP9 RSVD2
BG26 TP1 RSVD3 AU3
10 1 USB_OC6# BJ26 BG4
+3.3V_RUN USB_OC4# USB_OC0# TP2 RSVD4
9 2 BH25 TP3
USB_OC1# 8 3 SIO_EXT_W AKE# BJ16 AT10
USB_OC3# USB_OC5# TP4 RSVD5
7 4 BG16 TP5 RSVD6 BC8
D RP16 USB_OC2# 6 5 AH38 D
TP6
AH37 TP7 RSVD7 AU2
5 6 HDD_FALL_INT1 10KX10 AK43 AT4
W W AN_RADIO_DIS# PCIE_MCARD2_DET# TP8 RSVD8
15,28 W W AN_RADIO_DIS# 4 7 AK45 TP9 RSVD9 AT3
PCI_PIRQC# 3 8 SATA_ODD_MD# C18 AT1
PCI_PIRQD# PCI_PIRQA# +3.3V_RUN TP10 RSVD10
2 9 N30 TP11 RSVD11 AY3
PCI_PIRQB# 1 10 H3 AT5
DGPU_HOLD_RST# 10K_4 R236 TP12 RSVD12
2 1 AH12 TP13 RSVD13 AV3
LCD_DBC 10K_4 2 1 R235 AM4 AV1
8.2KX10 DGPU_PW R_EN 10K_4 R233 TP14 RSVD14
2 1 AM5 TP15 RSVD15 BB1
GPIO5 10K_4 2 1 R234 Y13 BA3
KB_LED_DET 10K_4 R232 TP16 RSVD16
2 1 K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8

RSVD
RSVD21 BD4
RSVD22 BF6

+3.3V_SUS B21 AV5


TP21 RSVD23
M20 TP22 RSVD24 AV10
AY16 TP23
BG46 TP24 RSVD25 AT8
1

*0.1U/16V_4_NC
C231 USB3.0 AY5
RSVD26
BA2
2

USB3.0_RX1- RSVD27
22 USB3.0_RX1- BE28 TP25 USB30_RX1N
5

USB3.0_RX2- BC30 USB30_RX2N AT12


22 USB3.0_RX2- TP26 RSVD28
PCI_PLTRST# 2 USB3.0_RX3- BE32 USB30_RX3N BF3
24 USB3.0_RX3- TP27 RSVD29
4 PLTRST# BJ32 USB30_RX4N
PLTRST# 7,24,28,31 TP28
C 1 USB3.0_RX1+ BC28 USB30_RX1P C
22 USB3.0_RX1+ TP29
USB3.0_RX2+ BE30 USB30_RX2P
22 USB3.0_RX2+ TP30
U11 USB3.0_RX3+ BF32 USB30_RX3P
24 USB3.0_RX3+
3

*TC7SH08FU_NC TP31 USBP0N


BG32 TP32 USB30_RX4P USBP0N C24 USBP0N 22
USB3.0_TX1- AV26 USB30_TX1N A24 USBP0P USB2.0/USB3.0 COMBO
22 USB3.0_TX1- TP33 USBP0P USBP0P 22
USB3.0_TX2- BB26 USB30_TX2N C25 USBP1N
22 USB3.0_TX2- TP34 USBP1N USBP1N 22
USB3.0_TX3- AU28 USB30_TX3N B25 USBP1P USB2.0/USB3.0 COMBO
24 USB3.0_TX3- TP35 USBP1P USBP1P 22
AY30 USB30_TX4N C26 USBP2N
USB3.0_TX1+ TP36 USBP2N USBP2P USBP2N 24
22 USB3.0_TX1+ AU26 TP37 USB30_TX1P USBP2P A26 USBP2P 24 USB2.0/USB3.0 COMBO
USB3.0_TX2+ AY26 USB30_TX2P K28
22 USB3.0_TX2+ TP38 USBP3N
1 2 USB3.0_TX3+ AV28 H28
1 2 24 USB3.0_TX3+ TP39 USB30_TX3P USBP3P
R175 SJ_0402 AW30 E28 USBP4N
TP40 USB30_TX4P USBP4N USBP4N 28
D28 USBP4P (WLAN/BT)
USBP4P USBP5N USBP4P 28
USBP5N C28 USBP5N 28
A28 USBP5P (WWAN)
USBP5P USBP5P 28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 USBP8N
PCI_PIRQD# PIRQC# USBP8N USBP8P USBP8N 33
G38 PIRQD# USBP8P K30 USBP8P 33 Fingerprint
USBP9N G30 Port 9 for debug
Sampled DGPU_HOLD_RST# +5V
Pin Name Strap description Configuration C46 REQ1# / GPIO50 USBP9P E30

USB
LCD_DBC C44 +5V C30 USBP10N
20 LCD_DBC REQ2# / GPIO52 USBP10N USBP10N 24
DGPU_PW R_EN E40 +5V A30 USBP10P Card Reader
REQ3# / GPIO54 USBP10P USBP10P 24
Should not be pull-down USBP11N L32
GNT2# / GPIO53 ESI strap (Server only) PWROK TP23 PCI_GNT1# D47 +3V K32
(weak pull-up 20K) PCIE_MCARD2_DET# E42
GNT1# / GPIO51
+3V USBP11P
G32 USBP12N
TP13 PCI_GNT3# GNT2# / GPIO53 USBP12N USBP12P USBP12N 20
B
F46 GNT3# / GPIO55 +3V USBP12P E32 USBP12P 20 Camera B
0 = "top-block swap" mode USBP13N C32
GNT3# / GPIO55 Top-Block Swap Override PWROK 1 = Default (weak pull-up 20K) HDD_FALL_INT1 USBP13P A32
26 HDD_FALL_INT1 G42 PIRQE# / GPIO2 +3V
SATA_ODD_MD# G40 +3V
KB_LED_DET PIRQF# / GPIO3 USB_BIAS R228 1
C42 PIRQG# / GPIO4 +3V USBRBIAS# C33 2 22.6/F_4
GPIO5 D44 +3V
PIRQH# / GPIO5

USBRBIAS B33
TP5 PCI_PME# K10
Bit 0 Bit 1 PME#
GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK Boot Location
PCI_PLTRST# C6 +3V_S5 A14 USB_OC0#
PLTRST# OC0# / GPIO59 USB_OC0# 22
+3V_S5 K20 USB_OC1#
OC1# / GPIO40 USB_OC1# 24
1 1 SPI +3V_S5 B17 USB_OC2#
* CLK_33M_LPC R239 1 2 22_4 CLK_33M_LPC_R H49 +3V_S5
OC2# / GPIO41
C16 USB_OC3#
28 CLK_33M_LPC CLKOUT_PCI0 OC3# / GPIO42
GPIO19 Boot BIOS Selection 0 [bit-0] PWROK H43 +3V_S5 L16 USB_OC4#
CLK_33M_KBC R238 1 CLKOUT_PCI1 OC4# / GPIO43
0 0 LPC 31 CLK_33M_KBC 2 22_4 CLK_33M_KBC_R J48 CLKOUT_PCI2 +3V_S5 OC5# / GPIO9 A16 USB_OC5#
K42 +3V_S5 D14 USB_OC6#
CLK_PCI_FB R73 CLKOUT_PCI3 OC6# / GPIO10
17 CLK_PCI_FB 1 2 22_4 CLK_PCI_FB_R H40 CLKOUT_PCI4 +3V_S5 OC7# / GPIO14 C14 SIO_EXT_W AKE#
SIO_EXT_W AKE# 31

Default weak pull-up on GNT0/1# CPT_PPT_Rev_0p5

[Need external pull-down for LPC


EC44 *10P/50V_4_NC
BIOS] CLK_33M_KBC
2 1

A
EC45 *10P/50V_4_NC A
2 1 CLK_33M_LPC

DF_TVS DMI and FDI Tx/Rx EC5 *10P/50V_4_NC


Termination Voltage PWROK weak pull-down 20kohm CLK_PCI_FB
2 1

R25 2.2K_4
Quanta Computer Inc.
2 1 +1.8V_RUN
2 1 DF_TVS PROJECT : V07
WWW.MANUALS.CLAN.SU
DF_TVS 18
R24 1K_4 Size Document Number Rev
H_SNB_IVB# 1A
H_SNB_IVB# 7 Panther Point 4/7
Date: Monday, January 09, 2012 Sheet 16 of 46
5 4 3 2 1
5 4 3 2 1

U16B Cougar Point-M/Panther Point (PCI-E,SMBUS,CLK) SMBus/Pull-up(CLG)


+3.3V_RUN
PCIE_RXN1 BG34
28 PCIE_RXN1 PERN1
WLAN PCIE_RXP1 BJ34 +3V_S5 E12 PCH_SMB_ALERT#
28 PCIE_RXP1 PERP1 SMBALERT# / GPIO11
PCIE_TXN1 C54 2 1 0.1U/16V_4 PCIE_TXN1_CAV32
28 PCIE_TXN1 PETN1

1
1
PCIE_TXP1 C67 2 1 0.1U/16V_4 PCIE_TXP1_CAU32 H14 SMBCLK
28 PCIE_TXP1 PETP1 SMBCLK R308 R309
BE34 C9 SMBDATA 2.2K_4 2.2K_4
PERN2 SMBDATA
BF34 PERP2

5
BB32

2
2
PETN2
AY32 PETP2

SMBUS
D +3V_S5 SML0ALERT# / GPIO60 A12 DDR_HVREF_RST_PCH DDR_HVREF_RST_PCH 7,9
SMBCLK 3 4W LAN_SCLK W LAN_SCLK 11,12,25,26 D
BG36 PERN3
BJ36 C8 SML0CLK Q31A
PERP3 SML0CLK DMN66D0LDW -7
AV34 PETN3
AU34 G12 SML0DATA
PETP3 SML0DATA

2
BF36 PERN4
BE36 SMBDATA 6 1W LAN_SDATA
PERP4 PCH_GPIO74 Q31B W LAN_SDATA 11,12,25,26
AY34 PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74 C13
BB34 DMN66D0LDW -7
PETP4 SMB_CLK_ME1
+3V_S5 SML1CLK / GPIO58 E14

PCI-E*
PCIE_RXN5 BG37
24 PCIE_RXN5 PERN5
LAN PCIE_RXP5 BH37 +3V_S5 M16 SMB_DATA_ME1 Q30A
24 PCIE_RXP5 PERP5 SML1DATA / GPIO75
PCIE_TXN5 C79 2 1 0.1U/16V_4 PCIE_TXN5_CAY36
24 PCIE_TXN5 PETN5
PCIE_TXP5 C71 2 1 0.1U/16V_4 PCIE_TXP5_CBB36 SMB_CLK_ME1 4 3 SMBCLK1
24 PCIE_TXP5 PETP5 SMBCLK1 31
DMN66D0LDW -7
BJ38 PERN6
BG38

5
PERP6

Controller
AU36 PETN6 CL_CLK1 M7 +3.3V_SUS
AV36 PETP6

2
Link
BG40 PERN7 CL_DATA1 T11
BJ40 DMN66D0LDW -7
PERP7 SMB_DATA_ME1
AY40 PETN7 1 6 SMBDAT1 SMBDAT1 31
BB40 P10 Q30B
PETP7 CL_RST1#
BE38 PERN8
BC38 PERP8
AW38 +3.3V_SUS
C PETN8 C
AY38 PETP8
+3V_S5 M10 PEG_A_CLKRQ# PCH_GPIO74 R321 1 2 10K_4
CLK_PCIE_W LANN PEG_A_CLKRQ# / GPIO47 PCH_SMB_ALERT# R320 1 10K_4
28 CLK_PCIE_W LANN Y40 CLKOUT_PCIE0N 2
WLAN CLK_PCIE_W LANP Y39
28 CLK_PCIE_W LANP CLKOUT_PCIE0P
CLKOUT_PEG_A_N AB37
PCIE_CLK_REQ0# +3V_S5

CLOCKS
28 PCIE_CLK_REQ0# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
SMBCLK R286 2 1 2.2K_4
SMBDATA R287 2 1 2.2K_4
AB49 AV22 CLK_CPU_BCLKN SML0CLK R288 2 1 2.2K_4
CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_BCLKN 7
AB47 AU22 CLK_CPU_BCLKP SML0DATA R289 2 1 2.2K_4
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_BCLKP 7
SMB_CLK_ME1 R290 2 1 2.2K_4
PCIE_CLK_REQ1# M1 +3V SMB_DATA_ME1 R291 2 1 2.2K_4
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
AM13 +3.3V_SUS
CLKOUT_DP_P RP2 10KX8
AA48 CLKOUT_PCIE2N
AA47 PCIE_CLK_REQ3# 1 2
CLKOUT_PCIE2P CLK_DMI PEG_B_CLKRQ#
CLKIN_DMI_N BF18 3 4
PCIE_CLK_REQ2# V10 +3V BE18 R220 1 2 10K_4 PCIE_CLK_REQ5# 5 6
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P PCIE_CLK_REQ0# 7 8
PCIE_CLK_REQ6# R319 1 2 10K_4
Y37 BJ30 PCIE_CLK_REQ7# R318 1 2 10K_4
CLKOUT_PCIE3N CLKIN_GND1_N R225 1
Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30 2 10K_4
PCIE_CLK_REQ4# R37 2 1 10K_4
PCIE_CLK_REQ3# A8 +3V_S5
PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N G24 CLK_BUF_DREFCLK
E24 R56 1 2 10K_4 +3.3V_RUN
CLK_PCIE_LANN CLKIN_DOT_96P
24 CLK_PCIE_LANN Y43 CLKOUT_PCIE4N
LAN CLK_PCIE_LANP Y45 PCIE_CLK_REQ2# R317 1 2 10K_4
B 24 CLK_PCIE_LANP CLKOUT_PCIE4P B
CLKIN_SATA_N AK7 CLK_BUF_DREFSSCLK PCIE_CLK_REQ1# R316 1 2 10K_4
PCIE_CLK_REQ4# L12 +3V_S5 AK5 R38 1 2 10K_4
24 PCIE_CLK_REQ4# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

V45 K45 CLK_PCH_14M C251 1 2 10P/50V_4 +3.3V_SUS


CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P PEG_A_CLKRQ# 10K_4 1 2 R31

3
4
PCIE_CLK_REQ5# L14 +3V_S5 H45 CLK_PCI_FB
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 16

1
Y1

AB42 V47 XTAL25_IN R237


25MHz
CLK_REQ/Strap Pin(CLG)
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT 1M_4
AB40 V49

1
2
CLKOUT_PEG_B_P XTAL25_OUT

2
PEG_B_CLKRQ# E6 +3V_S5
PEG_B_CLKRQ# / GPIO56
1 2
Y47 XCLK_RCOMP C252 10P/50V_4
V40
XCLK_RCOMP R77 90.9/F_4 Stuff for Integrated CLK Gen Mode
CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P 1 2 +1.05V_PCH
PCIE_CLK_REQ6# T13 +3V_S5
PCIECLKRQ6# / GPIO45 CLK_PCH_14M R76 1 2 10K_4
V38 +3V K43 CLK_48M_CARD_R T8
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

V37 CLKOUT_PCIE7P
+3V F47 CLK_VGA_27M_R T15
PCIE_CLK_REQ7# CLKOUTFLEX1 / GPIO65
K12 PCIECLKRQ7# / GPIO46 +3V_S5
+3V H47 CLK_FLEX2 R240 1 2 *22_4_NC
CLK_FLEX2_25M
CLKOUTFLEX2 / GPIO66 CLK_FLEX2_25M 24
XDP CLK_PCIE_XDPN AK14 CLKOUT_ITPXDP_N
CLK_PCIE_XDPP AK13 +3V K49 CLK_VGA_27M_SS__R T16
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
A A
CLK_FLEX2_25M
CPT_PPT_Rev_0p5
Configurable as a GPIO or as a programmable output clock

1
which can be configured as one of the following: EC46
*22P/50V_4_NC
CLKOUTFLEX0 /GPIO64 ‧33 /27 /48/ 14.318 MHz / DC Output logic ‘0’
Quanta Computer Inc.

2
CLKOUTFLEX1 /GPIO65 unsupported clock output value (Default) / 27/ 14.318 MHz output to SIO/EC /48/24 MHz
CLKOUTFLEX2 /GPIO66 ‧ 33/25/27/48/24/14.318 MHz / DC Output logic ‘0’ PROJECT : V07
WWW.MANUALS.CLAN.SU
CLKOUTFLEX3 /GPIO67 ‧ 27/14.318 output to SIO/48/24 MHz (Default)
Size Document Number
Panther Point 5/7
Rev
1A

Date: Monday, January 09, 2012 Sheet 17 of 46


5 4 3 2 1
5 4 3 2 1

Cougar Point/Panther Point (GPIO,VSS_NCTF,RSVD)


U16F

BMBUSY# T7 +3V +3V C40 PCH_GPIO68


BMBUSY# / GPIO0 TACH4 / GPIO68
SIO_EXT_SMI# A42 +3V +3V B41 PCH_GPIO69
31 SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
PCIE_MCARD1_DET# H36 +3V +3V C41 PCH_GPIO70
28 PCIE_MCARD1_DET# TACH2 / GPIO6 TACH6 / GPIO70
D
+3.3V_RUN SIO_EXT_SCI# E38 +3V +3V A40 PCH_GPIO71 D
31 SIO_EXT_SCI# TACH3 / GPIO7 TACH7 / GPIO71
BD2 C10 +3V_S5
RP6 10KX8 GPIO8
1 2 SIO_EXT_SMI# LAN_PHY_PW R_CTRL C4 +3V_S5
SIO_EXT_SCI# LAN_PHY_PWR_CTRL / GPIO12
3 4
SIO_A20GATE HOST_ALERT#1 SIO_A20GATE
5 6
SIO_RCIN#
G2 GPIO15 +3V_S5 A20GATE P4 SIO_A20GATE 31
7 8
PECI AU16
SATA_MCARD3_DET#
R310 10K_4 USB_MCARD2_DET#
28 SATA_MCARD3_DET# U2 SATA4GP / GPIO16 +3V SIO_RCIN#
1 2 RCIN# P5 SIO_RCIN# 31
R311 1 2 10K_4 USB_MCARD1_DET#

GPIO
R201 1 2 10K_4 MODC_EN DGPU_PW ROK D40 +3V AY11 H_PW RGOOD
TP11 TACH0 / GPIO17 PROCPWRGD H_PW RGOOD 7
R199 10K_4 BT_RADIO_DIS#

CPU/MISC
1 2
R78 1 2 10K_4 PCIE_MCARD1_DET# DGPU_VREN T5 +3V AY10 PCH_THRMTRIP# 1 2 PM_THRMTRIP#
SCLOCK / GPIO22 THRMTRIP# PM_THRMTRIP# 7
R22 1 2 10K_4 FFS_INT2
R194 10K_4 SATA_MCARD3_DET# CAP_LED R35 390_4
1 2
RP29 10KX8
33 CAP_LED E8 GPIO24 / MEM_LED +3V_S5 INIT3_3V# T14

1 2 PCH_GPIO69 ROUSH_PAID_TS_DET# E16 DSW AY1 DF_TVS


GPIO27 DF_TVS DF_TVS 16
3 4 PCH_GPIO70
5 6 PCH_GPIO71 PLL_ODVR_EN P8 +3V_S5
PCH_GPIO68 GPIO28
7 8 TS_VSS1 AH8
USB_MCARD2_DET# K1 +3V
28 USB_MCARD2_DET# STP_PCI# / GPIO34
TS_VSS2 AK11
+3.3V_SUS USB_MCARD1_DET#
28 USB_MCARD1_DET# K4 GPIO35 +3V
TS_VSS3 AH10
CAMERA_CBL_DET#
R47
V8 SATA2GP / GPIO36 +3V
1 2 *10K_4_NC BD2
TS_VSS4 AK10
R212 1 2 10K_4 LAN_PHY_PW R_CTRL TP_LED2 M5 +3V
33 TP_LED2 SATA3GP / GPIO37
C R33 1 2 *10K_4_NC CAP_LED C
W LAN_RADIO_DIS# N2 +3V P37
28 W LAN_RADIO_DIS# SLOAD / GPIO38 NC_1
BT_RADIO_DIS# M3 +3V
28 BT_RADIO_DIS# SDATAOUT0 / GPIO39
R49 2 1 10K_4 ROUSH_PAID_TS_DET# FFS_INT2 V13 +3V BG2
26 FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
R32 2 1 10K_4 DGPU_VREN
R30 2 1 10K_4 TP_LED2 MODC_EN V3 +3V BG48
SATA5GP / GPIO49 VSS_NCTF_16
SV_DET D6 GPIO57 +3V_S5 VSS_NCTF_17 BH3

VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

A45 VSS_NCTF_3 VSS_NCTF_21 BJ45

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48


B B
BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49

BE1 VSS_NCTF_11 VSS_NCTF_29 E1

BE49 VSS_NCTF_12 VSS_NCTF_30 E49

BF1 VSS_NCTF_13 VSS_NCTF_31 F1

BF49 VSS_NCTF_14 VSS_NCTF_32 F49

CPT_PPT_Rev_0p5

Pin Name Strap description Sampled Configuration


GPIO28 On-die PLL Voltage Regulator RSMRST# 0 = Disable
1 = Enable (Default) +3.3V_SUS

R43 1 2 *1K_4_NC PLL_ODVR_EN HOST_ALERT#1 R195 1 2 1K_4 +3.3V_SUS

Intel ME Crypto Transport Layer R28 1 2 10K_4 SV_DET


Security (TLS) cipher suite

A
Low = Disable (Default) A

BMBUSY#:(Intel feedback) High = Enable


CAMERA_CBL_DET# R18 1 2 10K_4
SGPIO Follow CRB checklist, 1K is
for intel BIOS validation purpose.
+3.3V_RUN MFG-TEST Quanta Computer Inc.
Low = Tx, Rx terminated to BMBUSY#: +3.3V_RUN
DMI TERMINATION same voltage (DC Coupling Mode) BMBUSY# R3 1 2 10K_4 If not used, require a weak pull-up PROJECT : V07
VOLTAGE OVERRIDE W LAN_RADIO_DIS# R2 1 2 10K_4
WWW.MANUALS.CLAN.SU
(DEFAULT) (8.2- KΩ to 10 kΩ) to Vcc3_3. Size Document Number Rev
CRB(V1.0)P28: it has 1K PU and Panther Point 6/7 1A
100 ohm on this net for validation purpose.
Date: Monday, January 09, 2012 Sheet 18 of 46
5 4 3 2 1
5 4 3 2 1

Cougar Point/Panther Point (POWER) BOM setup VOSTOR(V07) Inspiron(R07) Cougar Point/Panther Point (POWER)
L31 QPN CX000181024 CS00003J951
BOM setup VOSTOR(V07) Inspiron(R07) VccDSW3_3= 10mA(10mil)
T14
U16J POWER +1.05V_VCCUSBCORE +1.05V_PCH
C126,C105
C123 POP NC +3.3V_SUS AD49 VCCACLK VCCIO[29] N26

P26 C47 1 2 1U/6.3V_4


C24 VCCIO[30]
VccADAC =63mA(10mils) 2 1 0.1U/16V_4 T16 VCCDSW3_3
+3.3V_RUN
Tie to 3.3V_SUS, when VCCIO[31] P28
D D
1.7 A (70mils) +1.05V_PCH_VCC don't support Deep SX T2 PCH_VCCDSW V12 T27
L31 1 DCPSUSBYP VCCIO[32]
2 180ohm/5A CP_v1.0 p88
U16G POWER VCCIO[33] T29
+3.3V_SUS
C126 1 2 10U/6.3V_6 +3V_SUS_CLKF33 T38 +3V_VCCPUSB= 50mA(10mil)
+1.05V_PCH C105 1 VCC3_3[5]
2 0.1U/16V_4 +3V_SUS_CLKF33 =30mA(10mils)
AA23 U48 C123 1 2 0.01U/25V_4 T23
VCCCORE[1] VCCADAC T13 VCCSUS3_3[7]
AC23 VCCCORE[2] BH23 VCCAPLLDMI2
AD21 T24 C40 1 2 0.1U/16V_4

CRT
10U/6.3V_6 VCCCORE[3] VCCSUS3_3[8]
2 1 C63 AD23 VCCCORE[4] VSSADAC U47 +1.05V_PCH AL29 VCCIO[14]
AF21 +VCCDPLL_CRY =40mA(10mils) V23

VCC CORE
VCCCORE[5] VCCSUS3_3[9]

USB
1U/6.3V_4 2 1 C39 AF23
1U/6.3V_4 VCCCORE[6]
2 1 C45 AG21 VCCCORE[7]
T6 AL24 DCPSUS[3] VCCSUS3_3[10] V24
1U/6.3V_4 2 1 C29 AG23 +VCCALVDS +3.3V_RUN C38 1 2 0.1U/16V_4
VCCCORE[8]
AG24 VCCCORE[9] VCCALVDS AK36 VccALVDS=1mA (10mils) VCCSUS3_3[6] P24
AG26 +3V_VCCAUBG= 100mA(10mil)
VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 AA19 VCCASW[1]
AG29 VCCCORE[12] VCCIO[34] T26 +1.05V_PCH
AJ23 +1.8V_RUN AA21
VCCCORE[13] VCCASW[2]

LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VCC5REFSUS=1mA(10mil)
AJ27 VCCCORE[15] AA24 VCCASW[3] V5REF_SUS M26 +5V_PCH_VCC5REFSUS 1 2 +5V_SUS
AJ29 AM38 VccTX_LVDS=40mA (10mils) R62 10_4
VCCCORE[16] VCCTX_LVDS[2]
AJ31 VCCCORE[17] AA26 VCCASW[4] 1 2 +3.3V_SUS

Clock and Miscellaneous


AP36 AN23 T5 D7 SDM10K45-7-F
VCCTX_LVDS[3] C103 1 DCPSUS[4]
2 10U/6.3V_6 AA27 VCCASW[5] 1 2
+1.05V_PCH AP37 C73 1 2 0.01U/25V_4 AN24 +3V_VCCPSUS C49 0.1U/16V_4
VCCTX_LVDS[4] C81 1 +1.05V_PCH VCCSUS3_3[1]
+1.05V_PCH_VCCDPLL_EXP AN19 VCCIO[28] 2 0.01U/25V_4 AA29 VCCASW[6]
VccASW =0.903A AA31 VCCASW[7]
V5REF= 1mA(10mil)
BJ22 VCCAPLLEXP (40mils)
T12 +3V_VCC_GIO +3.3V_RUN C53 2 1 10U/6.3V_6 AC26 P34 +5V_PCH_VCC5REF 1 2
VCCASW[8] V5REF +5V_RUN
V33 Vcc3_3 = 0.228A (15mils) C52 2 1 10U/6.3V_6 R89 10_4
VCC3_3[6]
HVCMOS

AN16 VCCIO[15] AC27 VCCASW[9] 1 2 +3.3V_RUN


C26 2 1 1U/6.3V_4 N20 D9 SDM10K45-7-F
VCCSUS3_3[2]

PCI/GPIO/LPC
AN17 C80 2 1 1U/6.3V_4 AC29 VCCSUS3_3 = C70 1 2 1U/6.3V_4
VCCIO[16] C68 VCCASW[10]
+1.05V_VCCIO
VCC3_3[7] V34 1 2 0.1U/16V_4 C37 2 1 1U/6.3V_4 VCCSUS3_3[3] N22 40mA (10mils)
C C
VccIO =3.711 A(160mils) AC31 SJ1 SJ0603
VCCASW[11] +3V_VCCPSUS
AN21 VCCIO[17] VCCSUS3_3[4] P20 2 2 1 1 +3.3V_SUS
AD29 VCCASW[12]
AN26 P22 C31 1 2 1U/6.3V_4
+1.05V_PCH VCCIO[18] VCCSUS3_3[5]
AD31 VCCASW[13]
AN27 AT16 +1.05V_PCH
VCCIO[19] VCCVRM[3] +1.5V_RUN
W21 VCCASW[14] VCC3_3[1] AA16 +3.3V_RUN
AP21 VCCIO[20]
W23 W16 C21 1 2 0.1U/16V_4
VCCASW[15] VCC3_3[8]
AP23 AT20 VCCPCORE =50mA(10mils)
1U/6.3V_4 C56 VCCIO[21] VCCDMI[1] C32 1U/6.3V_4
2 1 1 2 W24 VCCASW[16] VCC3_3[4] T34 +3.3V_RUN
DMI

1U/6.3V_4 2 1 C51 AP24 VccDMI =47mA (10mils)


VCCIO[22]
VCCIO

1U/6.3V_4 2 1 C42 W26 C69 1 2 0.1U/16V_4


1U/6.3V_4 C33 VCCASW[17]
2 1 AP26 VCCIO[23] VCCCLKDMI AB36
+1.05V_PCH W29 VCCASW[18]
AT24 VCCIO[24]
W31 VCCASW[19] VCC3_3[2] AJ2 +3.3V_RUN
AN33 C74 1 2 1U/6.3V_4 W33 C12 1 2 0.1U/16V_4
VCCIO[25] VCCASW[20]
VCCIO[5] AF13
+3.3V_RUN AN34 AG16 +VCC_DMI_CCI= 70mA (10mils)
VCCIO[26] VCCDFTERM[1] C19 +VCCRTCEXT
+3V_VCC_EXP 1 2 0.1U/16V_4 N16 DCPRTC
VCCIO[12] AH13 +1.05V_PCH
BH29 AG17 +1.8V_RUN
VCC3_3[3] VCCDFTERM[2]
DFT / SPI

C50 2 1 0.1U/16V_4 +1.5V_RUN Y49 AH14 C22 1 2 1U/6.3V_4


VCCVRM[4] VCCIO[13]
+VCCP_NAND
VCCDFTERM[3] AJ16 VCCPNAND = 2 mA(10mils) +V1.05S_SATA3= 400mA(20mils)
+1.05V_PCH AF14
+1.05V_VCCA_A_DPL VCCIO[6]
+1.5V_RUN AP16 VCCVRM[2]
80mA(10mils) BD47 VCCADPLLA

SATA
AJ17 C23 1 2 0.1U/16V_4 AK1 T10
VCCDFTERM[4] VCCAPLLSATA
80mA(10mils) +1.05V_VCCA_B_DPL BF47 VCCADPLLB
T9 BG6 C28 2 1 1U/6.3V_4 +VCCDIFFCLK= 40mA(10mils)
VccAFDIPLL
VCCVRM[1] AF11 +1.5V_RUN
+3V_VCCME_SPI +3.3V_RUN AF17 VCCIO[7] +1.05V_PCH
+1.05V_PCH AP17 VCCIO[27] AF33 VCCDIFFCLKN[1]
B V1 VCCSPI = 10mA(10mils) VCCDIFFCLKN= 55mA(10mils) AF34 AC16 B
FDI

VCCSPI C75 VCCDIFFCLKN[2] VCCIO[2]


1.05V_VCCDPLL_FDI=40mA(10mils) 2 1 1U/6.3V_4 AG34 VCCDIFFCLKN[3]
+1.05V_PCH AU20 VCCDMI[2] VCCIO[3] AC17
C234 1 21U/6.3V_4

1
AG33 VCCSSC VCCIO[4] AD17
CPT_PPT_Rev_0p5 VCCSSC= 95mA(10mils) C27
VccDMI =0.047 A(10mils) C61 2 1 1U/6.3V_4 1U/6.3V_4

2
2 1 +VCCSST V16
C20 0.1U/16V_4 DCPSST

T4 T17 T21 +1.05V_PCH


DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]

MISC
+VTT_VCCPCPU 1mA(10mils) VCCASW[23] V21
VCCAFDI_VRM =167mA (10mils)

CPU
+1.05V_PCH BJ8 V_PROC_IO
C15 2 1 4.7U/6.3V_6 T19
C16 VCCASW[21]
VCCVRM: 1.8V (Destop) 2 1 0.1U/16V_4
1.5V (Mobile) C14 2 1 *0.1U/16V_4_NC VCCSUSHDA= 10mA(10mils)
A22 VCCRTC P32

RTC
+RTC_CELL VCCSUSHDA +3.3V_SUS

HDA
C245 2 1 1U/6.3V_4
VCCRTC<1mA(10mils) C247 2 1 0.1U/16V_4
C246 2 1 *0.1U/16V_4_NC CPT_PPT_Rev_0p5 C62 1 2 0.1U/16V_4

SJ3 SJ0805
1 1 +1.05V_VCCA_A_DPL +3.3V_RUN
+1.05V_PCH 2 2 SJ4 SJ5
1

SJ0402 SJ0402
C125 C102 2 1 +3V_SUS_CLKF33_L 2 1 +3V_SUS_CLKF33
1U/6.3V_4 2 1 2 1
10U/6.3V_6
2

1
A A
C143 C76
SJ2 SJ0805 10U/6.3V_6 1U/6.3V_4

2
1 1 +1.05V_VCCA_B_DPL
2 2
1

C104 C87
10U/6.3V_6 1U/6.3V_4
2

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
Panther Point 7/7
Rev
1A

Date: Monday, January 09, 2012 Sheet 19 of 46


5 4 3 2 1
5 4 3 2 1

Flow PDC connector PN

LVD-A30SFYG+ EL8 DLP11SN900HL2L


D USBP12P_R 2 1 USBP12P D
1 USBP12N_R USBP12N USBP12P 16
3 4
2 USBP12N 16
3 DMIC_DATA_R 33_4 2 DMIC_DATA
1 ER4 DMIC_DATA 25
4 DMIC_CLK_R 33_4 2 DMIC_CLK
1 ER5 DMIC_CLK 25
5
6 +3.3V_RUN
+3.3V_RUN +LCDVCC
7 +LCDVCC
U10 8
9 LCD_TST +3.3V_RUN
4 1 LCD_TST 31
IN OUT 10 LCD_DDCCLK
5
IN 11 LCD_DDCDAT LCD_DDCCLK 14
2
GND 12

1
INT_TXLOUTN0_C LCD_DDCDAT 14
3
EN 13

2
EC51 C227 INT_TXLOUTP0_C
C228 EC50 0.1U/16V_4 14
G5243A 220P/50V_4

2
0.1U/16V_4 15 INT_TXLOUTN1_C
220P/50V_4

1
16 INT_TXLOUTP1_C
17

1
18 INT_TXLOUTN2_C EC33 EC34
19 INT_TXLOUTP2_C

2
20
21 INT_TXLCLKOUTN_C 22P/50V_4 22P/50V_4
D14 22 INT_TXLCLKOUTP_C
23
35
ENVDD GND 24 BLT_PWM
14 ENVDD 1 34
GND 25 LCD_BAK
33
EN_LCDVCC GND 26 R172 2 1K_4 LCD_DBC
3 32 1 LCD_DBC 16
GND 27
31
LCDVCC_TST_EN 1 GND 28
31 LCDVCC_TST_EN 2 2
C R210 *0_4_NC 29 C
30 +GFX_PWR_SRC

1
BAT54C T/R
R180 J1
10K_4
2

2
R209 R211
0_4 0_4
LCD_TST
1

R244 2 1 *0_4_NC R248 2 1 *0_4_NC

EL21 DLP11SN900HL2L EL19 DLP11SN900HL2L


AUX_WWAN_EN# AUX_WWAN_EN# 28 INT_TXLOUTN2_C 2 1 INT_TXLOUTN2 INT_TXLOUTN0_C 2 1 INT_TXLOUTN0
INT_TXLOUTP2_C INT_TXLOUTP2 INT_TXLOUTN2 14 INT_TXLOUTP0_C INT_TXLOUTP0 INT_TXLOUTN0 14
3 4 INT_TXLOUTP2 14 3 4 INT_TXLOUTP0 14

2 1 2 1
R245 *0_4_NC R250 *0_4_NC

Backlight Enable R246 2 1 *0_4_NC R257 2 1 *0_4_NC

EL22 DLP11SN900HL2L EL20 DLP11SN900HL2L


LCD_BAK INT_TXLCLKOUTN_C 2 1 INT_TXLCLKOUTN INT_TXLOUTN1_C 2 1 INT_TXLOUTN1
31 LCD_BAK INT_TXLCLKOUTP_C INT_TXLCLKOUTP INT_TXLCLKOUTN 14 INT_TXLOUTP1_C INT_TXLOUTP1 INT_TXLOUTN1 14
3 4 INT_TXLCLKOUTP 14 3 4 INT_TXLOUTP1 14

1
R171 2 1 2 1
B B
*10K_4_NC R247 *0_4_NC R339 *0_4_NC

R187 *0_8_NC
2

+GFX_PWR_SRC
+PWR_SRC
Brightness Control D13
40mil
LCD_PWM 1
40mil 1 3
14 LCD_PWM
3 BLT_PWM Q27

1
AO3409

2
1

1
PWM_VADJ 2 C236
31 PWM_VADJ

1
R173 R213 0.1U/25V_6 C230
BAT54C T/R 10K_4 100K_4

2
0.1U/25V_6

2
2

2
R190
100K_4

1
3
RUN_ON 2 Q29
31,42 RUN_ON
A
2N7002W A

1
Quanta Computer Inc.
PROJECT : V07
Size Document Number Rev
1A

Date: Monday, January 09, 2012 Sheet 20 of 46


5 4 3 2 1

WWW.MANUALS.CLAN.SU
5 4 3 2 1

Reserve for EMI and close to HDMI CONN

EL6 EXC24CG900U
HDMI_TX2+_R 1 2 HDMI_TX2+_C HDMI_TX0+_R 3 4 HDMI_TX0+_C
HDMI_TX2-_R 4 3 HDMI_TX2-_C HDMI_TX0-_R 2 1 HDMI_TX0-_C

D EXC24CG900U EL7 D

EL5 EL4
HDMI_TX1+_R 1 2 HDMI_TX1+_C HDMI_CLK+_R 1 2 HDMI_CLK+_C
HDMI_TX1-_R 4 3 HDMI_TX1-_C HDMI_CLK-_R 4 3 HDMI_CLK-_C

EXC24CG900U EXC24CG900U

INT HDMI
INT_HDMI_TXP2 C221 1 2 0.1U/16V_4 HDMI_TX2+_R
14 INT_HDMI_TXP2
INT_HDMI_TXN2 C220 1 2 0.1U/16V_4 HDMI_TX2-_R
HDMI_HPD spec VinH_min=2.0V
14 INT_HDMI_TXN2

14 INT_HDMI_TXP1
14 INT_HDMI_TXN1
INT_HDMI_TXP1
INT_HDMI_TXN1
C218 1
C217 1
2 0.1U/16V_4
2 0.1U/16V_4
HDMI_TX1+_R
HDMI_TX1-_R +3.3V_RUN HDMI HPD
C INT_HDMI_TXP0 C226 1 2 0.1U/16V_4 HDMI_TX0+_R C
14 INT_HDMI_TXP0
INT_HDMI_TXN0 C225 1 2 0.1U/16V_4 HDMI_TX0-_R
14 INT_HDMI_TXN0
INT_HDMI_TXP3 C207 1 2 0.1U/16V_4 HDMI_CLK+_R
14 INT_HDMI_TXP3

3
INT_HDMI_TXN3 C205 1 2 0.1U/16V_4 HDMI_CLK-_R
14 INT_HDMI_TXN3
Q17 2 1 2 HDMI_HPD
MMST3904-7-F 150K R130
HDMI_SCL

1
14 HDMI_SCL HDMI_SDA INT_HDMI_HPD
14 HDMI_SDA INT_HDMI_HPD
14 INT_HDMI_HPD

2
R145
5.1K/F_4

1
R278 2 1 680_4 HDMI_TX2+_R
R276 2 1 680_4 HDMI_TX2-_R

R274 2 1 680_4 HDMI_TX1+_R


IB=(5V-0.7V)/(150K+(70+1)5.1K)=8.4uA
R273 2 1 680_4 HDMI_TX1-_R
IE=(1+70)X8.4uA=596.4uA
+HDMI_LS

R281 2 1 680_4 HDMI_TX0+_R


R280 2 1 680_4 HDMI_TX0-_R
VE=596.4uA X 5.1K=3.04V
R272 2 1 680_4 HDMI_CLK+_R
B=70
R271 2 1 680_4 HDMI_CLK-_R +5V_HDMIF1
3

B B
BOM setup VOSTOR(V07) Inspiron(R07)
2

+3.3V_RUN 2
Q44 D12 D24
2N7002W SDM10K45-7-F SDM10K45-7-F
1
1

CN6 QPN DFHS19FR067 DFHS19FR066


HDMI Conn.
1

R270
*1M_4_NC
1+5V_HDMIF1_D24

CN6
1+5V_HDMIF1_D
2

SHELL1 20
HDMI_TX2+_C 1 D2+
2 D2 Shield
HDMI_TX2-_C 3
HDMI_TX1+_C D2-
4 D1+
5 D1 Shield
HDMI_TX1-_C 6
R304 R305 HDMI_TX0+_C D1-
7 D0+
Q43 2.2K_4 2.2K_4 8
HDMI_TX0-_C D0 Shield
FDV301N_G 9 23
HDMI_CLK+_C D0- GND
10
2

HDMI_SCL CK+
1 3 11 CK Shield GND 22
HDMI_CLK-_C 12 CK-
13 CE Remote
14
2

HDMI_CLK NC
+3.3V_RUN 15 DDC CLK
HDMI_DAT 16 DDC DATA
2

17 GND
+5V_RUN HDMIF1 1206L110THYR +5V_HDMIF1 18
HDMI_SDA HDMI_HPD +5V
A 1 3 19 HP DET A
SHELL2 21
1

FDV301N_G
Q42 0.1U/16V_4 HDMI
C285
2

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
HDMI
Rev
1A

Date: Monday, January 09, 2012 Sheet 21 of 46


5 4 3 2 1
1 2 3 4 5 6 7 8

USB3.0 x2 (x1 with powershare) S3/S5 USB charging circuit

1
+5V_ALW
R100
30mA 22.1K/F_4
I continuous 1.5A
USB_OC0# 16

2
+5V_ALW U18 OC 2.0A M13 Request
UP7534BRA8-15
A A
C154 2 0.1U/16V_4

17
16
15
14
13
2 IN1 OUT3 8 +USB_SIDE_PWR 1
3 7 U4 +USB_BACK_PWR
IN2 OUT2
1

1
6

FAULT
GND
PwPd
ILIM0
ILIM1
C257 C256 OUT1
4 EN#
1
2

10U/6.3V_8 GND USB_OC0#


OC# 5 USB_OC0# 16 1 IN OUT 12
2 11 USBP1N_R
0.1U/16V_4 16 USBP1N DM_OUT DM_IN USBP1P_R
16 USBP1P 3 DP_OUT DP_IN 10
R86 2 1 10K/F_4 4 9
USB_RIGHT_EN# ILIM_SEL N/C
24,31 USB_RIGHT_EN# +5V_ALW

CTL1
CTL2
CTL3
EN

1
TPS2540ARTER

5
6
7
8
R83
100K_4
31 USB_BACK_EN
EL15

2
+USB_SIDE_PWR USBP1N_R USBP1N_L
close to conn CN4 USBP1P_R
2 1
USBP1P_L
3 4
100 mil 1 VBUS DLP11SN900HL2L
1

C255 USBP0N_L 2
C258 0.1U/16V_4 C254 USBP0P_L D- USB2.0
3 D+ 31 USBP0_BUS_SW_CB0
10U/6.3V_8 150P/50V_4
2

4 GND
EL18
B USB3.0_RX1- 1 2 USB3.0_RX1-_L 5 B
16 USB3.0_RX1- SSRX-
USB3.0_RX1+ 4 3 USB3.0_RX1+_L 6
16 USB3.0_RX1+ SSRX+
DLP11TB800UL2 USB3.0_TX1-_L 8 USB 3.0
USB3.0_TX1+_L SSTX-
9 SSTX+ GND 10
GND 11 USBP0_BUS_SW_CB0 Mode R8224 mA
7 GND GND 12
GND 13

USB3
Low DCP, Auto-detect OC 100k ohm 480
limitation
High CDP, BC Spec 1.1 22.1k ohm 2171 Applied Now
+USB_BACK_PWR
close to conn CN3
100 mil 1
EL17 VBUS

1
USB3.0_TX1- C262 2 1 0.1U/16V_4 USB3.0_TX1-_C 1 2 USB3.0_TX1-_L C248 USBP1N_L 2
16 USB3.0_TX1- D- USB2.0
USB3.0_TX1+ C261 2 1 0.1U/16V_4 USB3.0_TX1+_C 4 3 USB3.0_TX1+_L C250 0.1U/16V_4 C249 USBP1P_L 3
16 USB3.0_TX1+ D+
10U/6.3V_8 150P/50V_4

2
DLP11TB800UL2 4
DLP11TB800UL2 GND
USB3.0_RX2- 4 3 USB3.0_RX2-_L 5
16 USB3.0_RX2- SSRX-
USB3.0_RX2+ 1 2 USB3.0_RX2+_L 6
EL16 16 USB3.0_RX2+ SSRX+
USBP0N 1 2 USBP0N_L EL3 USB3.0_TX2-_L 8 USB 3.0
16 USBP0N USBP0P USBP0P_L USB3.0_TX2+_L SSTX-
16 USBP0P 4 3 9 SSTX+
C GND 11 C
7 GND GND 12
DLP11SN900HL2L 13
USB_CHG_DET# GND
34 USB_CHG_DET# 10 D1 DETECT GND 14

USB3.0 10P FR

DLP11TB800UL2
USB3.0_TX2- C119 2 1 0.1U/16V_4 USB3.0_TX2-_C 4 3 USB3.0_TX2-_L
16 USB3.0_TX2-
USB3.0_TX2+ C108 2 1 0.1U/16V_4 USB3.0_TX2+_C 1 2 USB3.0_TX2+_L
16 USB3.0_TX2+
EL2

ESD Function
Place ESD diodes as close as USB connector.
ESD2
USBP0N_L 1 6 USBP1N_L +5V_ALW
EU2 ESD7004MUTAG 1 6
2 2 5 5
USB3.0_TX1+_L 1 USB3.0_TX1+_L
10 USBP0P_L 3 4 USBP1P_L EU1 ESD7004MUTAG
1- NC 3 4 USB3.0_TX2+_L USB3.0_TX2+_L
1 1- NC 10
USB3.0_TX1-_L 2 9USB3.0_TX1-_L *TVL ST23 04 AD0_NC
1+ NC USB3.0_TX2-_L 2 1+ NC 9USB3.0_TX2-_L
3 GND GND 8
3 GND GND 8
D USB3.0_RX1+_L 4 7USB3.0_RX1+_L D
2- NC USB3.0_RX2+_L 4 2- NC 7USB3.0_RX2+_L
USB3.0_RX1-_L 5 6USB3.0_RX1-_L
2+ NC USB3.0_RX2-_L 5 2+ NC 6USB3.0_RX2-_L

Quanta Computer Inc.


PROJECT : V07
Size Document Number Rev
1A
USB3.0
Date: Monday, January 09, 2012 Sheet 22 of 46
1 2 3 4 5 6 7 8

WWW.MANUALS.CLAN.SU
A B C D E

Vostro only +5V_RUN

2
D6
SDM10K45-7-F

4 4

1
CRTF1
Layout Note: 1206L110THYR
Setting R,G,B treac
EL12
impedance to 50 ohm. BLM18BB750SN1D
INT_CRT_RED 1 2 RED
14 INT_CRT_RED

+5V_CRT_REF
EL10
BLM18BB750SN1D
INT_CRT_GRE 1 2 GREEN
14 INT_CRT_GRE

17
EL11 07012HR015S252ZR
BLM18BB750SN1D 6
INT_CRT_BLU 1 2 BLUE 1
14 INT_CRT_BLU
11
1

1 7

1
R188 R189 R186 EC39 EC40 EC38 EC35 EC36 EC37 2
150/F_4 150/F_4 150/F_4 22P/50V_4 22P/50V_4 22P/50V_4 22P/50V_4 22P/50V_4 22P/50V_4 12
8

2
3
2

13
9
4
14
3 10 3
5
+5V_CRT_REF 15
+3.3V_RUN JVGA1

16
1

1
R203 R181 R178 R193
2.2K_4 2.2K_4 2.2K_4 2.2K_4
Q26
BSS138-7-F

2
INT_DDCDAT 1 3 G_DAT_DDC_C
14 INT_DDCDAT

2
+3.3V_RUN

2
INT_DDCCLK 1 3 G_CLK_DDC_C
14 INT_DDCCLK

+5V_RUN BSS138-7-F
Q28

2 2
5

U15

INT_CRT_HSYNC 2 4 HSYNC_R 1 2 HSYNC


14 INT_CRT_HSYNC
ER11 33_4

74AHCT1G125GW Place near


C11 74AHCT125 <
0.1U/16V_4
2 1
200 mil
5

U13

INT_CRT_VSYNC 2 4 VSYNC_R 1 2 VSYNC


14 INT_CRT_VSYNC
ER10 33_4

74AHCT1G125GW

1 1

Quanta Computer Inc.


PROJECT : V07
WWW.MANUALS.CLAN.SU Size Document Number
VGA
Rev
1A

Date: Monday, January 09, 2012 Sheet 23 of 46


A B C D E
A B C D E

52
1

52
1 +5V_ALW
2 2
3 3
4 4
5 5
6 6 +3.3V_ALW
7 7
4
8 8 +3.3V_SUS 4

9 9 +3.3V_RUN
10 10
11 PCIE_CLK_REQ4#
11 PCIE_CLK_REQ4# 17
12 CLK_FLEX2_25M CLK_FLEX2_25M 17
+3.3V_RUN +3.3V_SUS +3.3V_ALW +5V_ALW 12 PCIE_EC_WAKE#
13 13 PCIE_EC_WAKE# 28,31
14 PLTRST#
14 PLTRST# 7,16,28,31
15 USB_RIGHT_EN# USB_RIGHT_EN# 22,31
15 USB_OC1#
16 16 USB_OC1# 16

1
17 CLK_PCIE_LANN
17 CLK_PCIE_LANN 17
C167 C160 C161 C146 18 CLK_PCIE_LANP
18 CLK_PCIE_LANP 17
0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 1U/6.3V_4 19

2
19 PCIE_RXN5
20 20 PCIE_RXN5 17
21 PCIE_RXP5
21 PCIE_RXP5 17
22 22
23 PCIE_TXN5
23 PCIE_TXN5 17
24 PCIE_TXP5
24 PCIE_TXP5 17
25
25 USBP10N
26
26 USBP10P USBP10N 16
27
27 USBP10P 16
28
28 USBP2P
29
29 USBP2N USBP2P 16
30
30 USBP2N 16
31
31 USB3.0_RX3-
32 USB3.0_RX3- 16
32 USB3.0_RX3+
33 USB3.0_RX3+ 16
33
34
34 USB3.0_TX3-
35 USB3.0_TX3- 16
35 USB3.0_TX3+
36 USB3.0_TX3+ 16
3 36 3
37
37 HP_JD#
38 HP_JD# 25,31
38 TIP
39 TIP 25
39 SLEEVE
40 SLEEVE 25
40 RING2
41 RING2 25
41
42
42 HPOUT_R
43 HPOUT_R 25
43 HPREF
44 HPREF 25
44 HPOUT_L
45 HPOUT_L 25
45 SPK_L+
46 SPK_L+ 25
46 SPK_L-
47 SPK_L- 25
47
48
48 SPK_R-
49 SPK_R- 25
CN5 49 SPK_R+
50

51
50 SPK_R+ 25
88511-4001

51
2 2

1 1

Quanta Computer Inc.


PROJECT : V07
Size Document Number Rev
1A
FPC CONN
Date: Monday, January 09, 2012 Sheet 24 of 46
A B C D E

WWW.MANUALS.CLAN.SU
5 4 3 2 1

Beep&Mute check with FAE


ACZ_BITCLK_E
+3.3V_SUS
C185
1 2

1
EC22
D *22P/50V_4_NC
0.1U/16V_4
CHECK WITCH FAE D

2
ACZ_SDOUT 1 2
15 ACZ_SDOUT BEEP 31
D10 SDM10K45-7-F
ACZ_BITCLK ER2 2 1 22_4 ACZ_BITCLK_E 1 2
15 ACZ_BITCLK ACZ_SPKR 15

1
D11
ACZ_SDIN0 R127 1 2 33_4 ACZ_SDIN0_R R125 SDM10K45-7-F
15 ACZ_SDIN0
10K_4
ACZ_SYNC
15 ACZ_SYNC
CAS4213D CO-LAY

2
ACZ_RST#
15 ACZ_RST#

+5V_RUN +RTC_CELL
+3.3V_RUN +3.3V_RUN

1
C194 C193 C182
10U/6.3V_6 1U/6.3V_4 0.1U/16V_4

37

36

35

34

33

32

31

30

29

28
2

1
U7 R116
R122

SPDIF_OUT

VL_IF
BITCLK
SYNC

VL_HD
thermal pad

SDI
VP_L

RESET#

SDO
10K/F_4
SLEEVE 100K_4

2
3
Q46A
SPK_L+ 1 27 DMIC_DATA R123 11K/F_4 5
24 SPK_L+ SPKR_L+ DMIC_SDA/SENSE_B DMIC_DATA 20
1 2 EC_HP_JD#
EC_HP_JD# 31
SPK_L- 2 26 DMIC_CLK DMN66D0LDW-7
24 SPK_L- DMIC_CLK 20

4
C
SPKR_L- DMIC_SCL R124 18K/F_4 C
3 25 SENSE_A 1 2 MIC_JD#
PGND_L SENSE_A

6
Q46B
4 PGND_R VREFOUT_C 24 2 SIO_SLP_S3# 9,13,31,41

24 SPK_R-
SPK_R- 5 CS4213D 23 DMN66D0LDW-7

1
SPKR_R- MICIN
SPK_R+ 6 22 MIC_BIAS
24 SPK_R+ SPKR_R+ VREFOUT_B

1
+5V_RUN 7 VP_R LINEIN_R 21
MIC C179
8 20 1U/6.3V_4

2
FLYP LINEIN_L
1

C198 C195 C196 9 19


10U/6.3V_6 1U/6.3V_4 FLYN VCOM

VREF_FILT
2

VHP_FILT-

HPOUT_R
2.2U/6.3V_6

HPOUT_L
2

HPREF
VA_HP

1
AGND
GND
C181 MIC_JD#

VA
10U/6.3V_6

1
+3.3V_RUN
10

11

12

13

14

15

16

17

18
R131
0_4
MIC_BIAS

2
1
R133

1
+1.8V_RUN +1.8V_RUN
U8 R120
1

1
C197 C186 100K_4 2.2K_4

1
B C184 WLAN_SCLK 1 8 B
C199

2
0.1U/16V_4 2.2U/6.3V_6 2.2U/6.3V_6 C191 11,12,17,26 WLAN_SCLK WLAN_SDATA SCL MIC_PRESENT TIP
2 9 TIP 24
2

2
0.1U/16V_4 11,12,17,26 WLAN_SDATA ADDR_SEL SDA TIP_SENSE MIC_R MIC