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8 December 2019 1441 ‫الثان‬
‫ ربيع ي‬11
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Digital IC Design

Lecture 03
Basic CMOS Circuits

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
 MOSFET
❑ MOSFET: Metal Oxide Semiconductor Field Effect Transistor
❑ Four terminals: gate, source, drain, body (bulk)
❑ NMOS body is usually tied to the lowest potential (VSS, ground, 0V)
❑ PMOS body is usually tied to the highest potential (VDD, power)
▪ VDD is scaled down: 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
❑ The gate controls the flow of current between the source and drain

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 Transistor as a Switch
❑ NMOS
▪ Gate HIGH: Switch closed (ON)
▪ Gate LOW: Switch open (OFF)
❑ PMOS
▪ Gate LOW: Switch closed (ON)
▪ Gate HIGH: Switch open (OFF)

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 CMOS Inverter
❑ Ideally, there is no static (idle) power consumption

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 CMOS NAND Gate
❑ Rule of Conduction Complements
▪ Pull-up network is complement of pull-down
▪ Parallel -> series, series -> parallel

PDN PUN

Bubble pushing with

DeMorgan’s law

03: Basic CMOS Circuits 5

 CMOS NOR Gate
❑ Rule of Conduction Complements
▪ Pull-up network is complement of pull-down
▪ Parallel -> series, series -> parallel

PDN PUN

Bubble pushing with

DeMorgan’s law

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 General Static CMOS Gate
❑ Crowbar (contention) is usually an unwanted condition

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 AND-OR-INVERT-22 (AOI22)
❑ An example of a complex logic function in a single stage (8 Ts)

❑ The wrong way of doing it (20 Ts)

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 Quiz
❑ What is the name of this gate?
(a) AOI31 (b) OAI33 (c) OAI31

A
B
C D
Y
D
A B C

03: Basic CMOS Circuits 9

 Pass Transistors
❑ NMOS: Strong ‘0’ but Weak ‘1’
▪ That’s why we use it in the pull-down network

❑ PMOS: Strong ‘1’ but Weak ‘0’

▪ That’s why we use it in the pull-up network

03: Basic CMOS Circuits 10

 Transmission Gate
❑ Strong ‘0’ and ‘1’ (if the input is strong!)
❑ Simple, but non-restoring (noisy/degraded input passed to output)

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 Multiplexer
❑ Non-restoring mux

❑ Restoring mux (where have we seen this schematic before?)

❑ Multiplexers are usually preferred over tristate busses (why?).

03: Basic CMOS Circuits 12

 Level sensitive D-latch
❑ CLK = 1: transparent
❑ CLK = 0: hold current state
❑ How do we get a negative latch?

03: Basic CMOS Circuits 13

 Master-Slave Edge-Triggered D Flip-Flop
❑ Negative latch (master) + positive latch (slave)
❑ Register: A collection of D flip-flops sharing a common clock

03: Basic CMOS Circuits 14

 Thank you!

03: Basic CMOS Circuits 15