0 0
S 1 S 0
Q Q A B NOR
0 1
0 0 1

0 1 0

1 0 0
1 0
1 1 0
Q Q
R 0 R 1
0 0
(a) (b) (c)

   !"# $&%
 ')( *,-+ ' ./+- 0 12' +34,52+678)9:;<' ,+=+> ?@ABDCEF
S
Q

Clock

Q
R

G
 H I JLK M

   .N12 O %
D
Q

E+PDQR12

S T VU WX#,Y 526 Z8 $  T*[ \E] U [ \^

S _ WX<EY 56 Z8 $  _ [ \^

`
 a b dc e,f  c

gY  +h 2 +>  ] +> ?Q7BDC,F jijik:'<' l C*,<.E +

 ')( *,  +-' . +- 0 #,Y 526 Z8m$

d
∆

a b b AND c
d

c
c

(a) b

Time

(b)

D
Q

n
 H I JLK M a b oc e,f  c

S   p% +!'qi<'2+rDQ>(E(E''). Ws)>;*m$ ./E+N+6-i<'+t+- ^

S u +h1q u +-1/% 'r.,(k' DQ>(,(k'2v'). Ws)9: $ .N,+ wB;"

$' ^

x +PDQyY  
. y1'2 'E+6zq#v' {|1"X{1p%
{}41qX{~;1 Y )Z$'"+>ji<' WX.;C#' +>   #)?# 8 ^q€

 Y ' ‚+>m  ] ƒ{|1"X{~;1 V &.!Z( <C ;<  *

5 r„'
p„'r(;,+6 .L( 'm$„L%   † O † T U † _

 E1,19'm„'2m8)9:;<' (;F ‡ˆ#p%

D Q D Q D Q D Q

CK CK CK CK

(a) (b) (c) (d)

Ws ^ $W 5 ^ +>m  † WX ^ XW . ^ {|1"‰{~1

Š
 ‹ Œ Ž J 9

'+-'2Y ' p.yY '2Y NQ6  12C 9-ws' 52Q:' W$57 †

5*9 .> (7 ^

v'E+h!"))9:#'R% C, „'rl;C#'2r# ./{|1"‰{~1

‘
 ’ b K “

 ”C27p„'rl;C#'2r96,+6•%
9”C27$ Y 52 $NQ: – Y 'Y NQ6

Outputs
Combinational logic

Next state

State register

Inputs

wsC,r9:*EY ' $&%

S  +‚9”C7$ Y 52 $NQ: .E'D$'2dY * + 19ks

Y  Z8 $

S +- Z8 $ .k'q$'dY 4 +3Ž<(;'m$„ .E'+ ”C27$

Y 52*m$/@>

g}1)$— .N ˜8 $  Z8m$

 +- 0k% +R„'r(;,+-' #' <<.E')# +3t'qi<+=C)9:;<'
™
 Falling edge

Clock period Rising edge

šC › :' $'Y ' $' +=C,<(E&% +&9”C27$ .k'"i<' Z8,5œ

+6!"#9

ž@+Ÿ12C/3 12k$V45+!' 5 v'"i<'R% +ˆ”C27$ .E'qi' j;Y 1EC"

89' i<'2+- 'Y ' $' €

ˆ'2Q: .k . +- 0k% *E<k ') <.E W$) ^ W \#¡N¢ £
 ') <. ^
 ’ ¤ K ¥  J  ¦ 

  I

14C§ ')(¨!ZDQ•% <. R( 2 z˜8, $'  „'2+-'m9: C,
v')(¨z˜D
Data in
I2
I1
I0

Write D Q D Q D Q
gate Word 0
CK CK CK

Word 0
select
line D Q D Q D Q
Word 1
CK CK CK

Word 1
A1 select
A0 line D Q D Q D Q
Word 2
CK CK CK

Word 2
select
line D Q D Q D Q
Word 3
CK CK CK

CS • RD

CS

O1
RD
O2

O3

OE Output enable = CS • RD • OE

©
&'r(;,+6

S ž@.Q!"m

S O  ~4 (;v' $ 

S &'r(;,+6ƒ. mD+=+-

ª   21 „'+!'r

ª  O v'<.

ª « ¬ CmD1,Cm '2,5E+!'

S O  ~4 C)?978
 x ­ Z8m>#'   x ­

 x ­ .¨4,Y >#' O  x ­
Word line

Pass transistor

Capacitor

Bit line

O Ai'„' $'r<+-,(:' . kZDdCr9:#'

S ¬ O « W ¬L® $'r.E'r. ./ 8 ;C D1,Cm ^

S  O  x ­ WX;R<E#Cr O  x ­ ^

S O O ¯° x ­ W„O ;C,5,+-' O  8   $'  x ­ ^

S  EY —5EC)

g#,CEY ' 8 +3±EY 1:' ") .¨5,.N ] < +> +²m$'2r#

u !><EY ' $',% 9”C27& $'r(;Fm ] ž   21

³
  ¦ ¥ b ¦ 

 9 I

9-to-512 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64 512 × 64

decoder 512 SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
Address
[14–6]

64
Address
[5–0]

Mux Mux Mux Mux Mux Mux Mux Mux

Dout7 Dout6 Dout5 Dout4 Dout3 Dout2 Dout1 Dout0

y0D<((

S ƒž ­ ­ g4<(;+-' žQE+h#' ­ '2Y / ­  .;CE+-'

S O ž­ ­ O C,5E+-' ž@,+6<' ­ 'Y N ­  .;CE+!'

S  « O ž ­ ­ šY ,+=+ « C D+6<' O ž ­ ­

´

  ¦  } bµI b JpJ ¥  I

S  « ­

S  « ­

S ¬  « ­

S ¬ ¬  « ­

S W$Y '2Y NQ6 {¶)q ^

GQ·