TOSHIBA TC7WO4F/FU/FK TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC7WO4F, TC7WO4FU, TC7WO4FK 3 INVERTERS The TC7WO4 is high speed C2MOS BU silicon gate C2MOS technology. ‘The internal circuit is composed of 3 buffer output, which enable high noi stable output. IFFER fabricated with stage including ise immunity and All inputs are equipped with protection circuits against static discharge or transient excess vol FEATURES . High Speed Low Power Dissipation tage. lec= 1,28 (Max. at Ta=25°e TCTWOaF soPe--1.27 Te7woaru —™. © High Noise Immunity Viet = Vie = 28% Vcc (Min.) © Output Drive Capability 10 LSTTL Loads © symmetrical Output Impedance... llgy|=loL =4mA ss07e 7-065 (min.) TC7WwoaFK © Balanced Propagation Delays tpLHStpHL © Wide Operating Voltage Range ... Vcc (opr) =2~6V MARKING TCTWOAE sc wane TCTWOAFU Te7woark Boag” OO jeter 7WO4F 7WoO4 Lot Wo. SS0PEP.O-50A tot No w Weight 04 ‘SOP8-P-1.27 0.05g (Typ.) . oo Oo l. SSOP8-P-0.65 : 0.029 (Typ) fats 380P8-P.0.50A : 0.019 (Typ) 1 2001-05-31TOSHIBA TC7WO4F/FU/FK MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Vohage Range Vee TOS=7 Vv DC Input Voltage Vin =O5=Vec+05_| V DC Output Voltage Vour_| _-05=Vec+05_| V Input Diode Current TK. £20 mA [Output Diode Current lok £20 mA DC Output Current tour £25 mA DC Vec/Ground Current lee £25 mA 300 (FMB, SMB) Power Dissipation Pp 300 (058) mw [Storage Temperature Tag = 65~150 *€ Lead Temperature (10s) TL 260 % LOGIC DIAGRAM TRUTH TABLE PIN ASSIGNMENT (TOP VIEW) w o "a 7 v aly 2a OY NL) oy aa Of NO) yy L H HTL RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC SYMBOL RATING UNIT Supply Vohage Range Vee 26 Vv Input Voltage VIN o-Vec v [Output Voltage Vout o=Vec v [Operating Temperature Tope =40~85 = (0=1000 (Vec =2.0V) Input Rise and Fall Time tr te | 0~ 500 (vec=4.5v)| ns O~ 400 (Vcc =6.0V)TOSHIBA TC7WO4F/FU/FK DC ELECTRICAL CHARACTERISTICS Tasasc [las 40-85 ‘CHARACTERISTIC | SYMBOL TEST CONDITION Tec MNP IM MiN Twa] UNIT High-Level aslais|_|_|as| — ; Vin - 45|315| —| —|] 315] — | v Input Voltage 6o| 42|—~|—| a2] — ow lew 207 —|—] 05] — | os Low-Level Vi = as} —|— | 135] — | 135] v input Voltage 6o| —|—| 18| — | 18 20] 19] 20f— | 19 f — sigh-tevel a5| 44) as] —| a4] — jigh-Level Vou 6o| 59| 60| —| s9| — | y Output Voltage 45/418/431| — | 413] — 6.0 |5.68|5.80| — | 563 | — 20] —| oof o1| — | oa vew-teve 45|—| 00] 01] — | 01 ow-Level Vou |vin=Vin 60] —| oo] o1| — | or] y Output Voltage 45 | — [0.17] 026, — | 033 60 | — |o18|026| — | 033 Input Leakage lin |Vin=Vec or GND 60] — | — |t01] — | +10 Current (Quiescent “a Supply Current tec |Win=Vec or GNP se} =| =] te] = | 8