5

CHARGER

HPA02224RGRR-1-GP
INPUTS
OUTPUTS

Cedar/Janus Block Diagram

Project code:4PD00I010001
PCB P/N: 13302-1
Revision: A00

AD+

44

DCBATOUT

BT+

SYSTEM DC/DC

TPS51225RUKR-GP
INPUTS
OUTPUTS

45

3D3V_AUX_S5
5V_AUX_S5
DCBATOUT 5V_S5
3D3V_S5

Intel CPU

GPU
2GB

DDR3L

78,79

DIS only

DDR3L SUS

WPT-LP
4 USB 3.0 ports

VGA

RTD2168

PCIE x 1

High Definition Audio

DP/VGA Converter (Janus only)

DP

0D65V_S0

RJ45
Conn.
30

8 PCIE ports

CPU 1.05V

RT8237CZQW-2-GP
INPUTS
OUTPUTS

31

CPU 1D5V_S0

PCIE x 1
HDMI

USB2.0 x 1

54

14.0"/15"/17" LCD
52
(16:9)

WLAN

USB1(USB3.0)

MIC_IN/GND

1D35V_S0

5V_S5

5V_S0

3D3V_S5

3D3V_S0

1D05V_S0

1D05V_VGA_S0

3D3V_S0

3D3V_VGA_S0

1D35V_S3

1D35V_VGA_S0

PCB LAYER

HDA

L1:Top
L2:VCC
L3:Signal
L4:Signal
L5:GND
L6:Signal

IO Board

Right side

USB3(USB2.0)

27

Combo Jack
2CH SPEAKER
(2CH 2W/4ohm)

USB2.0 x 1
29

1D35V_S3

34,35

52

USB2.0 x 1

36 83

OUTPUTS

USB2(USB2.0)

USB2.0 x 1

Realtek
ALC3234

HP_R/L

Left side

USB2.0 x 1

HDA
CODEC

29

34,35

USB2.0 x 1

Camera
Digital MIC

INPUTS

Left side

USB3.0 x 1

Touch Panel

Switches
58

51

1D5V_S0

3D3V_S5

802.11a/b/g/n
BT V4.0 combo

USB2.0 x 1

eDP

TLV70215DBVR-GP
INPUTS
OUTPUTS

ACPI 4.0a

HDMI V1.4a
(Cedar only)

48

DCBATOUT 1D05V_S0

LPC I/F

49

DCBATOUT 1D35V_S3

RealTek
Cedar:(10/100)RTL8106E
Janus:(10/100/1000)RTL8111G

4 SATA ports

55

TPS51716RUKR-GP
INPUTS
OUTPUTS

LAN
10/100 & 10/100/1000 co-lay

8 USB 2.0/1.1 ports

VGA Conn.
(Janus only)

DCBATOUT VCC_CORE

12

28W (UMA)
15W (DIS)

PCIE x 4

46,47
ISL95813HRZ-GP
33
INPUTS
OUTPUTS

SODIMM A

Broadwell ULT

NVIDIA
N15V-GM-S-A2
GB2-64 (23x23)
73,74,75,76,77
25W

VRAM(DDR3L) *4

CPU Core Power

DDR3L
1333/1600

DDR3L 1333/1600MHz Channel A

CardReader

SD Card Slot

Realtek
RTS5170

LPC BUS

LPC debug port

65

Thermal

SMBUS

NUVOTON
NCT7718W 26

KBC

SATA(Gen3) x 1

NUVOTON
NPCE285P

Fan Control
A

ANPEC
APL5606AKI

FAN26

HDD
56

SPI
24

26

Int.
KB

SATA(Gen1) x 1

Flash ROM

PS2

8MB
Quad Read 25

ODD
56

<Core Design>

62

Wistron Corporation

I2C

Touch PAD
Image sensor

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Block Diagram

62
Size
C
Date:
5

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

X02
of

104

(Blanking)
C

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

2

Sheet

A00
of

104

SSID = CPU
1D05S_VCCST
RN401
XDP_TMS
XDP_TDI

1
2
3
4

XDP_TDO

8
7
6
5

DY

SRN51J-1-GP
XDP_TRST# R402
XDP_TCLK R406

1
1

DY

2 51R2J-2-GP
2 51R2J-2-GP

1D05S_VCCST
HSW_ULT_DDR3L

CPU1B
R401
62R2J-GP

TP402
[24]

Impedance control:50 ohm

1
TP403
1

H_CATERR#

H_PECI

[24,42,44,46] H_PROCHOT#

[36] H_THERMTRIP_EN

D61
K61
N62

PROC_DETECT#
CATERR#
PECI

MISC

Layout Note:

2 OF 19

Remove TP401 for TP604 spacing.

DY
R411

2 H_PROCHOT#_R
R403
156R2J-4-GP
H_CPUPWRGD

2
2

0R2J-2-GP

Layout Note: Close to CPU

[12] DDR_PG_CTRL

K63

C61

R405

PROCHOT#

JTAG
THERMAL

PROCPWRGD

AU60
AV60
AU61
AV15
AV61

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST#
SM_PG_CNTL1

J62
K62
E60
E61
E59
F63
F62

XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

J60
H60
H61
H62
K59
H63
K60
J61

XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7

XDP_PRDY# [96]
XDP_PREQ# [96]
XDP_TCLK [96]
XDP_TMS [96]
XDP_TRST# [96]
XDP_TDI [96]
XDP_TDO [96]

XDP_BPM[7:0]

PWR

1
10KR2J-3-GP
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST#
DDR_PG_CTRL

PRDY#
PREQ#
PROC_TCK
PROC_TMS
PROC_TRST#
PROC_TDI
PROC_TDO

DDR3L

XDP_BPM[7:0] [96]

HASWELL-6-GP-U

200R2F-L-GP

SM_RCOMP_0

R408 1

121R2F-GP

SM_RCOMP_1

100R2F-L1-GP-U SM_RCOMP_2

1D35V_S3

Layout Note:
Place close to DIMM

R410
470R2J-2-GP
2

R409 1

71.HASWE.G0U

R407 1

SM_DRAMRST#

1 R404

DDR3_DRAMRST# [12]

0R0402-PAD

Layout Note:

<Core Design>

Design Guideline:
SM_RCOMP keep routing length less than 500 mils.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (THERMAL/MISC/PM)

Size
A4

Document Number

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

of
1

Rev

A00
104

SSID = CPU
DDR3L ball type: Non-Interleaved Type
CPU1C
[12] M_A_DQ[63:0]

CPU1D

HSW_ULT_DDR3L

HSW_ULT_DDR3L

4 OF 19

3 OF 19

M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS#
SA_WE#
SA_CAS#
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

DDR CHANNEL A

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

M_A_DIMA_CLK_DDR#0 [12]
M_A_DIMA_CLK_DDR0 [12]
M_A_DIMA_CLK_DDR#1 [12]
M_A_DIMA_CLK_DDR1 [12]

AU43
AW43
AY42
AY43
AP33
AR32

M_A_DIMA_CKE0
M_A_DIMA_CKE1

[12]
[12]

M_A_DIMA_CS#0
M_A_DIMA_CS#1

[12]
[12]

TP_M_A_DIMA_ODT0

AP32
AY34
AW34
AU34

TP501

M_A_RAS# [12]
M_A_WE# [12]
M_A_CAS# [12]

AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

AP49 +V_SM_VREF_CNT
AR51
AP51

M_A_BS0 [12]
M_A_BS1 [12]
M_A_BS2 [12]
M_A_A[15:0]

[12]

M_A_DQS#[7:0]

M_A_DQS[7:0]

+V_SM_VREF_CNT
DDR_WR_VREF01

[12]

[12]

[37]
[37]

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS#
SB_WE#
SB_CAS#
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

DDR CHANNEL B

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38
D

AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

HASWELL-6-GP-U
HASWELL-6-GP-U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

Document Number

CPU (DDR)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

of

A00
104

SSID = CPU

D
HSW_ULT_DDR3L

CPU1S

19 OF 19

#514405

[96]

CFG[19:0]

CFG[19:0]
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

R601
49D9R2F-GP

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AA62
U63
AA61
U62

CFG16
CFG18
CFG17
CFG19

V63
A5
E1
D1
J20
H18
B12

TD_IREF

AV63
AU63

RSVDAV63
RSVDAU63

1
1

TP601
TP602

RSVD_TP#C63
RSVD_TP#C62
RSVD#B43

C63
C62
B43

RSVDC63
1
RSVDC62
1
EDP_SPARE 1

TP603
TP604
TP605

RSVD_TP#A51
RSVD_TP#B51

A51
B51

RSVDA51
RSVDB51

1
1

TP606
TP607

RSVD_TP#L60

L60

RSVDL60

TP608

RSVD#N60

N60

RSVD_TP#AV63
RSVD_TP#AU63

RESERVED

RSVD#W23
RSVD#Y22
PROC_OPI_RCOMP
RSVD#AV62
RSVD#D58

CFG_RCOMP

VSS
VSS

RSVD#A5
RSVD#P20
RSVD#R20

RSVD#E1
RSVD#D1
RSVD#J20
RSVD#H18
TD_IREF

W23
PROC_OPI_COMP3
Y22
AY15 PROC_OPI_COMP

Intel Recommend
R606 1
R602 1

DY

2 49D9R2F-GP
2 49D9R2F-GP

AV62
D58

Layout Note:

P22
N21
P20 HVM_CLK#
R20 HVM_CLK

1
1

TP619
TP620

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy
signals.
3.Trace width: 12~15mil
4.Isolation Spacing: 12mil
5.Max length: 500mil

R603
8K2R2F-1-GP

#514405

PCH strap pin:

1

CFG3
R604
1KR2J-1-GP

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG[3]

DY

0 : ENABLED
SET DFX ENABLED BIT

IN DEBUG INTERFACE MSR

1 : DISABLED

CFG4
R605
1KR2J-1-GP

DISPLAY PORT PRESENCE STRAP

CFG[4]

0 : ENABLED
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

CPU (CFG)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

of

A00
104

SSID = CPU

VCC_CORE
CPU1L

1D35V_S3
1D05S_VCCST

R703 1

2 75R2F-2-GP

VR_SVID_ALERT#

R704 1

2 130R2F-1-GP

H_CPU_SVIDDAT

VCC_CORE

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil

R702
100R2F-L1-GP-U

VCC_CORE

#487822

Layout Note:

[46]

VCC_SENSE
TP701

SCD1U16V2KX-3GP

C702

[46] H_VR_ENABLE

[96]

U701

R706

GND

DY 10KR2J-3-GP

DY

2 10KR2J-3-GP

PW R_DEBUG
2150R2J-L1-GP-U
RSVDP60
1
RSVDP61
1
RSVDN59
1
RSVDN61
1

PW R_DEBUG
1D05S_VCCST R705 1
TP702
TP703
TP704
TP705

NC#1 VCC

R710 1
IMVP_PW RGD_R

1D05S_VCCST

DY

R701
43R2J-GP
1
2H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
H_VCCST_PW RGD

[46] VR_SVID_ALERT#
[46] H_CPU_SVIDCLK
[46] H_CPU_SVIDDAT

3D3V_S5

1 TP_VCCIO_OUT
+VCCIOA_OUT

DY
4

H_VCCST_PW RGD [96]

EC701

DY

0R0603-PAD-1-GP-U

DY

Need to fine tune to 1.05V.

0.1A

2
1

DY

C703
SC1U10V2KX-1GP

1D05S_VCCST

R711

R709
47KR2F-GP

1D05S_VCCST
1D05V_S0

1
2
R707
100KR2F-L1-GP

SCD1U16V2KX-3GP
2

73.01G07.0HG

C701
SC22U6D3V5MX-2GP

74LVC1G07GW -GP

[36,48] 1D05V_VTT_PW RGD

VCC_CORE

L59
J58

12 OF 19

RSVD#L59
RSVD#J58

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

F59
N58
AC58

VCC
RSVD#N58
RSVD#AC58

E63
AB23
A59
E20
AD23
AA23
AE59

VCC_SENSE
RSVD#AB23
VCCIO_OUT
VCCIOA_OUT
RSVD#AD23
RSVD#AA23
RSVD#AE59

L62
N63
L63
B59
F60
C59

HSW_ULT_DDR3L

VIDALERT#
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

VSS
PWR_DEBUG#
VSS
RSVD_TP#P60
RSVD_TP#P61
RSVD_TP#N59
RSVD_TP#N61
RSVD#T59
RSVD#AD60
RSVD#AD59
RSVD#AA59
RSVD#AE60
RSVD#AC59
RSVD#AG58
RSVD#U59
RSVD#V59

AC22
AE22
AE23

VCCST
VCCST
VCCST

AB57
AD57
AG57
C24
C28
C32

VCC
VCC
VCC
VCC
VCC
VCC

HSW ULT POWER

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

HASW ELL-6-GP-U

EC702

R712
47KR2F-GP

IMVP_PW RGD_R

DY

SCD1U16V2KX-3GP
2

1
2
R713
100KR2F-L1-GP

[24,46] IMVP_PW RGD

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CPU (VCC CORE)

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

of

104

SSID = CPU

www.vinafix.vn

HSW_ULT_DDR3L

C
DP to VGA Converter

C54
C55
B58
C58
B55
A55
A57
B57

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

C51
C50
C53
B54
C49
B50
A53
B53

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

DDI

EDP

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

C45
B46
A47
B47

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

C47
C46
A49
B49

EDP_AUXN
EDP_AUXP

A45
B45

EDP_RCOMP
EDP_DISP_UTIL

D20
A43

EDP_TX0_DN
EDP_TX0_DP
EDP_TX1_DN
EDP_TX1_DP

[52]
[52]
[52]
[52]
+VCCIOA_OUT
R801
24D9R2F-L-GP

[55] PCH_DPB_N0
[55] PCH_DPB_P0
[55] PCH_DPB_N1
[55] PCH_DPB_P1

1 OF 19

Design Guideline:
EDP_COMP keep routing length max 100 mils.
Trace Width:20 mils.

EDP_AUX_DN [52]
EDP_AUX_DP [52]
EDP_COMP
EDP_BRIGHTNESS

CPU1A

TP801

HASW ELL-6-GP-U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

Document Number

CPU (DDI/EDP)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet

of

X02
104

SSID = CPU
D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

VSS_SENSE
1

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

HSW_ULT_DDR3L

HASWELL-6-GP-U

R901
100R2F-L1-GP-U

CPU1P

VSS_SENSE [46]

Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

CPU (VSS)

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

2

Sheet

of
1

A00
104

SSID = CPU

1D35V_S3

1
2

DY

Layout Note:

C1006
SC10U10V5KX-2GP

1
2

DY

C1005
SC10U10V5KX-2GP

1
2
1
2

DY

C1004
SC10U10V5KX-2GP

DY

C1020
SC2D2U6D3V2MX-GP

C1003
SC10U10V5KX-2GP

2
1

C1019
SC2D2U6D3V2MX-GP

DY
2

C1002
SC10U10V5KX-2GP

2
1

C1018
SC2D2U6D3V2MX-GP

2
1
2

C1017
SC2D2U6D3V2MX-GP

C1001
SC10U10V5KX-2GP

As close to CPU as possible

Layout Note:
Direct tie to CPU VccIn/Vss balls

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CPU (Power CAP1)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

10

A00
of

104

MAX: 1.92A
1.838A

42mA

+V1.05DX_MODPHY_PCH

1D05V_HSIO

57mA

C1125
SC10U10V5KX-2GP

C1112
SC10U10V5KX-2GP

SC1U10V2KX-1GP
2
1

1
2

1
2

SC1U10V2KX-1GP

1
2

1
2

SC1U10V2KX-1GP
2
1

C1115
SC10U10V5KX-2GP

SC1U10V2KX-1GP
2
1

1
2

C1114
SC10U10V5KX-2GP

CAP need close to pin AE8 J11

DY

C1122

DY

C1121
SCD1U16V2KX-3GP

0R0805-PAD-1-GP-U

C1120
SCD1U16V2KX-3GP

CAP need close to pin AE9

C1118

CAP need close to pin A20

DY

RTC_AUX_S5

2
C1117

DY

C1116

C1113

DY

0R0603-PAD-1-GP-U

DY

+V1.05S_CORE_PCH

R1105

1D05V_S0

1mA

C1119
SC10U10V5KX-2GP

+1.05M_ASW

1 R1104

SC1U10V2KX-1GP
2
1

1D05V_S0

+V1.05S_AXCK_DCB

CAP need close to pin J18

1.632A

1D05V_S0

68.2R21D.10R

C1108
SC10U10V5KX-2GP

CAP need close to pin AC9

658mA

IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL
L1104
1
2

2 IND-2D2UH-196-GP

68.2R21D.10R

SC1U10V2KX-1GP
2
1

31mA

DY
2

0R0603-PAD-1-GP-U
C1124
SC10U10V5KX-2GP

DY
2

C1110
SC10U10V5KX-2GP

1
2

CAP need close to pin AA21

1 R1103

L1103 1

C1111

C1109

DY

+V1.05S_AXCK_DCB

+V3.3A_PSUS

+V1.05S_APLLOPI

SC1U10V2KX-1GP
2
1

1 R1102

1D05V_S0
3D3V_S5_PCH

0R0603-PAD-1-GP-U

DY

185mA

+V1.05S_APLLOPI

DY

CAP need close to pin B11

62mA

1D05V_S0

+V1.05S_ASATA3PLL
C1107
SC10U10V5KX-2GP

CAP need close to pin B18

DY

C1123
SC10U10V5KX-2GP

CAP need close to pin K9 L10

C1104
SC10U10V5KX-2GP

SC1U10V2KX-1GP
2
1

DY

+V1.05S_AUSB3PLL

0R3J-0-U-GP

C1105

2 0R3J-0-U-GP

C1103

C1101

C1102

L1101

C1106
SC10U10V5KX-2GP

L1102

0R0805-PAD-1-GP-U

+V1.05S_ASATA3PLL

+V1.05S_AUSB3PLL

SC1U10V2KX-1GP
2
1

1D05V_HSIO

R1101

SC1U10V2KX-1GP

1D05V_HSIO

SC1U10V2KX-1GP
2
1

41mA

CAP need close to pin AG10

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CPU (Power CAP2)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

11

A00
of

104

SSID = MEMORY

M_A_DIMA_ODT0
M_A_DIMA_ODT1

126
1

M_VREF_CA_DIMMA
M_VREF_DQ_DIMMA

30

[4] DDR3_DRAMRST#

All VREF traces should

have width=20mil;
spacing=20 mil

0D675V_S0

Layout Note:

116
120

C1217
SCD1U16V2KX-3GP

DY

203
204

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

C1222

2
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C1221

C1220

C1209
SC10U10V5KX-2GP
2
1

SCD1U16V2KX-3GP

C1213
SC1U10V2KX-1GP

C1210

DY

DY

C1212
SC1U10V2KX-1GP

DY

DY

C1208
SC10U10V5KX-2GP
2
1

1D35V_S3

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

Q1202
2N7002K-2-GP

5V_S5

84.2N702.J31
2ND = 84.2N702.031

1D35V_S3

84.05067.031

R1205
[4] DDR_PG_CTRL

DDR_PG_CTRL_R

R1208
220KR2J-L2-GP

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

C1203

DY
1D35V_S3

77
122
125

SA0_DIMA
SA1_DIMA

C1207
SC10U10V5KX-2GP
2
1

12
29
47
64
137
154
171
188

197
201

M_A_DQS1
M_A_DQS3
M_A_DQS5
M_A_DQS6
M_A_DQS0
M_A_DQS2
M_A_DQS4
M_A_DQS7

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3D3V_S0

199

C1211

10
27
45
62
135
152
169
186

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

PCH_SMBDATA [18,62,96]
PCH_SMBCLK [18,62,96]

198

M_A_B_DIMM_ODT

[5] M_A_DQS[7:0]

M_A_DQS#1
M_A_DQS#3
M_A_DQS#5
M_A_DQS#6
M_A_DQS#0
M_A_DQS#2
M_A_DQS#4
M_A_DQS#7

SA0
SA1
NC#1
NC#2
NC#/TEST

200
202

Vth = 1V max.
D

DDR_VTT_PG_CTRL

DDR_VTT_PG_CTRL

R1206

2 66D5R2F-GP

M_A_DIMA_ODT0

R1207

2 66D5R2F-GP

M_A_DIMA_ODT1

[49]

[5] M_A_DQS#[7:0]

VDDSPD

M_A_DIMA_CLK_DDR1 [5]
M_A_DIMA_CLK_DDR#1 [5]

11
28
46
63
136
153
170
187

0R0402-PAD

Q1201 must use Vth=1V.

Q1201
DMN5L06K-7-GP

DY

R1204
2MR2-GP

SDA
SCL
EVENT#

102
104

Place these caps

close to VTT1 and
VTT2.

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DIMA_CLK_DDR0 [5]
M_A_DIMA_CLK_DDR#0 [5]

SCD1U16V2KX-3GP

Layout Note:

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

[5]
[5]

101
103

SCD1U16V2KX-3GP

1
1

1
2

C1215
SC1U10V2KX-1GP

DY

C1206

C1216
SC1U10V2KX-1GP

1
C1205
SC2D2U10V3KX-1GP

DY

1
2
1
2

C1214
SC1U10V2KX-1GP

0D675V_S0

SCD1U16V2KX-3GP

C1204

CK1
CK1#

BA0
BA1

[5]
[5]

M_A_DIMA_CKE0
M_A_DIMA_CKE1

Place these caps

close to VREF_DQ
M_VREF_DQ_DIMMA

CK0
CK0#

M_A_DIMA_CS#0
M_A_DIMA_CS#1

73
74

Layout Note:

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CKE0
CKE1

M_A_RAS# [5]
M_A_WE# [5]
M_A_CAS# [5]

114
121

TC1201
ST330U2VDM-4-GP

1
C1202
2

SCD1U16V2KX-3GP

2
C

C1218

SCD1U16V2KX-3GP

C1201

SCD1U16V2KX-3GP

Place these caps

close to VREF_CA

M_A_DQ13
M_A_DQ8
M_A_DQ14
M_A_DQ10
M_A_DQ9
M_A_DQ12
M_A_DQ15
M_A_DQ11
M_A_DQ29
M_A_DQ28
M_A_DQ30
M_A_DQ31
M_A_DQ25
M_A_DQ24
M_A_DQ27
M_A_DQ26
M_A_DQ44
M_A_DQ41
M_A_DQ43
M_A_DQ47
M_A_DQ45
M_A_DQ40
M_A_DQ42
M_A_DQ46
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ7
M_A_DQ21
M_A_DQ20
M_A_DQ17
M_A_DQ16
M_A_DQ18
M_A_DQ19
M_A_DQ22
M_A_DQ23
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ38
M_A_DQ37
M_A_DQ32
M_A_DQ35
M_A_DQ39
M_A_DQ62
M_A_DQ58
M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ59
M_A_DQ56
M_A_DQ57

CS0#
CS1#

110
113
115

Layout Note:

RAS#
WE#
CAS#

NP1
NP2

M_VREF_CA_DIMMA

NP1
NP2

SCD1U16V2KX-3GP

109
108

[5]
M_A_BS0
[5]
M_A_BS1
[5] M_A_DQ[63:0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

M_A_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

[5]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

Note:
SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

SCD1U16V2KX-3GP

[5] M_A_A[15:0]

R1201
0R0402-PAD
2

R1202
0R0402-PAD

DM1

SA0_DIMA
SA1_DIMA

DDR3-204P-48-GP-U

62.10017.P41

close to dimm
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

DDR3-SODIMM1

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

12

of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

(Reserved)DDR3-SODIMM2
Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

13

of

104

(Blanking)

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)_SODIMM _SODIMM4

Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

14

of
1

A00
104

SSID = CPU

PCH strap pin:

Port B Detected

DDPB_CTRLDATA

*
*

DDPC_CTRLDATA

Low = Disable Port B (default)

High = Enable Port B
Low = Disable Port C (default)
High = Enable Port C

The internal pull-down is disabled after PLTRST# deasserts

RN1501
SRN2K2J-1-GP

HSW_ULT_DDR3L

9 OF 19

4
3

CPU1I

1
2

3D3V_S0

B8
A9
C6

[52] L_BKLT_CTRL
[24] L_BKLT_EN
[52] EDP_VDD_EN

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

eDP SIDEBAND

DDPB_CTRLCLK
B9
C9 DDPB_CTRLDATA
D9
D11 DDPC_CTRLDATA 1

DGPU_HOLD_RST#
DGPU_PW R_EN

4
3

OPS

[20]

PIRQA#

SRN10KJ-5-GP
DGPU_PW ROK
100KR2J-1-GP

[20,24,62]

EC1501
3D3V_S0

RN1505

1
2
3
4

8
7
6
5

PIRQC#
PIRQD#
PIRQB#

CLK_PCIE_W LAN_REQ3#

INT_TP#_GPIO55

SC1KP50V2KX-1GP
2

UMA

R1509 1

TP1501
R1512
1 0R2J-2-GP
2
INT_TP#
[82,83] DGPU_PW R_EN
[73] DGPU_HOLD_RST#
[24,82,83] DGPU_PW ROK

SC1KP50V2KX-1GP
2

PIRQB#
PIRQC#
PIRQD#
PCI_PME#

U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4

PIRQA#/GPIO77
PIRQB#/GPIO78
PIRQC#/GPIO79
PIRQD#/GPIO80
PME#
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DISPLAY
PCIE

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

C5
B6
B5
A6

DDPB_HPD
DDPC_HPD
EDP_HPD

C8
A8
D6

TP1502

EE Note:
If layout is on constraint, please reserve TP for DDPC_CTRLCLK.

RN1503

1
2

PCH_DPB_AUXN [55]
C

PCH_DPB_AUXP [55]

CRT_PCH_HPD

[55]

EDP_HPD [52]

DY EC1502 DY
HASW ELL-6-GP-U

[18,58]

SRN10KJ-6-GP

3D3V_S0
B

R1510
10KR2J-3-GP

Cedar
CEDAR/JANUS_ID

[19]

CEDAR/JANUS_ID

R1511
10KR2J-3-GP

Janus

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

PCH ( EDP/GPIO/DDI )
Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

15

of

Rev

X02
104

SSID = PCH
HSW_ULT_DDR3L

CPU1K

F10
E10

[73] CPU_RXN_C_dGPU_TXN0
[73] CPU_RXP_C_dGPU_TXP0
C1606 1
C1605 1

[73] dGPU_RXN_C_CPU_TXN0
[73] dGPU_RXP_C_CPU_TXP0

2
2

[73] CPU_RXN_C_dGPU_TXN1
[73] CPU_RXP_C_dGPU_TXP1
C1608 1
C1607 1

[73] dGPU_RXN_C_CPU_TXN1
[73] dGPU_RXP_C_CPU_TXP1

2
2

[73] CPU_RXN_C_dGPU_TXN2
[73] CPU_RXP_C_dGPU_TXP2
C1610 1
C1609 1

[73] dGPU_RXN_C_CPU_TXN2
[73] dGPU_RXP_C_CPU_TXP2

2
2

[73] CPU_RXN_C_dGPU_TXN3
[73] CPU_RXP_C_dGPU_TXP3
C1612 1
C1611 1

[73] dGPU_RXN_C_CPU_TXN3
[73] dGPU_RXP_C_CPU_TXP3

2
2

[58] PCIE_PRX_W LANTX_N3

[58] PCIE_PRX_W LANTX_P3
[58] PCIE_PTX_W LANRX_N3_C
[58] PCIE_PTX_W LANRX_P3_C

C1601 1
C1602 1

2
2

[30] PCIE_PRX_LANTX_N4
[30] PCIE_PRX_LANTX_P4
C

C1603 1
C1604 1

[30] PCIE_PTX_LANRX_N4_C
[30] PCIE_PTX_LANRX_P4_C

+V1.05S_AUSB3PLL

2
2

SCD1U16V2KX-3GP
C23
OPS dGPU_RXN_CPU_TXN0
dGPU_RXP_CPU_TXP0 C22
OPS
SCD1U16V2KX-3GP
F8
E8
SCD1U16V2KX-3GP
dGPU_RXN_CPU_TXN1
OPS dGPU_RXP_CPU_TXP1 B23
A23
OPS
SCD1U16V2KX-3GP
H10
G10
SCD1U16V2KX-3GP
B21
OPS dGPU_RXN_CPU_TXN2
dGPU_RXP_CPU_TXP2
C21
OPS
SCD1U16V2KX-3GP
E6
F6
SCD1U16V2KX-3GP
B22
OPS dGPU_RXN_CPU_TXN3
dGPU_RXP_CPU_TXP3 A21
OPS
SCD1U16V2KX-3GP
G11
F11
SCD1U16V2KX-3GP
PCIE_PTX_W LANRX_N3
C29
PCIE_PTX_W LANRX_P3
B30
SCD1U16V2KX-3GP
F13
G13
SCD1U16V2KX-3GP
PCIE_PTX_LANRX_N4
B29
PCIE_PTX_LANRX_P4
A29
SCD1U16V2KX-3GP
G17
F17

R1601
3KR2F-GP
1
2

PCIE_RCOMP

PERN5_L0
PERP5_L0

USB2N0
USB2P0

AN8
AM8

USB_PN0 [34]
USB_PP0 [34]

PETN5_L0
PETP5_L0

USB2N1
USB2P1

AR7
AT7

USB_PN1 [34]
USB_PP1 [34]

PERN5_L1
PERP5_L1

USB2N2
USB2P2

AR8
AP8

USB_PN2 [63]
USB_PP2 [63]

PETN5_L1
PETP5_L1

USB2N3
USB2P3

AR10 USB_PN3
AT10 USB_PP3

USB2N4
USB2P4

AM15
AL15

USB_PN4 [52]
USB_PP4 [52]

PETN5_L2
PETP5_L2

USB2N5
USB2P5

AM13
AN13

USB_PN5 [58]
USB_PP5 [58]

PERN5_L3
PERP5_L3

USB2N6
USB2P6

AP11
AN11

USB_PN6 [52]
USB_PP6 [52]

PETN5_L3
PETP5_L3

USB2N7
USB2P7

AR13
AP13

USB_PN7 [63]
USB_PP7 [63]

USB3RN1
USB3RP1

G20
H20

USB3_PRX_CTX_N0 [34]
USB3_PRX_CTX_P0 [34]

USB3TN1
USB3TP1

C33
B34

USB3_PTX_CRX_N0 [34]
USB3_PTX_CRX_P0 [34]

USB3RN2
USB3RP2

E18
F18

USB3TN2
USB3TP2

B33
A33

GPU

PERN5_L2
PERP5_L2

PERN3
PERP3
PETN3
PETP3
PERN4
PERP4

WLAN

PCIE

LAN

PETN4
PETP4

USB

1
1

TP1601
TP1602

PETN1/USB3TN3
PETP1/USB3TP3

F15
G15

PERN2/USB3RN4
PERP2/USB3RP4

B31
A31

PETN2/USB3TN4
PETP2/USB3TP4

Pair

Device

USB3.0 port1

USB2.0 Port2 (Debug Port)

USB2.0 Port3 (IOBD)

CAMERA

WLAN

Touch Panel

Card Reader

PERN1/USB3RN3
PERP1/USB3RP3

C30
C31

E15
E13
A27
B27

USB 2.0 Table

11 OF 19

Layout Note:
USBRBIAS#
USBRBIAS
RSVD#AN10
RSVD#AM10

OC0/GPIO40#
OC1/GPIO41#
OC2/GPIO42#
OC3/GPIO43#

RSVD#E15
RSVD#E13
PCIE_RCOMP
PCIE_IREF

AJ10
AJ11
AN10
AM10

USB_COMP

AL3
AT1
AH2
AV3

USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7

1. USB_COMP using 50 ohm single-ended impedance

2. Isolation Spacing :15mil
3. Total trace length<500mil

1
2
R1602
22D6R2F-L1-GP

USB_OC#0_1 [18,35]
USB_OC#2_3 [35]
USB_OC#4_5 [20]

3D3V_S5_PCH
RN1601
USB_OC#2_3
USB_OC#6_7

HASW ELL-6-GP-U

Layout Note:

[18] MCP_GPIO73
[17] PM_SUSW ARN#_R

1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil

2. Isolation Spacing: 12mil
3. Total trace length<500mil

8
7
6
5

1
2
3
4
B

SRN10KJ-6-GP

#515621

PCIE Table
Port

Device

Share BUS

N/A

USB3.0_3

N/A

USB3.0_4

WLAN

LAN

5(L0~L3)

GPU

6(L3)

HDD

SATA0

6(L2)

ODD

SATA1

6(L0~L1)

N/A

GPU

GPU

GPU

GPU

<Core Design>

Wistron Corporation
GPU

GPU

GPU

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

GPU
Title
Size
A3
Date:

Document Number

PCH (PCIE/USB)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

16

of

A00
104

SSID = PCH

RN1703

1
2

R1717

PM_RSMRST#
PM_PCH_PW ROK

4
3
SRN10KJ-5-GP
1 10KR2J-3-GP

PCH strap pin:

SYS_PW ROK

DY

RTC_AUX_S5
R1720
330KR2J-L1-GP
1
2

On Die DSW VR Enable

DSW ODVREN

DSWVRMEN

Low = Disable
High = Enable (default)

DY

R1721
330KR2J-L1-GP

This signal has no integrated pull-up/pull-down.

3D3V_S0

R1701
10KR2J-3-GP

HSW_ULT_DDR3L

CPU1H

[96] XDP_DBRESET#
[24,96] SYS_PW ROK
[24,26,36] PCH_PW ROK

1 R1706 2
0R0402-PAD

PM_SUSACK#_R AK2
XDP_DBRESET#
AC3
SYS_PW ROK
AG2
PM_PCH_PW ROK AY7
MPW ROK
AB5
PCI_PLTRST#
AG7

1 R1707 2
0R0402-PAD

[16] PM_SUSW ARN#_R

[24,96] PM_PW RBTN#
[24,76] AC_PRESENT
[20]
BATLOW #

DSWVRMEN
DPWROK
WAKE#

AW7
AV5
AJ5

DSW ODVREN
PCH_DPW ROK
PCH_W AKE#

CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63

V5
AG4
AE6
AP5

PM_CLKRUN#
PM_SUS_STAT#1
SUS_CLK_PCH
PM_SLP_S5# 1

SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
SLP_LAN#

AJ6
AT4
AL5
AP4
AJ7

PM_SLP_S4#
PM_SLP_S3#
PM_SLP_A#
1
PM_SLP_SUS#
PM_SLP_LAN# 1

RSMRST#
SUSWARN#/SUSPWRDNACK#/GPIO30
PWRBTN#
ACPRESENT/GPIO31
BATLOW#/GPIO72
SLP_S0#
SLP_WLAN#/GPIO29

NON DS3
1
1

DY
R1705

2
2

0R2J-2-GP
1 R1709
TP1702 R1710
1
TP1703

PM_RSMRST#
PCIE_W AKE# [24,30]

R1705: DY for OBFF disable

2
2

0R0402-PAD
0R2J-2-GP

PM_CLKRUN#_EC [24]

SUS_CLK [24]

PM_SLP_S4# [24,49]
PM_SLP_S3# [24,36,48,49,51]
TP1704

PM_SLP_SUS# [24,38]

TP1707

DY DY

1
2

PCI_PLTRST#
HASW ELL-6-GP-U

0R0402-PAD
C1701
SC220P50V2KX-3GP

NON DS3

R1715
100KR2J-1-GP

PM_SUSW ARN#_R

MCP_GPIO12
AC_PRESENT

4
3

[24] PM_SUSACK#
[24] PM_SUSW ARN#

MCP_GPIO12 [20]

R1708
1
2
0R2J-2-GP
RN1702
2
1

PM_SUSACK#_R
PCH_DPW ROK

R1718 1

DS3 2

PM_SUSACK#_R
PM_SUSW ARN#_R

3
4

DS3

0R2J-2-GP

KBC_DPW ROK [24]

1 R1713

PLT_RST#

[24,30,36,52,58,65,73,96]

RN1701

R1704
0R2J-2-GP

SUSACK#
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK
PLTRST#

SCD1U16V2KX-3GP
2

DY

3D3V_S5

PM_RSMRST#
AW6
PM_SUSW ARN#_R AV4
PM_PW RBTN#
AL7
AC_PRESENT
AJ8
BATLOW #
AN4
PCH_SLP_S0#
AF3
PCH_SLP_W LAN# AM5

1
1

TP1706
TP1705

AC_PRESENT
EC1707

8 OF 19

SYSTEM POWER MANAGEMENT

DS3

SRN0J-6-GP

R1725
100KR2F-L1-GP
B

SRN10KJ-5-GP
R1703

PCH_W AKE#

2
1KR2J-1-GP

(CRB#514469)
3D3V_S5_PCH

3D3V_AUX_S5

3V_5V_POK# 5

SC1KP50V2KX-1GP
2

SC1KP50V2KX-1GP
2

EC1701
SC4D7P50V2CN-1GP
Q1701

SC1KP50V2KX-1GP
2

SC1KP50V2KX-1GP
2

SUS_CLK_PCH

NON DS3
R1726
10KR2J-3-GP

DY
DY
DY
DY
DY
EC1702
EC1703
EC1704
EC1705

SC1KP50V2KX-1GP
2

EC1706

XDP_DBRESET#
SYS_PW ROK
PLT_RST#
PCH_PW ROK
KBC_DPW ROK

PM_CLKRUN#
R1727
100KR2J-1-GP
1
2

PM_SUS_STAT#
2
10KR2J-3-GP

1KR2J-1-GP
R1702
PM_RSMRST# 1
2
R1728
3V_5V_POK_C 1
2

2N7002KDW -GP

NON DS3

RSMRST#_KBC [24]
3V_5V_POK [45]

0R2J-2-GP

DS3

R1729 1
0R2J-2-GP

PM_SLP_SUS#
<Core Design>

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Date:
4

Wistron Corporation

Size
A3
5

DY
1

DY

1
R1724

3D3V_S0
R1714
8K2R2F-1-GP
1
2

Document Number

PCH (PM)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

17

of

A00
104

SSID = PCH
C1801

R1810
XTAL24_IN

XTAL24_IN_R

0R0402-PAD
1

2
D

R1802
1MR2J-1-GP
MCP_GPIO76
PEG_CLKREQ#
CLK_PCIE_REQ#

82.30004.841
3

MCP_GPIO76 [20]

C1802

8
7
6
5

RN1801
1
2
3
4

XTAL24_OUT

HSW_ULT_DDR3L

CPU1F

X1801
XTAL-24MHZ-81-GP

1
3D3V_S0

1
SC15P50V2JN-2-GP

6 OF 19

SRN10KJ-6-GP

1
SC15P50V2JN-2-GP

CLK_PCIE_LAN_REQ4#

B38
C37
N1
A39
B39
U5

CLK_PCIE_REQ#

B37
A37
T2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3#/GPIO21

LAN

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4#/GPIO22

GPU

SIGNALS

RSVD#K21
RSVD#M21
DIFFCLK_BIASREF

XCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

C35
C34
AK8
AL8

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

AN15
AP15

CLK_PCI_LPC_R
CLK_PCI_KBC_R

CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P

+V1.05S_AXCK_LCPLL

R1803 1
RN1803
4
3

2 3KR2F-GP

1
RN1804
2
3
SRN10KJ-5-GP 4

R1804
R1805

DEBUG
1
1

2
1
SRN10KJ-5-GP

2 0R2J-2-GP
2 33R2J-2-GP

CLK_PCI_LPC
CLK_PCI_KBC

B35
A35

[65]
[24]

CLK_PCI_LPC_R

R1813

2 0R2J-2-GP

CLK_DP2VGA [55]

CRT_DEBUG

PCIE_CLK_XDP_N [96]
PCIE_CLK_XDP_P [96]

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5#/GPIO23

DY
2

CLOCK

WLAN

XTAL24_IN
XTAL24_OUT

K21
M21
C26

HASWELL-6-GP-U

DY

SC10P50V2JN-4GP
EC1802

PEG_CLKREQ#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2#/GPIO20

A25
B25

SC10P50V2JN-4GP
EC1801

[73] CLK_PCIE_VGA#
[73] CLK_PCIE_VGA
[73] PEG_CLKREQ#

CLK_PCIE_WLAN_REQ3#

C41
B42
AD1

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1#/GPIO19

XTAL24_IN
XTAL24_OUT

[30] CLK_PCIE_LAN_N4
[30] CLK_PCIE_LAN_P4
[20,30] CLK_PCIE_LAN_REQ4#

CLK_PCIE_REQ#

B41
A41
Y5

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0#/GPIO18

[58] CLK_PCIE_WLAN_N3
[58] CLK_PCIE_WLAN_P3
[15,58] CLK_PCIE_WLAN_REQ3#

C43
C42
U2

CLK_PCIE_REQ#

3D3V_S5_PCH

RN1807
[24,65] LPC_AD[3..0]

LPC_AD[3..0]

Based on the swap report.

CPU1G

HSW_ULT_DDR3L

SML1_CLK
SML1_DATA
SML0_DATA
SML0_CLK

7 OF 19

RN1806
LPC_AD2
LPC_AD1
LPC_AD3
LPC_AD0

8
7
6
5

1
2
3
4

LPC_LAD2_PCH
LPC_LAD1_PCH
LPC_LAD3_PCH
LPC_LAD0_PCH

LPC_LAD0_PCH
LPC_LAD1_PCH
LPC_LAD2_PCH
LPC_LAD3_PCH
LPC_LFRAME#_PCH

SRN0J-7-GP-U
R1801

[24,65] LPC_FRAME#
[24,25] SPI_CLK_R
[24,25] SPI_CS0#_R
[24,25] SPI_SI_R
[24,25] SPI_SO_R
[25]
SPI_WP#
[25]
SPI_HOLD#

LAD0
LAD1
LAD2
LAD3
LFRAME#

LPC
SMBUS

0R0402-PAD

33R2J-2-GP 1
0R0402-PAD 1

2 R1806 PCH_SPI_CLK
2 R1807 PCH_SPI_CS0#

0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD

2
2
2
2

1
1
1
1

AU14
AW12
AY12
AW11
AV12

R1808
R1809
R1811
R1812

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_DQ2
PCH_SPI_DQ3

AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1

SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

SPI

C-LINK

SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1ALERT#/PCHHOT#/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST#

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

MCP_GPIO11
SMB_CLK
SMB_DATA
CARD_PWR_EN
SML0_CLK
SML0_DATA
MCP_GPIO73
SML1_CLK
SML1_DATA

AF2
AD2
AF4

TP_CL_CLK 1
TP_CL_DATA1
TP_CL_RST# 1

8
7
6
5

1
2
3
4
SRN2K2J-4-GP

MCP_GPIO73 [16]
SML1_CLK [24,26,76]
SML1_DATA [24,26,76]

CARD_PWR_EN
[16,35] USB_OC#0_1
[20,24] EC_SCI#

TP1801
TP1802
TP1803

MCP_GPIO11

RN1809
SRN10KJ-6-GP
8
7
6
5

1
2
3
4

SRN2K2J-1-GP
SMB_CLK
SMB_DATA

3
4

2
1
RN1811

3D3V_S5

3D3V_S0
HASWELL-6-GP-U

2
1

RN1810
3
4

RN1802
SRN1KJ-7-GP

2
1

3D3V_S0

SRN10KJ-5-GP

3
4

2N7002KDW-GP
SMB_DATA
PCH_SPI_DQ3

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

PCH_SPI_DQ2

PCH_SMBDATA [12,55,62,96]

Q1801

PCH_SMBCLK [12,55,62,96]
SMB_CLK

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (CLOCK/SMBUS/CL/LPC/SPI)Rev

Size
Document Number
Custom
Date:
5

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

18

of

X02
104

SSID = CPU
RTC_X1
R1915

2
10MR2J-L-GP

RTC_X2

X1901

RTC_AUX_S5

RTC_AUX_S5
R1913

82.30001.841

PCH_INTVRMEN

330KR2J-L1-GP

Low = External VRs

High = Internal VRs*

DY

R1901
1MR2J-1-GP

2
1

INTVRMEN

R1903
330KR2J-L1-GP

Integrated SUS 1V VRM Enable

XTAL-32D768KHZ-65-GP

PCH strap pin:

RN1901
SRN20KJ-1-GP

3
4

RTC_X1
AW5
RTC_X2
AY5
SM_INTRUDER# AU6
PCH_INTVRMEN AV7
SRTC_RST#
AV6
RTC_RST#
AU7

G
1

(#514849)

HDA_BITCLK
HDA_SYNC
HDA_RST#
HDA_SDIN0

AW8
AV11
AU8
AY10
AU12
HDA_SDOUT
AU11
1TP_HDA_DOCK_EN# AW10
AV10
AY8

[27] HDA_SDIN0

Layout: Place at the open door area.

PCH strap pin:

TP1902

[27] HDA_CODEC_BITCLK

R1907

2 33R2J-2-GP

HDA_BITCLK

[27] HDA_CODEC_SYNC

R1908

2 0R0402-PAD

HDA_SYNC

[27,29] HDA_CODEC_RST#

R1911

2 0R0402-PAD

HDA_RST#
TP1901

Flash Descriptor Security Overide/

Intel ME Debug Mode
HDA_SDOUT

Low = Default
High = Enable

[27] HDA_CODEC_SDOUT

[24]

RTC

C1902
SC1U10V2KX-1GP

G1901

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31

GAP-OPEN

2N7002K-2-GP

SC1U10V2KX-1GP
C1901
2
1

RTCX1
RTCX2
INTRUDER#
INTVRMEN
SRTCRST#
RTCRST#

5 OF 19

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

J5
H5
B15
A15

SATA3_PRX_HDDTX_N0
SATA3_PRX_HDDTX_P0
SATA3_PTX_HDDRX_N0
SATA3_PTX_HDDRX_P0

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

J8
H8
A17
B17

SATA_PRX_ODDTX_N2
SATA_PRX_ODDTX_P2
SATA_PTX_ODDRX_N2
SATA_PTX_ODDRX_P2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

J6
H6
B14
C15

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

F5
E5
C17
D17

R1902
10KR2J-3-GP

HSW_ULT_DDR3L

CPU1E

Q1901
[24] RTCRST_ON

C1904
SC15P50V2JN-2-GP

C1903
SC15P50V2JN-2-GP

ME_UNLOCK

R1912

2 33R2J-2-GP

R1909

2 1KR2J-1-GP

HDA_SDOUT

PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TCK_JTAGX

The internal pull-down is disabled after

PLTRST# deasserts

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST#/I2S_MCLK#
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN#/I2S1_TXD#
HDA_DOCK_RST#/I2S1_SFRM#
I2S1_SCLK

SATA

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST#
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD#AL11
RSVD#AC4
JTAGX
RSVD#AV2

SATA_IREF
RSVD#L11
RSVD#K10
SATA_RCOMP
SATALED#

JTAG

EC_SMI#
V1
U1
MCP_GPIO36
V6
AC1

A12
L11
K10
C12
U3

[56]
[56]
[56]
[56]

HDD1

[56]
[56]
[56]
[56]

ODD
C

EC_SMI# [24]
SATA_ODD_PRSNT# [56]
CEDAR/JANUS_ID

+V1.05S_ASATA3PLL

[15]

SATA_IREF

1 R1904 2
0R0402-PAD

SATA_RCOMP
SATA_LED#

2
R1906
3KR2F-GP

Layout Note:

R1916
R1917
R1918
R1919

2
2
2
2

DY

PCH_JTAG_TDI
1
51R2J-2-GP
PCH_JTAG_TDO
1
51R2J-2-GP
PCH_JTAG_TMS
1
51R2J-2-GP
XDP_TCK_JTAGX
1
1KR2J-1-GP

DY
DY
DY

4mil trace at break-out and 3

12-15mil trace with <0.2 ohms
and length total <= 500mils.

HASW ELL-6-GP-U

1D05S_VCCST

3D3V_S0
RN1902

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K
to 10K
on the
motherboard. Either pull-up or pull-down is acceptable.

SATA_ODD_PRSNT# 1
2
EC_SMI#
3
MCP_GPIO36
4

8
7
6
5

SRN10KJ-6-GP
3D3V_S0
R1905

EC1901
1
2

HDA_CODEC_BITCLK

DY

SATA_LED#
R1920

PCH_JTAG_TCK
2
51R2J-2-GP

DY

DY

10KR2J-3-GP

SC10P50V2JN-4GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

PCH (RTC/SATA/HDA/JTAG)

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

19

of

Rev

A00
104

SSID = CPU

1D05S_VCCST

HSW_ULT_DDR3L

CPU1J

3D3V_S5

10 OF 19

R2018
1KR2J-1-GP

RN2006
1
2

BATLOW# [17]

MCP_GPIO76
2INT_TP#_GPIO8
MCP_GPIO12
DY
0R2J-2-GP MCP_GPIO15

[18] MCP_GPIO76
[15,24,62] INT_TP#
[17] MCP_GPIO12

SRN10KJ-5-GP

1 R2031

3D3V_S5_PCH
[56] SATA_ODD_DA#
[25] RTC_DET#

R2015
10KR2J-3-GP 1

INT_TP#_GPIO8

R2010
10KR2J-3-GP
1
2

RTC_DET#
MCP_GPIO27
MCP_GPIO28
MCP_GPIO26

INT_TP#_GPIO46

HSW
1 R2029

[76] GPU_EVENT#

0R0402-PAD
[21] HSIOPC

[24,75,76,83]

R2027

BATLOW#
MCP_GPIO27

4
3

R2028 1

GC6_FB_EN

[15,24,62]

TP2002
2 0R0402-PAD
1 R2030
INT_TP#

MCP_GPIO56
MCP_GPIO57
MCP_GPIO58
WLAN_PLT_RST#
MCP_GPIO44
GPU_EVENT_MCP#
BOARD_ID1
BOARD_ID2
BOARD_ID3
HSIOPC
MCP_GPIO13
MCP_GPIO14
1CAMERA_PWR_EN
GC6_FB_EN_MCP
2INT_TP#_GPIO46

BDW

0R2J-2-GP EC_SWI#
EC_SCI#
TP2001
1HDD_DEVSLP

[24] EC_SWI#
[18,24] EC_SCI#

HDA_SPKR

[27] HDA_SPKR

P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2

BMBUSY#/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

CPU/
MISC

GPIO

SERIAL IO

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

3D3V_S5_PCH

THRMTRIP#
RCIN#/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD#AF20
RSVD#AB21

GSPI0_CS#/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS#/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS#/GPIO93
UART0_CTS#/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST#/GPIO2
UART1_CTS#/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

PCH_THERMTRIP
H_RCIN#
INT_SERIRQ
PCH_OPIRCOMP

D60
V4
T4
AW15
AF20
AB21

1
1

DY

0R2J-2-GP

R2003
49D9R2F-GP

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

H_THERMTRIP# [36]
H_RCIN# [24]
INT_SERIRQ [24]

SATA_ODD_PWRGT

LPSS_GSPI0_MOSI_BBS0_R

Layout Note:
1.Referenced "continuous" VSS plane only.
2.Avoid routing next to clock pins or noisy
signals.
3. Trace width: 12~15mil
[56]4. Isolation Spacing: 12mil
5. Max length: 500mil

KB_DET# [62]
KB_LED_BL_DET [62]
DBC_EN [52]
PANEL_SIZE_ID [52]

3D3V_S0

H_RCIN#
[56] SATA_ODD_DA#
BLUETOOTH_EN [58]

I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL

INT_SERIRQ
KB_DET#

RN2002
SRN10KJ-6-GP
8
7
6
5

1
2
3
4

I2C1_SDA [62]
I2C1_SCL [62]

COLOR_ENGINE
LPSS_SDIO_D0_CMNHDR

3D3V_S0

TP2003

I2C0_SDA
I2C0_SCL
HSIOPC

HASWELL-6-GP-U

SRN10KJ-5-GP
RN2007
1
4
2
3
R2007 1

2
100KR2J-1-GP

R2013
10KR2J-3-GP

3D3V_S0

1
MCP_R

0R0402-PAD-1-GP 1
0R0402-PAD-1-GP 1
0R0402-PAD-1-GP 1
0R0402-PAD-1-GP 1

2 R2001 MCP_GPIO58
2 R2002 MCP_GPIO44
2 R2004 MCP_GPIO56
2 R2009 MCP_GPIO26

0R0402-PAD-1-GP 1
0R0402-PAD-1-GP 1

2 R2016 MCP_GPIO14
2 R2017 MCP_GPIO28

0R0402-PAD-1-GP 1

2 R2020 MCP_GPIO13

0R0402-PAD-1-GP 1

2 R2022 MCP_GPIO57

3D3V_S5_PCH
RN2012
SRN10KJ-6-GP
1
8
2
7
3
6
4
5

RN2008
I2C1_SDA
I2C1_SCL

4
3

EC_SWI#
RTC_DET#
WLAN_PLT_RST#

USB_OC#4_5

[16]

PCH strap pin:

NO REBOOT

1
2
3
4

DY

SRN10KJ-5-GP

3D3V_S0
RN2011
SRN10KJ-6-GP
8
7
6
5

1
2

PIRQA#
DBC_EN
BLUETOOTH_EN

CLK_PCIE_LAN_REQ4#
PIRQA# [15]

HDA_SPKR

[18,30]

3D3V_S0
1KR2J-1-GP
R2006
1
2

Low = Enable (Default)

High = Disable

DY

HDA_SPKR

The internal pull-down is disabled after

PLTRST# deasserts
3D3V_S0

BOARD_ID1

VRAM_2G

PCH strap pin:

3D3V_S0

R2023
10KR2J-3-GP

Top-Block Swap Override mode

2G

BOARD_ID1

SDIO_D0
/ GPIO66
R2024
10KR2J-3-GP

DY

High = Enable "Top-Block swap" mode

Low = Disable "Top-Block swap" mode (Default)

R2011
1KR2J-1-GP
LPSS_SDIO_D0_CMNHDR

The internal pull-down is disabled after PLTRST# deasserts

Need SW double confirm if that's needed Top-Block swap

VRAM_1G

1G

BIOS VRAM Size Strap pin

BIOS strap pin:

PCH strap pin:

3D3V_S5_PCH
3D3V_S0

OPS

R2005
10KR2J-3-GP

BOARD_ID2
0

DIS

BOARD_ID2
1

UMA

* Low = Disable Intel ME Crypto TLS (Default)

R2008
10KR2J-3-GP

R2014
1KR2J-1-GP
MCP_GPIO15

PCH strap pin:

3D3V_S0

Boot BIOS Strap Bit BBS

1

Boot BIOS
Destination

Low = SPI (Default)

High = LPC

3D3V_S0

DY

R2012
1KR2J-1-GP
LPSS_GSPI0_MOSI_BBS0_R

The internal pull-down is disabled after PLTRST# deasserts

BIOS strap pin:

N15S-GT

R2025
10KR2J-3-GP

Need double confirm, GPIO table set to GPI if that's needed PH or PL

BOARD_ID3
2

BIOS UMA/DIS Strap pin

DY

High = Enable Intel ME Crypto TLS

UMA

GPIO15

The internal pull-down is disabled after

RSMRST# deasserts.

BIOS UMA/DIS Strap pin

BIOS strap pin:

TLS Confidentiality

N15V-GM-S(DVC40/50)

N15S-GT (DVC70)

BOARD_ID3
A

R2026
10KR2J-3-GP

N15V-GM

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

CPU (GPIO/MISC)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

20

of

A00
104

SSID = CPU
3D3V_S5_PCH

DSW
1

+3.3A_DSW _PRTCSUS
+V1.05DX_MODPHY_PCH
HSW_ULT_DDR3L

CPU1M

1 R2105

+V1.05S_AIDLE

3D3V_S5_PCH

+V3.3A_1.5A_HDA

+V3.3A_DSW _P

C2116

3D3V_S5

3D3V_S0

+V3.3A_DSW _P

1 R2112
1

0R0402-PAD

1 TP_VCCAPLLOPI_VAL
+V1.05S_APLLOPI

Y20
AA21
W21

RTC_AUX_S5
HSIO

RTC

VCCSUS3_3
VCCRTC
DCPRTC

SPI

RSVD#Y20
VCCAPLL
VCCAPLL

VCCSPI

OPI

VCCASW
VCCASW
TP2107

TP2108

+V1.05A_VCCUSB3SUS

J13

VCCHDA

+V1.05A_USB2SUS

AH13

DCPSUS2

AC9
AA9
AH10
V8
W9

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

+V3.3A_PSUS
+V3.3A_DSW _P

0R0402-PAD
C2136
SCD1U16V2KX-3GP

HDA

AH14

+V3.3S_PCORE

C2123
SC10U6D3V3MX-GP

AH11
AG10
AE7

+VCCRTCEXT

1
2
C2110
SCD1U16V2KX-3GP

3D3V_S5

Y8
AG14
AG13

C2147
1D05V_S0

VRM
CORE

GPIO/LPC

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP#AG19
DCPSUSBYP#AG20
VCCASW
VCCASW
VCCASW
DCPSUS1#AD10
DCPSUS1#AD8

THERMAL SENSOR

VCCTS1_5
VCC3_3
VCC3_3

J11
+V1.05S_CORE_PCH Broadwell(#514849): No series resistors (0 ohm).
H11
Haswell(#486713):Series resistor:5 ohm.
H15
R2110
C2114
AE8
5D1R2F-GP
SC1U10V2KX-1GP
AF22
PCH_VCCDSW _R
AG19 +PCH_VCCDSW 1
2
1
2
AG20
BDW/HSW
AE9
+1.05M_ASW
AF9
C2101
AG8
TP2106
+V3.3A_DSW _P 1
+PCH_VCCDSW
AD10 +V1.05A_SUS_PCH 1
2
AD8
SCD47U6D3V2KX-GP
3D3V_S0
J15
WistronSKB: match Intel design_20130417
1D5V_S0
K14
(#489999_2013WW15)
K16

1 TP_V1.05S_SSCF100
1 TP_V1.05S_AXCK_DCB
1 TP_V1.05S_SSCFF
+V3.3A_PSUS

U8
T9

DCPSUS4

AB8 +V1.05A_AOSCSUS

TP2109

AC20 TP_V1.05S_APLLOPI
AG16
AG17

TP2105

+V3.3S_1.8S_LPSS_SDIO

LPT LP POWER
SUS OSCILLATOR

RSVD#AC20
VCC1_05
VCC1_05

USB2

1D05V_S0

HASW ELL-6-GP-U
1D05V_S0

+V1.05S_SSCFF

+V1.05S_SSCFF
1D05V_HSIO
R2122

Non-HSIO
0R5J-5-GP
+V3.3S_1.8S_LPSS_SDIO
R2123
1

1 R2103

DY
0R2J-2-GP
U2101

1
2
3
4

5V_S5
1D05V_S0

VDD
D#2
D#3
D#4

1D05V_HSIO

DY

GND
S#7
S#6
S#5

8
7
6
5

DY
2

74.59147.093

HSIO_OUT

R2114
1 0R5J-5-GP
2

C2141
SC4D7U6D3V3KX-GP

0R0402-PAD
C2104
SC1U10V2KX-1GP

DY
C2142
SC10U10V5KX-2GP

DY
2

SLG59M1470VTR-GP

3D3V_S0

HSIOPC_R

HSIOPC

[20]

SC1U10V2KX-1GP
C2138

1D05V_S0

0R0402-PAD

ON

1 R2118

VCCSDIO
VCCSDIO

TP2103
TP2104
TP2101

SERIAL IO

C2135
SC1U10V2KX-1GP

SC1U10V2KX-1GP
C2137

0R0402-PAD

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD#K18
RSVD#M20
RSVD#V21
VCCSUS3_3
VCCSUS3_3

+V1.05S_AXCK_LCPLL
+V1.05S_SSCF100
+V1.05S_SSCFF

+V1.05S_SSCF100

J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21

+V1.05S_AXCK_DCB

+V1.05S_SSCF100

1 R2117

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

C2128
SC1U10V2KX-1GP

1D05V_S0

SCD1U16V2KX-3GP

USB3

DCPSUS3

+V3.3A_1.5A_HDA

SC1U10V2KX-1GP

DY

TP2102

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

1 R2101

SC1U10V2KX-1GP

1 R2108 2
0R0603-PAD-1-GP-U

+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL

DY

SC1U10V2KX-1GP
C2105

0R0402-PAD

Intel Recommend

1D05V_S0

K9
L10
M9
N8
P9
B18
B11

13 OF 19

1 R2102

0R0603-PAD-1-GP-U

C2109

Document Number

CPU (POWER2)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

21

of

A00
104

SSID = PCH

CPU1Q

TP2201
TP2204

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
1TP_DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
1TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2

DC_TEST_C1_C2

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

17 OF 19

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

A3
A4

DC_TEST_A3_B3
TP_DC_TEST_A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

TP_DC_TEST_A60
DC_TEST_A61_B61
TP_DC_TEST_A62
TP_DC_TEST_AV1
TP_DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_AW63

TP2202

TP2203

1
1
1

TP2205
TP2206
TP2207

TP2208
C

HASWELL-6-GP-U

CPU1R

AT2
AU44
AV44
D15
F22
H22
J21

HSW_ULT_DDR3L

18 OF 19

RSVD#N23
RSVD#R23
RSVD#T23
RSVD#U10

RSVD#AT2
RSVD#AU44
RSVD#AV44
RSVD#D15

RSVD#AL1
RSVD#AM11
RSVD#AP7
RSVD#AU10
RSVD#AU15
RSVD#AW14
RSVD#AY14

RSVD#F22
RSVD#H22
RSVD#J21

N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14

HASWELL-6-GP-U

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (RSVD)

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

2

Sheet

22

of
1

A00
104

SSID = PCH

CPU1N

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

HSW_ULT_DDR3L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CPU1O

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

HSW_ULT_DDR3L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

15 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

HASW ELL-6-GP-U
HASW ELL-6-GP-U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

CPU(VSS)

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

23

of

A00
104

SSID = KBC

VBAT

3D3V_AUX_KBC
VBAT

20.0K

2.75V

X02

100.0K

33.0K

2.48V

X03

1
R2406
100KR2F-L1-GP

EC_AGND

DY
1

SCD1U16V2KX-3GP

C2411

2
SC2D2U10V3KX-1GP

SCD1U16V2KX-3GP C2410

DY

SCD1U16V2KX-3GP C2409

1
2

DY

SCD1U16V2KX-3GP C2408

Need very close to EC

DY

SCD1U16V2KX-3GP C2407

Layout Note:

SCD1U16V2KX-3GP C2406

SCD1U16V2KX-3GP

C2401

C2404

EC_VTT

0R0402-PAD

SCD1U16V2KX-3GP

1 R2401

SC2D2U10V3KX-1GP
C2405

C2402

1D05V_S0

47.0K

2.24V

100.0K

64.9K

2.0V

100.0K

76.8

1.87V

Reserved

100.0K

100.0K

1.65V

Reserved

100.0K

143.0K

1.358V

Reserved

100.0K

174.0K

1.204V

EC_AGND

Reserved

100.0K

215.0K

1.048V

100.0K

A00

PCB_VER_AD

MODEL_ID_DET

3D3V_AUX_KBC_VCC

R2405
10KR2F-2-GP

Cedar_UMA Cedar_OPSJanus_OPS

Reserved

R2403
2D2R3-1-U-GP

R2445
57K6R2F-GP

100.0K

X01

R2446
64K9R2F-1-GP

3.0V

MODEL_ID_DET(GPIO07)

VOLTAGE

R2407
100KR2F-L1-GP

C2403

DY
2

10.0K

R2404
64K9R2F-1-GP

PULL-HIGH RESISTOR

100.0K

PULL-LOW RESISTOR

X00

A00

0R0603-PAD-1-GP-U

PCB VERSION A/D(PIN98)

SCD1U16V2KX-3GP

1 R2402

VBAT

VBAT

EC_AGND

PULL-LOW RESISTOR

Janus-OPS
Janus-UMA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Cedar-OPS
CedarUMA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD

ECSCI#_KBC

0R0402-PAD-1-GP

2 R2408

ECSMI#_KBC

0R0402-PAD-1-GP

2 R2409

EC_SMI# [19]

ECSWI#_KBC

0R0402-PAD-1-GP

2 R2410

EC_SWI#

0R0402-PAD

1 R2450
0R2J-2-GP

PROCHOT_EC
LCD_TST_EN
TP_LID_CLOSE#_KBC
ECSWI#_KBC

70
69
67
68
119
120
24
28
26
123

DY

72
71
10
11
25
27

[62]
TPCLK
[62]
TPDATA
[36] ALL_SYS_PWRGD
[42] PWR_CHG_AD_OFF
[44] AD_IA_HW2
[52] BLON_OUT

GPIO17/SCL1/N2TCK
GPIO22/SDA1/N2TMS
GPIO73/SCL2/N2TCK
GPIO74/SDA2/N2TMS
GPIO23/SCL3/N2TCK
GPIO31/SDA3/N2TMS
GPIO47/SCL4A/N2TCK
GPIO53/SDA4A/N2TMS
GPIO51/TA3/N2TCK
GPIO67/SOUT1/N2TMS

LAD0/GPIOF1
LAD1/GPIOF2
LAD2/GPIOF3
LAD3/GPIOF4
LCLK/GPIOF5
LFRAME#/GPIOF6
LRESET#/GPIOF7

126
127
128
1
2
3
7

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

GPIOC6/F_CS0#
GPIOC7/F_SCK
GPIO30/F_WP#/RTS1#
GPIO41/F_WP#/PSL_GPIO41
GPIOC5/F_SDIO/F_SDIO0
GPIOC4/F_SDI/F_SDIO1
GPIO81/F_WP#/F_SDIO2
GPIO00/32KCLKIN/F_SDIO3

GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27/PSDAT2
GPIO50/PSCLK3
GPIO52/PSDAT3

[62]

3D3V_AUX_KBC
3D3V_AUX_KBC
RN2401
R2452
1KR2J-1-GP

BAT_SCL
BAT_SDA

LPC_AD[3..0]

[18,65]

CLK_PCI_KBC
LPC_FRAME#

[18]
[18,65]

90
92
109
80
87
86
91
77

EC_SPI_CS#_C
EC_SPI_CLK_C

2 R2419
2 R2420

1 33R2J-2-GP
1 33R2J-2-GP

BAT_IN#
EC_SPI_DI_C
EC_SPI_DO_C

2 R2422
2 R2423

1 33R2J-2-GP
1 33R2J-2-GP

SUSCLK_KBC

1 R2441

73
93
74

PSL_IN1#
PSL_IN2#
PSL_OUT#

29
85
122

ECSCI#_KBC
ECRST#

R2416

SPI_CS0#_R [18,25]
SPI_CLK_R [18,25]
CAP_LED# [62]
BAT_IN# [42,43,44]
SPI_SI_R [18,25]
SPI_SO_R [18,25]
PM_SUSACK# [17]
SUS_CLK [17]

PLT_RST# [17,30,36,52,58,65,73,96]

0R0402-PAD

[52] EC_BRIGHTNESS
[27] KBC_BEEP
[61] BATT_WHITE_LED#
[42] AC_IN_KBC#
[62] KB_BL_CTRL
[61] CHG_AMBER_LED#
[17] KBC_DPWROK

VD1_EN#

1KR2J-1-GP

104

[26] VD_IN1

ALL_SYS_PWRGD de-assert,
delay 100ms; SYS_PWROK assert.

R2411

[15,20,62]

DY

1 R2448

INT_TP#

3D3V_AUX_KBC

GPIO82/IOX_LDSH/VD_OUT1
GPIO84/IOX_SCLK/VD_OUT2

VSBY
VBKUP
VCORF
PECI
SERIRQ/GPIOF0
GPIO24
GPIO36/TB3/CTS1#

GPIO44/SCL4B
PSL_IN4#/GPI43
PSL_IN3#/GPI42
GPIO46/SDA4B/CIRRXM

TOUCH_PANEL_INTR_KBC#
INT_TP#_KBC
2 0R2J-2-GP
[58] E51_TxD
L_BKLT_EN_EC

8
30

[17] PM_CLKRUN#_EC
[27] AMP_MUTE#

124
121
111
9

GPIO77/SPI_MISO
GPIO76/SPI_MOSI
GPIO75/SPI_SCK
GPIO02/SPI_CS#

GPIO87/CIRRXM/SIN_CR
GPIO34/SIN1/CIRRXL

GPIO10/LPCPD#
GPIO85/GA20
GPIO83/SOUT_CR
GPIO65/SMI#

GND
GND
GND
GND
GND
GND

GPIO11/CLKRUN#
GPIO55/CLKOUT/IOX_DIN_DIO

AGND

EC_VBKUP
KBC_VCORF
PECI

[61]

1
INT_SERIRQ

[20]
[17]

21
20
17
23

PM_SLP_S4# [17,49]
BOOST_MODE# [44]
LID_CLOSE# [64]
ME_UNLOCK [19]

113
14

PCIE_WAKE# [17,30]
S5_ENABLE [36]

DY

5
18
45
78
89
116

1
2

R2443 1

2100KR2J-1-GP

2 10KR2J-3-GP
2 10KR2J-3-GP

DY

3D3V_S5

PSL_IN2#

LID_CLOSE#

R2421 1

USB_PWR_EN#

R2412 1

0R0402-PAD

2
H_PECI

R2429
43R2J-GP

[44]

[4]

1 R2430

AC_IN#

DY
DY

2100KR2J-1-GP
2100KR2J-1-GP

PSL_IN1#

0R0402-PAD

Layout Note:
3D3V_AUX_S5

D2401

R2432

RB751V-40-H-GP

TOUCH_PANEL_INTR#

PSL_OUT#

[52]

3D3V_AUX_S5

K
1

RB751V-40-H-GP

2 SCD1U16V2KX-3GP

KBC_ON#_GATE_L

KBC_ON#_GATE

R2433
20KR2F-L-GP

Q2402
DMP2130L-7-GP

DY

R2434
0R2J-2-GP

3D3V_AUX_KBC

DY
R2447
100KR2J-1-GP

C2417

84.02130.031
2ND = 84.03413.A31

D2402

0R0402-PAD

eDP backlight Control from PCH

1KR2J-1-GP

83.R2004.H8F

0R0402-PAD
R2435

071.00285.000G

L_BKLT_EN_EC

R2415 1

TOUCH_PANEL_INTR#

SC1U10V2KX-1GP

Need very close to EC

LID_CLOSE#
EC_AGND

103

R2444

FAN_TACH1

Touch Panel PH internally.

R2431
330KR2J-L1-GP

NPCE285PA0DX-GP

L_BKLT_EN

1 R2427

KBC_PWRBTN#

C2416

3D3V_AUX_S5
RTC_AUX_S5

RSMRST#_KBC

2 100KR2J-1-GP
2 10KR2J-3-GP

R2425
330KR2J-L1-GP

[20]

1 R2428 2
0R0402-PAD

ECSMI#_KBC

10KR2J-3-GP

[15]

3D3V_AUX_S5

Need very close to EC

H_RCIN#

75
114
44
13
125
6
15

DY

Power Switch Logic(PSL)

DY

GPIO80/VD_IN1

ECSCI#/GPIO54
EXT_RST#
KBRST#/GPIO86

2 0R2J-2-GP

R2453

84
83
82
79

[17,96] SYS_PWROK
[35] USB_PWR_EN#
[58] WIFI_RF_EN
[17] PM_SUSWARN#

LVDS backlight Control from PS8625

[52] TOUCH_PANEL_INTR#

110
112

[26] VD_OUT1#
[17,76] AC_PRESENT

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO45/E_PWM/DTR1#_BOUT1
GPIO40/F_PWM/1_WIRE/RI1#
GPIO66/G_PWM/PSL_GPIO66
GPO33/H_PWM/VD1_EN#

R2426 1

3D3V_S0

Layout Note:

SC100P50V2JN-3GP
C2422

1 R2449

32
118
62
65
22
16
81
66

R2413 1
R2414 1

AC_IN_KBC#

TP_LID_CLOSE#

3D3V_AUX_KBC

[62]

0R2J-2-GP

PM_SLP_S3#

AC_IN#
BAT_IN#

[17,36,48,49,51]

GPIO56/TA1
PSL_IN1#/GPI70
GPIO20/TA2/IOX_DIN_DIO
PSL_IN2#/GPI06/EXT_PURST#
GPIO14/TB1
PSL_OUT#/GPIO71
GPIO01/TB2

2 10KR2J-3-GP

DY C2415
SC220P50V2KX-3GP

OPS

31
117
63
64

DGPU_PWROK

DGPU_PWROK_KBC

R2418 1

[62]

3D3V_AUX_KBC

PLT_RST#_EC

[15,82,83]

2
1
SRN4K7J-8-GP

ECRST#
TP_ON#

0R0402-PAD
[26] FAN_TACH1
[17,96] PM_PWRBTN#

R2437

3
4

1 R2417

LCD_TST

[52] LCD_TST_EN
[62] TP_LID_CLOSE#

BAT_SCL
BAT_SDA

R2436
10KR2J-3-GP

83.R2004.H8F
Q2403

EC_AGND

Layout Note:

EC_GPIO47 High Active

Connect GND and AGND planes via either

0R resistor or connect directly.

DY

1
R2439
10KR2J-3-GP

ECRST#

DY

2N7002K-2-GP

E
H_PROCHOT#

DY

C2421
SC47P50V2JN-3GP

[4,42,44,46]

[26,36,76]

PURE_HW_SHUTDOWN#

B
Q2404
LMBT3906LT1G-1-GP

DY
2

C2418

1 R2440

0R0402-PAD

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

H_PROCHOT#_EC

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

1
2

DY

R2424
0R2J-2-GP

SC1U10V2KX-1GP

Q2401

R2442
100KR2J-1-GP

3D3V_AUX_S5

S5_ENABLE

R2438
0R2J-2-GP

PROCHOT_EC

[18,20]

[20]

[52]

[43,44] BAT_SCL
[43,44] BAT_SDA
[18,26,76] SML1_CLK
[18,26,76] SML1_DATA
[30] PM_LAN_ENABLE
[19] RTCRST_ON

EC_SCI#

101
105
106
107

KBSOUT0/GPOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TCK
KBSOUT2/GPIOB2/TMS
GPIO90/AD0
KBSOUT3/GPIOB3/TDI
GPIO91/AD1
KBSOUT4/GPOB4
GPIO92/AD2
KBSOUT5/GPIOB5/TDO
GPIO93/AD3
KBSOUT6/GPIOB6/RDY#
GPIO05/AD4
KBSOUT7/GPIOB7
GPIO04/AD5
KBSOUT8/GPIOC0
GPIO03/EXT_PURST#/AD6KBSOUT9/GPOC1/SDP_VIS#
GPIO07/AD7/VD_IN2
KBSOUT10/P80_CLK/GPIOC2
KBSOUT11/P80_DAT/GPIOC3
KBSOUT12/GPO64/TEST#
GPIO94/DA0
KBSOUT13/GP(I)O63/TRIST#
GPIO95/DA1
KBSOUT14/GP(I)O62/XORTR#
GPIO96/DA2
KBSOUT15/GPIO61/XOR_OUT
GPIO97/DA3
GPIO60/KBSOUT16/DSR1#
GPIO57/KBSOUT17/DCD1#

GC6_FB_EN_KBC

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

KCOL[0..16]

VTT

[26] FAN1_DAC_1
[44]
AD_IA_HW
[7,46] IMVP_PWRGD

DY

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

VDD

MODEL_ID_DET

97
98
99
100
108
96
95
94

PCB_VER_AD

[62]

3.0V
2.902V
2.801V
2.702V
2.598V
2.492V
2.402V
2.304V
2.201V
2.093V
2.001V
1.905V
1.808V
1.709V
1.594V
1.499V
1.392V
1.299V
1.099V
0.994V

[42]
PSID_EC
[17,26,36] PCH_PWROK
[17,38] PM_SLP_SUS#
[44] BOOST_MON
[76] OVER_CURRENT_P8#

1 R2451
0R2J-2-GP

GC6_FB_EN

2 SCD1U16V2KX-3GP

AVCC

KROW[0..7]

C2414

EC_AGND

ALL_SYS_PWRGD assert,
delay 10ms; PCH_PWROK assert.
[20,75,76,83]

12

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

DY

SCD1U16V2KX-3GP C2412

4
EC_VTT

AD_IA

54
55
56
57
58
59
60
61

102

[44]

KBSIN0/GPIOA0/N2TCK
KBSIN1/GPIOA1/N2TMS
KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
KBSIN6/GPIOA6
KBSIN7/GPIOA7

VOLTAGE

10.0K(64.10025.6DL)
13.7K(64.13725.6DL)
17.8K(64.17825.6DL)
22.1K(64.22125.6DL)
27.0K(64.27025.6DL)
32.4K(64.32425.6DL)
37.4K(64.37425.6DL)
43.2K(64.43225.6DL)
49.9K(64.49925.6DL)
57.6K(64.57625.6DL)
64.9K(64.64925.6DL)
73.2K(64.73225.6DL)
82.5K(64.82525.6DL)
93.1K(64.93125.6DL)
107K(64.10735.6DL)
120K(64.12035.6DL)
137K(64.13735.6DL)
154K(64.15435.6DL)
200K(64.20035.6DL)
232K(64.23236.6DL)

3D3V_S0

VCC
VCC
VCC
VCC
VCC

PULL-HIGH RESISTOR

100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K

KBC24

19
46
76
88
115

C2413
SC2D2U10V3KX-1GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A1
Date:
5

KBC Nuvoton NPCE885

Document Number
Janus HSW 40/50/70
Friday, February 07, 2014
1

Sheet

24

of

Rev

A00
104

SSID = Flash.ROM
SPI Flash ROM(8M) for PCH

4
3

C2502
SCD1U16V2KX-3GP

Single SPI shared flash connection (SPI Quad I/O mode)

1
2

DY

RN2501
SRN4K7J-8-GP

C2501
SC10U10V5KX-2GPDY

R2501
4K7R2J-2-GP

3D3V_S5

3D3V_S5

3D3V_S5

SPI25

72.25Q64.K01

EC2501
SC4D7P50V2CN-1GP

DY DY
2

W 25Q64FVSSIQ-GP

DY

SPI_HOLD# [18]
SPI_CLK_R [18,24]
SPI_SI_R [18,24]

VCC
HOLD#/IO3
CLK
DI/IO0

EC2502
SC4D7P50V2CN-1GP

CS#
DO/IO1
WP#/IO2
GND

8
7
6
5

1
2
3
4

[18,24] SPI_CS0#_R
[18,24] SPI_SO_R
[18]
SPI_W P#

EC2503
SC10P50V2JN-4GP

3D3V_S5

SKT25
SPI_CS0#_R
SPI_SO_R
SPI_W P#

1
2
3
4

DY

Source

8
7
6
5

SPI_HOLD#
SPI_CLK_R
SPI_SI_R

SKT-G6179HT0321-001-GP

62.10089.011

QUAD/DUAL fast read

DUAL fast read

72.25Q64.K01

72.25647.00A

072.25B64.0001

Refer to "NCPE985x/ NPCE995x board design reference guide"

SSID = RBATT
+RTC_VCC
B

AFTP2502

3D3V_AUX_S5

RTC_AUX_S5
B

1 +RTC_VCC
D2501

1
2
NP1
NP2

3
RTC_PW R

2
BAS40C-2-GP

DY

C2503
SCD47U6D3V2KX-GP

PWR
GND
NP1
NP2

R2502
1KR2J-1-GP
2
1

RTC1

75.00040.07D

BAT-060003HA002M213ZL-GP-U1

2nd = 75.00040.C7D

AFTP2501

3rd = 75.00040.A7D

62.70014.001
2nd = 62.70001.061
3rd = 20.F2316.002

Q2505

<Core Design>

R2504
10MR2J-L-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

Title
Size
A3
Date:

RTC_DET# [20]

Flash/RTC

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

25

of

104

SSID = Thermal
Fan controller1
5V_S0

T8
3D3V_S0

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

T8 C2602

SCD1U16V2KX-3GP

DY

74.02113.0E1

Layout Note:
THM_SML1_DATA

FAN1

[24]

1 R2606

FAN_TACH1

DY

DY

NCT7718W -GP

74.07718.0B9
R2601
0R2J-2-GP

DY

T8

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

3D3V_S0

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

DY
2

2N7002K-2-GP

[24,36,76]

1
R2612

DY

PURE_KBCT8

S
C2610
SCD1U16V2KX-3GP

THERM_SYS_SHDN#

PURE_HW _SHUTDOW N#

VD_OUT1#
0R2J-2-GP

EC2602

EC2601

DY

SC10P50V2JN-4GP

Layout Note:

1FAN_TACH1_C
1FAN_VCC1

FAN_VCC1

[17,24,36] PCH_PW ROK

AFTP2802
AFTP2801

FAN_TACH1

Q2602

C2812 close U2801

Layout Note:

DY

SCD1U16V2KX-3GP
2

2.System Sensor, Put on palm rest

AFTP2803

ALERT#
C2609
SCD1U16V2KX-3GP

NCT7718_DXN

20.F1841.003
2nd = 20.F1295.003

THM_SML1_CLK
THM_SML1_DATA

C2607
SC2200P50V2KX-2GP
T_CRIT#

8
7
6
5

C2608
SCD1U16V2KX-3GP

T8

DY

4
ETY-CON3-8-GP

83.R5003.H8H

VDD
SCL
D+
SDA
T8 ALERT#
DT_CRIT#
GND

1
C2606
SC470P50V3JN-2GP

1
2
3
4

DY

THM26

LMBT3904LT1G-GP

Q2603

2
1
C2603
SC2200P50V2KX-2GP

DY

Signal Routing Guideline:

Trace width = 15mil

RB551V30-GP

Layout Note:

C2604
SC4D7U6D3V3KX-GP

D2601

NCT7718_DXP

3
2

THM_SML1_CLK

84.T3904.H11

T8

FAN_TACH1_C

0R0402-PAD
FAN_VCC1

Q2601

[18,24,76] SML1_CLK

Need 10 mil trace width.

1
2

DY

C2601
SC10U6D3V3MX-GP

[18,24,76] SML1_DATA

AP2113MTR-G1-GP

4
3

2N7002KDW -GP

RN2602
SRN2K2J-1-GP

8
7
6
5

GND
GND
GND
GND

FAN1_DAC_1

FON#
VIN
VOUT
VSET

C2611
SC4D7U6D3V3KX-GP

1
2
3
4

FAN_VCC1

1
2

[24]

FON#

DY

5V_S0

3D3V_S0

FAN261

C2605
SCD1U16V2KX-3GP

3D3V_S0

R2605
0R2J-2-GP
1
2

R2603

R2604

T8

2 18K7R2F-GP

ALERT#

T8

2 2KR2F-3-GP

T_CRIT#

3D3V_AUX_KBC
R2607
THERM_SYS_SHDN#

T8

2 2KR2F-3-GP

T8

R2602

VD_OUT1# [24]

0R2J-2-GP

Close to KBC
VD_IN1 for system thermal sensor

Close to Thermal sensor

R2608
24K9R2F-L-GP

1
2

DY

3D3V_AUX_KBC

R2609
24K9R2F-L-GP

3D3V_AUX_S5

VD_IN1

[24]

<Core Design>

C2612
SCD1U16V2KX-3GP

VD_IN1_C

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

SC100P50V2JN-3GP
Title

1 R2611 2
0R0402-PAD

Size
A3
Date:
5

Wistron Corporation

C2613

R2610
NTC-100K-8-GP

THERMAL NCT7718W/Fan
Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

Rev

A00
26

of

104

www.vinafix.vn

SSID = AUDIO

MIC2_VREFO

[29] LINE1_VREFO_R

AUD_AGND

ALC3234-CG-GP

25

26

MIC2/LINE2_JD/JD2
HP/LINE1_JD/JD1

22

0R0805-PAD-1-GP-U

Place close to Pin 26

AUD_AGND

LINE1_L

21

LINE1_R

20

V3D3_STB

19

AUD_AGND

MIC_CAP

C2713

[29]

3D3V_S5

[29]

17

2 SC10U6D3V3MX-GP

SLEEVE

[29]

RING2

[29]

0R2J-2-GP

JDREF

R2707 1

DY

AUD_AGND

Layout Note:
Width>40mil, to improve Headpohone Crosstalk noise
Change it to sharp will be better.
Add 2 vias (>0.5A) when trace layer change.

16
15

Layout Note:
Tied at point only under
Codec or near the Codec

R2712 1

18

2 R2706

Layout Note:

C2711

0R0603-PAD-1-GP-U

23

2 20KR2F-L-GP

AUD_AGND

14
13

PCBEEP

GND

AUD_AGND

SPDIFO/FRONT_JD/JD3/GPIO3

RESET#

49

SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SCD1U25V2KX-GP
SC1KP50V2KX-1GP
SCD1U25V2KX-GP

+3V_AVDD
AUD_SENSE_A

2
R2709
200KR2F-L-GP

AUD_SENSE

AUD_SENSE

R2722

[29]
AUD_SENSE_A

Layout Note:
Place close to Pin 13

12

SPDIF-OUT/GPIO2

24

C2710

AVSS1

AVDD1

28

29

27
LDO1-CAP

VREF

30

MIC2-VREFO

31
LINE1-VREFO-L

LINE1-VREFO-R

HPOUT-L/PORT-I-L

32

33
HPOUT-R/PORT-I-R

34
CPVEE

35

PDB

11

Close pin40

PVDD2

SYNC

48

DVDD-IO

47

10

EAPD#
COMBO-GPI

SDATA-IN

0R0402-PAD

MONO-OUT

1 R2708

[24] AMP_MUTE#

MIC2_L/PORT-F-L/RING

SPK-OUT-R+

C2715
SC4D7U6D3V3KX-GP

SPK-OUT-R-

LDO3-CAP

46

MIC2_R/PORT-F-R/SLEEVE

BCLK

45

NC#20
MIC-CAP

SPK-OUT-L-

SDATA-OUT

44

AUD_SPK_R+

LINE2_L/PORT-E-L

SPK-OUT-L+

71.03234.003

DY

5V_S0

AUD_AGND

PVDD1

AUD_SPK_R-

DY
DY

AUD_AGND

LINE1_L/PORT-C-L

43

2
2
2
2
2

R2703

LINE1_R/PORT-C-R

DVSS

2 0R2J-2-GP

DY

42

AUD_SPK_L-

+5V_PVDD
1

R2710 1

[29] AUD_SPK_R+

AUD_SPK_L+

1
1
1
1
1

+5V_AVDD

+5V_AVDD

LINE2_R/PORT-E-R

AVDD2

[29] AUD_SPK_R+3V_1D5V_AVDD
20R0402-PAD

LDO2-CAP

41

[29] AUD_SPK_L-

39
40

+5V_PVDD
[29] AUD_SPK_L+

Speaker trace width >40mil @ 2W4ohm speaker power

R2705 1

LDO2_CAP

GPIO1/DMIC-CLK

2 SC10U6D3V3MX-GP

AVSS2

+3V_1D5V_AVDD

Layout Note:

1D5V_S0

36
CPVDD

C2712

AUD_AGND

moat

CBP

38

GPIO0/DMIC-DATA

Close pin46

37

DVDD

Layout Note:

Close pin41

CBP
AUD_AGND

Layout Note:

CBN

HDA27

SCD1U16V2KX-3GP

1
2

C2709

C2708
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

1
2

C2707

C2706

SC4D7U6D3V3KX-GP

1 R2704

0R0805-PAD-1-GP-U

EC2707
EC2706
EC2705
EC2704
EC2703

moat

0R0805-PAD-1-GP-U

3D3V_S0

R2711
100KR2J-1-GP

SC4D7U6D3V3KX-GP

R2702
1

moat

Reserved for ALC3234

SCD1U16V2KX-3GP

+5V_PVDD

+3V_AVDD
C2703
SC1U10V2KX-1GP

CPVEE

Close pin36
CBN

1.5A

C2701
SC4D7U6D3V3KX-GP
1

SC1U10V2KX-1GP
C2704
1
2

0R0402-PAD

5V_S0

[29] AUD_HP1_JACK_R

LDO1_CAP

+3V_AVDD

AUD_VREF

[29] AUD_HP1_JACK_L

25mA
1 R2701

1 C2705
SC2D2U6D3V2MX-GP
1
C2702
SC4D7U6D3V3KX-GP

[29] LINE1_VREFO_L

3D3V_S0

[29]

1
100KR2J-1-GP

moat

2
C2723
SC22P50V2JN-4GP

[19] HDA_CODEC_SDOUT

DY

[19] HDA_CODEC_BITCLK

[19] HDA_SDIN0

Close pin3

[19] HDA_CODEC_SYNC
[19,29]

HDA_CODEC_RST#

1 R2714
0R0402-PAD
0R2J-2-GP
1 R2716

DMIC_DATA_R

DMIC_CLK_R

0R0402-PAD 1 R2719

CODEC_SDOUT_R

0R2J-2-GP
1 R2720

CODEC_BITCLK_R

0R0402-PAD 1 R2718

HDA_CODEC_SDIN0

1
2

C2719

+3V_AVDD

C2717

AUD_PC_BEEP

SCD1U16V2KX-3GP

[52] DMIC_DATA
[52] DMIC_CLK

1
2

C2716
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

DY

DY

SCD1U16V2KX-3GP
2

1
SCD1U16V2KX-3GP
2

DY

EC2709

SC10P50V2JN-4GP
EC2701

HDA_CODEC_SDOUT
HDA_CODEC_BITCLK
EC2708

SCD1U16V2KX-3GP

TP2702
DMIC_DATA_R

Azalia I/F EMI

LDO3_CAP
C2718

+3V_AVDD

HDA_CODEC_SYNC
HDA_CODEC_RST#
D2701
RN2701
2
1

[20] HDA_SPKR
[24]
KBC_BEEP

HDA_SPKR_R

KBC_BEEP_R

3
4

AUD_PC_BEEP_C

C2720
1
2AUD_PC_BEEP
SCD1U16V2KX-3GP

SRN0J-6-GP

BAT54C-7-F-3-GP

R2717
1KR2J-1-GP
2

75.00054.E7D
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

Audio Codec ALC3234

Document Number

Sheet
1

27

Rev

A00

Janus HSW 40/50/70

Monday, February 10, 2014

of

104

(Blanking)

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Reserved

Sheet

28

A00
of

104

SSID = AUDIO
Speaker

Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power

SPK1

[27] AUD_SPK_R+

0R0603-PAD-1-GP-U 2

1 R2904 AUD_SPK_R+_C

[27] AUD_SPK_R[27] AUD_SPK_L+

[27] AUD_SPK_L-

0R0603-PAD-1-GP-U 2
0R0603-PAD-1-GP-U 2
0R0603-PAD-1-GP-U 2

1 R2903 AUD_SPK_R-_C
1 R2902 AUD_SPK_L+_C
1 R2901 AUD_SPK_L-_C

2
3
4

20.F1639.004
1

2nd = 20.F1804.004

DY

CONN Pin

Net name

Pin1

SPK_R+

Pin2

SPK_R-

Pin3

SPK_L+

Pin4

SPK_L-

SC2K2P50V3KX-GP
EC2904

DY
2

1
2

DY

SC2K2P50V3KX-GP
EC2903

1
2

DY

SC2K2P50V3KX-GP
EC2902

SC2K2P50V3KX-GP
EC2901

ACES-CON4-29-GP

AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C

AFTP2901
AFTP2902
AFTP2903
AFTP2904

1
1
1
1

AUD_PORTA_L_R_B 1
AUD_PORTA_R_R_B 1
1
AUD_SENSE
1

RN2901

3D3V_S0

DY

3
1

1 R2909
1 R2911

JACK_PLUG
JACK_PLUG_DET
AUD_PORTA_R_R_B
SLEEVE_R

5
6
2
4
MS

R2914
10KR2J-3-GP

RING2_R
AUD_PORTA_L_R_B

AUD_DELAY

JACK_PLUG_DET
10 mils

0R0402-PAD
R2916

AUDIO-JK430-GP

022.10002.0001

DY

DY

DY

1
2

DY

R2919
10KR2J-3-GP

SLEEVE

0R0603-PAD-1-GP-U 2
0R0603-PAD-1-GP-U 2

1 R2906
1 R2907

EC2905

AUD_HP1_JACK_R1
SC100P50V2JN-3GP

2 10R2F-L-GP
2 1KR2J-1-GP
2 4K7R2J-2-GP

EC2906

R2910 1
R2921 1
R2913 1

0R0603-PAD-1-GP-U 2
0R0603-PAD-1-GP-U 2

SC100P50V2JN-3GP

AUD_HP1_JACK_L1

EC2907
SC100P50V2JN-3GP

2 LINE1-L_R
SC4D7U6D3V3KX-GP

2 10R2F-L-GP
2 1KR2J-1-GP
2 4K7R2J-2-GP

R2920
10KR2J-3-GP

[27]

C2908 1

2 LINE1-L_C
SC4D7U6D3V3KX-GP

R2908 1
R2922 1
R2912 1

EC2908
SC100P50V2JN-3GP

[27] AUD_HP1_JACK_R
[27]
LINE1_R
[27] LINE1_VREFO_R

C2907 1

Combo Jack
HPMIC1

SRN2K2J-1-GP

[27]
RING2
[27] AUD_HP1_JACK_L
[27]
LINE1_L
[27] LINE1_VREFO_L

4
3

AFTP2906
AFTP2907
AFTP2908
AFTP2909

1
2

[27] MIC2_VREFO

AUD_AGND

NON_DELAY

AUD_AGND

DY

AUD_AGND

AUD_AGND

Delay circuit

AUD_AGND

AUD_AGND
10 mils

AUD_DELAY
C2902
SC10U6D3V3MX-GP
Q2901
2N7002K-2-GP
AUD_AGND

R2905
100KR2J-1-GP

AUD_DELAY

JACK_PLUG

84.2N702.J31
2ND = 84.2N702.031

AUD_AGND

D
R2923

DY

SLEEVE_CTRL

G
D

4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F

DY

D
G

R2917

1
DY
0R3J-0-U-GP

<Core Design>
HDA_CODEC_RST#

Wistron Corporation

SLEEVE [27]

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

DY
2N7002KDW -GP

Title

C2901
SC1U10V2KX-1GP

Speaker/HPMIC
Size
A3
Date:

[19,27]

MUTE_CTRL

AUD_SENSE [27]

NON_DELAY

AUD_AGND

10 mils

0R0603-PAD-1-GP-U

U2901

2
1

2
1

2
1

2
1

2
1

DY

AZ2025-01H-R7G-GP
ED2905

DY

AZ2025-01H-R7G-GP
ED2904

DY

AZ2025-01H-R7G-GP
ED2903

moat

DY

AZ2025-01H-R7G-GP
ED2902

DY

AZ2025-01H-R7G-GP
ED2901

R2918
100KR2J-1-GP

R2915
470KR2J-2-GP

DY

AUD_DELAY

+3V_AVDD

5V_PW R_2

AUD_PORTA_R_R_B
AUD_PORTA_L_R_B
RING2_R
AUD_SENSE
SLEEVE_R

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

A00
29

of

104

Layout:
For RTL8111G(S)
* Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30
For RTL8106E
* Place C3021,C3022 close to each VDD10 pin-- 8, 30

C3021: colse to Pin8

C3022 close to Pin30
C3023: close to Pin3
C3024: close to Pin22

R3001

RTL8111GUS-CG

RTL8111G-CGT

RTL8106EUS-CG

RTL8106E-CG

71.08111.W03

71.08111.U03

71.08106.003

071.08106.0003

SWR mode

LDO mode

SWR mode

LDO mode

10/100/1000M

10/100/1000M

10/100M

10/100M

LAN_MDI1P
LAN_MDI1N
LAN_MDI2P
LAN_MDI2N

3D3V_LAN_S5
RSET
VDD10
LANXOUT
LANXIN
VDD10

(NC) REGOUT
(DVDD33) VDDREG
(NC) DVDD10
LANWAKE#
71.08111.U03 ISOLATE#
(071.08106.0003)
PERST#
HSON
HSOP

MDIP0
MDIN0
AVDD10 (NC)
MDIP1
MDIN1
MDIP2 (NC)
MDIN2 (NC)
AVDD10

X5R
RTL8111G-CGT-1-GP-U1

3D3V_LAN_S5
3D3V_LAN_S5

[31]
[31]

1
2

84.T3904.H11
Q3003
E

DY

C3018 1
REGOUT
VDDREG
C3025 1
VDD10
PCIE_WAKE#
ISOLATE#
PLT_RST#_LAN
LAN_TXN_C_PCH_RXN4
LAN_TXP_C_PCH_RXP4

2
SC1U10V2KX-1GP
2 SCD1U16V2KX-3GP
PCIE_WAKE#

LMBT3904LT1G-GP
PLT_RST#_LAN
C

3D3V_S0

[17,24]
2

1
R3014
1KR2J-1-GP

R3015
15KR2J-1-GP

3D3V_S5
R3033
PCIE_WAKE#

2
10KR2J-3-GP

3D3V_LAN_S5

Layout:
C3004: close to Pin32
C3005: close to Pin11

3D3V_LAN_S5

PLT_RST#

24
23
22
21
20
19
18
17

071.08106.0003(DVC)/71.08111.U03(DVJ)
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
RTL8106E-CG (071.08106.0003): 10/100M <70mW.

3D3V_LAN_S5
CLK_LAN_REQ4#_R
PCIE_PTX_LANRX_P4_C
PCIE_PTX_LANRX_N4_C
CLK_PCIE_LAN_P4
CLK_PCIE_LAN_N4

DY
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

BQ402_1 4
3

DY

[17,24,36,52,58,65,73,96]

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

LAN_MDI3P
LAN_MDI3N

C3005

RN3001
SRN10KJ-5-GP

C3004

DY

TP3003
TP3002
TP3001

[16]
[16]

[18]
[18]

[31]
[31]
[31]
[31]

1
2
3
4
5
6
7
8

VDD10

LED0 1
LED1 1
LED2 1

9
10
11
12
13
14
15
16

SC4D7U6D3V3KX-GP

LAN_MDI0P
LAN_MDI0N

PCIE_PTX_LANRX_P4_C
PCIE_PTX_LANRX_N4_C

MDIP3 (NC)
MDIN3 (NC)
AVDD33 (NC)
CLKREQ#
HSIP
HSIN
REFCLK_P
REFCLK_N

C3010

[31]
[31]

C3016
PCIE_PTX_LANRX_P4_C
PCIE_PTX_LANRX_N4_C

PCIE_PRX_LANTX_P4 [16]
PCIE_PRX_LANTX_N4 [16]

LAN_SW
2

C3009

LAN_SW

C3008: close to Pin32

C3007: close to Pin11
C3003: close to Pin23

SCD1U16V2KX-3GP
2
1

1
2

8106E

0R0603-PAD-1-GP-U
C3003
SCD1U16V2KX-3GP

C3008
SCD1U16V2KX-3GP

C3007
SCD1U16V2KX-3GP

GND

VDDREG
R3006

40 mils

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

32
31
30
29
28
27
26
25

LOM30
33

3D3V_LAN_S5

C3014
LAN_TXP_C_PCH_RXP4
1
LAN_TXN_C_PCH_RXN4
1

CLK_PCIE_LAN_P4
CLK_PCIE_LAN_N4

Layout:
For RTL8111G(S)
* Place C3007 and C3008 close to each VDD33 pin-- 11, 32
For RTL8106E
* Place C3003 and C3008 close to each VDD33 pin-- 23, 32

8111G/LAN_SW

R3032
2K49R2F-GP
2

AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
(GPO) LED1/GPO
(LED1) LED2

1
2

1
2

1
2

1
2

C3024 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

LAN CHIP (10/100/1000M & 10/100M co-lay)

C3023 SCD1U16V2KX-3GP

68.4R71E.10G

C3022 SCD1U16V2KX-3GP

LAN_SW

C3021 SCD1U16V2KX-3GP

C3019 SCD1U16V2KX-3GP

8111G

8111G/LAN_SW

LAN_SW

2
IND-4D7UH-242-GP

LAN_SW

0R3J-0-U-GP

8111G
L3001
1

8111G/LAN_SW

VDD10

SC4D7U6D3V3KX-GP C3012
2
1

REGOUT
C3002,R3001:
Only for
RTL8111 LDO mode.
C3002

X3001
XTAL-25MHZ-181-GP

84.02130.031
2nd = 84.00102.031

DY
2

PM_LAN_ENABLE_R

2
20KR2J-L2-GP

2
LAN_ENABLE_R_C

SCD1U16V2KX-3GP

[18,20]
C3015
SC1U10V2KX-1GP

C3001
1

LANXIN

DY 10KR2J-3-GP

LMBT3904LT1G-GP
CLK_LAN_REQ4#_R
E

CLK_PCIE_LAN_REQ4#

DY

C3017
SCD1U16V2KX-3GP

Q3001

R3023
100KR2J-1-GP

R3021
10KR2J-3-GP
R3022

[24] PM_LAN_ENABLE

84.T3904.H11
Q3002

C3013

82.30020.G71

R3004

4
3D3V_LAN_S5

Q3004
DMP2130L-7-GP

85mA

DY
CLK_LAN_REQ#_EN

3D3V_LAN_S5 rise time must be controlled

between 0.5 mS and 100 mS.

3D3V_S5

R3003
10KR2J-3-GP

SC15P50V2JN-2-GP

C3011
1

LANXOUT

2
0R0603-PAD

R3016
1

1 R3005
2

0R0402-PAD
SC15P50V2JN-2-GP

3rd = 84.03413.B31

S
2N7002K-2-GP

1.0V Source

RTL8111G-CGT
(71.08111.U03)

RTL8111GUS-CG
(71.08111.W03)/
RTL8106EUS-CG
(71.08106.003)

RTL8106E-CG
(071.08106.0003)

LDO

SWR

R3001 C3002 C3023 C3024 C3007 L3001 C3012 C3019 C3009 C3010 C3003

X
<Core Design>

LDO

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:

LAN RTL8111/RTL8106

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

30

of

104

SSID = LOM

LAN TransFormer (10/100/1000M & 10/100M co-lay)

U3101

[30]

[30]

LAN_MDI3P

LAN_MDI2N

LAN_MDI2P

12
1
EC3108

3
11

1
EC3107

DY2SC10P50V2JN-4GP

1
EC3106

2
SC10P50V2JN-4GP

DY

1
EC3105

DY2SC10P50V2JN-4GP

MCT0

10/100/1000

1CT:1CT

MDO3+

MDO2-

4
7

MCT1
MDO2+

LOM_TCT

[30]

[30]

LAN_MDI0N

LAN_MDI0P

2
4

8
1
EC3103

DY2SC10P50V2JN-4GP

1
EC3102

DY2SC10P50V2JN-4GP

11

DY2SC10P50V2JN-4GP

C3101
SC100P3KV8JN-2-GP

TVW DF1004AD0-1-GP

75.01004.073

MCT2
MDO1+

MDO0-

2
3

12
1
EC3101

MCT3

RJ45-8P-165-GP
MDO0+
MDO0+

XFORM-12P-48-GP

MDO0MDO1+
MDO2+
MDO2MDO1MDO3+
MDO3-

68.68167.30D
C3106
SCD01U50V2KX-1GP

LAN_MDI3P
LAN_MDI3N

10

1CT:1CT

LAN_MDI1P

LAN_MDI2P
LAN_MDI2N

MDO1-

DY2SC10P50V2JN-4GP
1CT:1CT

[30]

10
9
8
7
6

IN1
NC#10
IN2
NC#9
GND
GND
IN3
NC#7
DY
IN4
NC#6

7
1
EC3104

LAN_MDI3P
LAN_MDI3N

1
2
3
4
5

78.1013N.1AL

9
LAN_MDI1N

U3102
LAN_MDI2P
LAN_MDI2N

68.68167.30D

[30]

LAN_MDI1P
LAN_MDI1N

75.01004.073
RN3101
SRN75J-1-GP

XF3101
C

LAN_MDI0P
LAN_MDI0N

TVW DF1004AD0-1-GP

10
8

10
9
8
7
6

IN1
NC#10
IN2
NC#9
GND
GND
IN3
NC#7
DY
IN4
NC#6

MDO3-

DY2SC10P50V2JN-4GP

LAN_MDI1P
LAN_MDI1N

5
6
7
8

[30]

LAN_MDI3N

XFORM-12P-48-GP

1CT:1CT

MCT

[30]

MCT0
MCT1
MCT2
MCT3

1
2
3
4
5

4
3
2
1

XF3102

LAN_MDI0P
LAN_MDI0N

Layout note:
30 mil spacing between MDI differential pairs.

9
1

CHASSIS#9
MDO0+

2
3
4
5
6
7
8
10

MDO0MDO1+
MDO2+
MDO2MDO1MDO3+
MDO3CHASSIS#10
RJ45

Follow Reference Schematic 0.01uF~0.4uF

RJ45

022.10001.0551

2nd = 022.10001.0561
Layout:
Place near RJ45
AFTP3107
AFTP3102
AFTP3101
AFTP3103
AFTP3104
AFTP3106
AFTP3105
AFTP3108

1
1
1
1
1
1
1
1

MDO0+
MDO0MDO1+
MDO2+
MDO2MDO1MDO3+
MDO3-

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

XFOM&RJ45

Rev

Janus HSW 40/50/70

Monday, February 10, 2014

Sheet
1

31

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)Card Reader

Size
A4

Document Number

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

32

A00
of

Rev
104

(Blanking)
C

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

2

Sheet

A00

33

of
1

104

SSID = USB

U3401

GND

I/O2

DY

TR3401
[16]

USB_PN1

[16]

USB_PP1

2
3

USB20_VCCA

I/O4

VDD

I/O3

USB2.0 Port2

I/O1

C3406

DY
2

USB_PP1_R

Note:ZZ.09904.07C01

USB_PN1_R

USB20_VCCA
USB2

SCD1U16V2KX-3GP

6
1

75.09904.07C

USB_PN1_R

AZC099-04S-1-GP

USB_PN1_R
USB_PP1_R

USB_PP1_R

2
3
4
5

FILTER-4P-6-GP

69.10103.041
USB20_VCCA

AFTP6205

SKT-USB8-14-GP

USB_PN1_R
USB_PP1_R

1
1

AFTP6204
AFTP6209

22.10321.E91

USB_PN0

USB_PN0_C

USB_PP0

USB_PP0_C

USB3_PTX_CRX_N0_C
USB3_PTX_CRX_P0_C

U3403

NC#10
NC#9
GND
NC#7
NC#6

10
9
8
7
6

USB3_PRX_CTX_N0_C
USB3_PRX_CTX_P0_C
USB3_PTX_CRX_N0_C
USB3_PTX_CRX_P0_C

USB_PN0_C

USB_PP0_C

DY

I/O1

GND

I/O2

DY

I/O4

VDD

I/O3

USB30_VCCC

DY
2

[16]
[16]

IN1
IN2
GND
IN3
IN4

Note:ZZ.09904.07C01

TR3404

1
2
3
4
5

U3402
USB3_PRX_CTX_N0_C
USB3_PRX_CTX_P0_C

FILTER-4P-6-GP

C3405
SCD1U16V2KX-3GP

TVW DF1004AD0-1-GP

USB3.0 Port1

AZC099-04S-1-GP

69.10103.041
75.01004.073

USB30_VCCC
USB_PN0_C
USB_PP0_C

75.09904.07C

1
1
1

USB1

10
9
1

USB3_PTX_CRX_P0_C
USB30_VCCC
USB3_PTX_CRX_N0_C
USB_PN0_C

R3408

USB3_PTX_CRX_P0_R

SCD1U16V2KX-3GP

R3410

USB3_PTX_CRX_P0_C

[16] USB3_PRX_CTX_P0

0R0402-PAD

USB3_PRX_CTX_P0_C

USB3_PRX_CTX_N0_C

0R0402-PAD

C3402

USB3_PTX_CRX_P0_C
USB3_PTX_CRX_N0_C

USB3_PTX_CRX_N0_R

SCD1U16V2KX-3GP

R3411

USB3_PTX_CRX_N0_C

[16] USB3_PRX_CTX_N0

0R0402-PAD

USB3_PRX_CTX_N0_C

0R0402-PAD

AFTP6217

22.10341.Q21

2
SC4D7P50V2CN-1GP

[16] USB3_PTX_CRX_N0

R3409

SC4D7P50V2CN-1GP

C3403

DY

DY

13
SKT-USB13-151-GP

C3401

[16] USB3_PTX_CRX_P0

C3404

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom

USB 3.0

Rev

Janus HSW 40/50/70

Date:
5

12

8
2
7
3
6
4
5
11

USB_PP0_C
USB3_PRX_CTX_P0_C

AFTP6210
AFTP6211
AFTP6212

Monday, February 10, 2014

Sheet
1

34

A00
of

104

78.10710.52L

TC3502
SC100U6D3V6MX-GP

1
2

DY

1
C3509

C3514

SC22U6D3V5MX-2GP

USB_OC#0_1 [16,18]

SY6288DAAC-GP

1
1

IN
OUT
GND
EN#
OC#
Active Low

1
2
3

C3506
SC1U10V2KX-1GP

C3503
SCD1U16V2KX-3GP

U3504

USB30_VCCC
5V_S5

[24] USB_PW R_EN#

TC3501
SC100U6D3V6MX-GP

USB2.0 Port2
2A

USB20_VCCA

074.06288.009B

C3510
SC1U10V2KX-1GP

DY

USB_OC#0_1 [16,18]

SY6288DAAC-GP

C3513

1
2
3

SC22U6D3V5MX-2GP

OUT
GND
EN#
OC#
Active Low

SC1U10V2KX-1GP

IN

5
[24] USB_PW R_EN#

C3512

SC22U6D3V5MX-2GP

U3503

2A

SC22U6D3V5MX-2GP

5V_S5

DY
C3505

C3507

USB20_VCCA

SC1U10V2KX-1GP

2
D

DY

74.02182.071

SCD1U16V2KX-3GP

AP2182SG-13-GP

USB3.0 Port1

100KR2J-1-GP

USB30_VCCC
USB20_VCCA
USB_OC#0_1 [16,18]

1
2

8
7
6
5

C3508

FLG1
OUT1
OUT2
FLG2

R3501

[24] USB_PW R_EN#

GND
IN
EN1#
EN2# DY

USB30_VCCC

C3502
SC1U10V2KX-1GP

U3502

1
2
3
4

5V_S5

78.10710.52L

074.06288.009B
C

Layout Note: Close CON1

Support 2A

5V_S5

USB20_VCCB

1
2

USB2.0 Port3 (IO Board)

C3516
SC22U6D3V5MX-2GP

74.02000.B71

C3515
SC22U6D3V5MX-2GP

TPS2000CDGNR-GP

1
9

GND
GND

100KR2J-1-GP

FLT#

DY

SC1U10V2KX-1GP

SCD1U16V2KX-3GP

EN/EN# DY

2A

6
7
8

C3518

OUT#6
OUT#7
OUT#8

SCD1U16V2KX-3GP

[16] USB_OC#2_3

IN#2
IN#3

C3517

C3501 [24] USB_PW R_EN#

2
3

R3502

U3501

2nd = 74.02301.079

Support 2A

5V_S5

USB20_VCCB

U3505

[24] USB_PW R_EN#

C3504

IN

OUT
GND
EN#
OC#
Active Low

1
2
3

USB_OC#2_3 [16]

SY6288DAAC-GP

SCD1U16V2KX-3GP

074.06288.009B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Document Number

USB Power SW

Rev

Janus HSW 40/50/70

Date:
5

Friday, February 07, 2014

Sheet
1

35

A00
of

104

SSID = Reset.Suspend

Power Good
3D3V_S0

ROSA Run Power

D

3D3V_AUX_S5

DY

[49] 1D35V_VTT_PW RGD

1 R3610 2
0R0402-PAD

[7,48] 1D05V_VTT_PW RGD

1 R3611 2
0R0402-PAD

R3601
1KR2J-1-GP

ALL_SYS_PW RGD

[24]

PS_S3CNTRL

R3607
100KR2J-1-GP

D G

1
2

G5016KD1U-GP

074.05016.0093

11
15

GND
GND

3V5V_CT2

IN2#6
IN2#7
EN2

8
9
10

SC10U10V5KX-2GP
C3605

6
7
5

OUT2#8
OUT2#9
CT2

3D3V_S0

SC470P50V2KX-3GP
C3602

IN1#1
IN1#2
EN1

5V_S0
3V5V_CT1

SC470P50V2KX-3GP
C3601

0R0402-PAD
3D3V_S5

1
2
3

13
14
12

PM_SLP_S3#

[17,24,26] PCH_PW ROK

2 3V5V_S0_ON

OUT1#13
OUT1#14
CT1

R3609

VBIAS

SC10U10V5KX-2GP
C3603

[17,24,48,49,51]

5V_S0
U3601

DY

84.2N702.A3F
2nd = 84.2N702.E3F S G
3rd = 75.00601.07C
4th = 84.DMN66.03F

5V_S5
5V_S5

Q3601
2N7002KDW -GP

5V_S0 Comsumption
Peak current 5A

3D3V_S0

3D3V_S0 Comsumption
Peak current 2.5A

R3608

1D05V_S0

DY

H_THERMTRIP# [20]

1KR2J-1-GP
B

H_THERMTRIP_EN

84.02222.V11

B
C

[4] H_THERMTRIP_EN

Q3602
MMBT2222A-3-GP

2
4K7R2J-2-GP

C3604
SCD1U16V2KX-3GP

PLT_RST#

R3606
[17,24,30,52,58,65,73,96]

R3605
2K2R2J-2-GP

2ND = 83.00016.F11

D3602
BAS16-6-GP

3rd = 83.00016.P11

4th = 83.00016.G11

[24,26,76]

83.00016.K11

R3602
200KR2F-L-GP

DY
A

PURE_HW _SHUTDOW N#

3V_5V_EN

[45]

S5_ENABLE [24]

R3603
1KR2J-1-GP
<Core Design>

Check R3603 is 1k or 2k.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

Power Plane Enable

Document Number

Janus HSW 40/50/70

Monday, February 10, 2014

Sheet
1

36

Rev

A00
of

104

SSID = Reset.Suspend
Layout Note:
Place Close SO-DIMM1
D

DDR_VREF_S3

1D35V_S3

2R2F-GP
1 R3708 2

M_VREF_CA_DIMMA

+V_SM_VREF_CNT [5]

SODIMM1

R3706
1K8R2F-GP

DY
2

SA_DIMM_VREFDQ

R3704
0R2J-2-GP

R3703
1K8R2F-GP

C3701
SCD022U16V2KX-3GP
+V_VREF_PATH3

R3707
24D9R2F-L-GP

Layout Note:
Place Close SO-DIMM1

R3710
0R2J-2-GP

1D35V_S3

DDR_VREF_S3

R3701
1K8R2F-GP

M_VREF_DQ_DIMMA

+V_VREF_PATH1

R3709
1K8R2F-GP

C3702
SCD022U16V2KX-3GP

2
1
B

2R2F-GP
R3702
2

[5] DDR_W R_VREF01

DY

R3711
24D9R2F-L-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

S3 Reduction Circuit

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

37

Rev

A00
of

104

3D3V_S5

3D3V_S5_PCH

R3801
1

NON DS3

0R5J-5-GP

DS3

U3801

DS3

GND
OUT#8
IN#2
OUT#7
IN#3
OUT#6
EN/EN#
OCB

8
7
6
5

C3802

74.06288.079 (OBS)
RdsON: 100m ohm

SY6288CCAC-GP

DS3

SC1U10V2KX-1GP

2 DS3_PWRCTL
R3802
0R2J-2-GP

1
2
3
4

[17,24] PM_SLP_SUS#

3D3V_S5_PCH

SC1U10V2KX-1GP

DS3
C

Obs reason:
For new project,
pls help to use cost down version
SY6288C10CAC for instead.

C3801

3D3V_S5

DS3

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

DSW

Size
A4

Document Number

Rev

Date: Friday, February 07, 2014

5

A00

Janus HSW 40/50/70

2

Sheet

38

of
1

104

(Blanking)
C

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved) 1D05_M

Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

39

of
1

A00
104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Reserved

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

Sheet

40

of

A00
104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Reserved
Sheet

41
1

A00
of

104

SSID = PWR.Support

PR4217
1

PS_ID_R

PSID_DISABLE#_R_C

84.05067.031
PS_ID_R2

PR4205
PS_ID

75.00099.O7D
2nd = 75.00099.K7D
3rd = 75.00099.Q7D
4th = 75.00099.D7D

PR4204
2K2R2J-2-GP

PSID_EC

[24]

33R2J-2-GP

DY

JGND

PQ4201
DMN5L06K-7-GP
PR4206
1
2

0R3J-0-U-GP

3D3V_S5
PD4203
LBAV99LT1G-1-GP

2
C

2
1

PSID Layout width > 25mil

LMBT3904LT1G-GP

PR4209
100KR2J-1-GP

Layout Note:

3D3V_S5
PR4203
10KR2J-3-GP

E
1

PQ3802_1 B

84.T3904.H11

PQ4202

PR4202
15KR2F-GP

5V_S5

PD4204
PESD24VS2UT-GP

DY

33R2J-2-GP
3

EL4203
2
0R0J-GP

60ohm@100MHz
DCR=0.02 ohm
Max current = 6000mA

E
R2
PDTC124EU-1-GP

84.00124.H1K
2nd = 84.05124.011

AD_OFF_R

AC_IN_KBC#

DY

2N7002K-2-GP

+DC_IN_C
PS_ID_R
+DC_IN_C

BAT_IN#

PQ4203
PR4216
2

DY

100KR2J-1-GP
H_PROCHOT#

PC4210
PQ4203_5
1

2
SCD47U6D3V2KX-GP

BAT_IN# [24,43,44]

2N7002KDW-GP

PR4218
100KR2J-1-GP
2

[4,24,44,46]

1
1
1

PC4209

84.2N702.J31

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
AFTP3801
AFTP3802
AFTP3805

PR4215
PQ3808G 1
2
1KR2J-1-GP

D
S

PR4211
10KR2J-3-GP

PWR_CHG_AD_OFF_R

[24] PWR_CHG_AD_OFF

PQ4208

PQ3808D

SCD01U50V2KX-1GP

3D3V_S5

2
PR4210
1KR2J-1-GP

DT MODE

PC4206
SC10U25V5KX-GP

84.00124.K1K
2nd = 84.05124.A11

2N7002KDW-GP

PR4213
100KR2J-1-GP

[24]

PC4204
SCD01U50V2KX-1GP

1
1

PR4207
240KR3-GP

Id=-9.6A
Qg=-25nC
Rdson=18~30mohm

PR4208
47KR3J-L-GP

PDTA124EU-1-GP

DY

1
AD_OFF_L

R1

DY

PAD-2P-4516-GP-U

PQ4204
B

8
7
6
5

SI7121DN-T1-GE3-GP

SC1U25V3KX-1-GP
PC4208
2
1

AC_IN#_G

PQ4205

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

D
D
D
D

AD+
PU4201
S
S
S
G

1
2
3
4

PQ4206

EL4202

PQ3809_D

PR4212
100KR2J-1-GP

JGND

ZZ.00PAD.V91

PC4201

PC4202
SCD1U50V3KX-GP

PAD-2P-4516-GP-U

1
2

EC4202
SCD1U25V2KX-GP

1
2

JGND

EL4201

PD4201
P6SBMJ24APT-GP

R1

2nd = 20.F1718.007
3rd = 20.F1763.007

SC10U25V5KX-GP

20.F1783.007

PR4214
3K3R6J-GP

ZZ.00PAD.V91

SC1U50V5ZY-1-GP-U

EC4201
DCIN1

R2

DY

1
NP1

+DC_IN

PC4203
SCD01U50V2KX-1GP

1
1
+DC_IN_C

AFTP3806
AFTP3803

7
6
5
4
3
2

ACES-CON7-6-GP-U
NP2

PC4205
SCD01U50V2KX-1GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

DCIN

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

42

of

A00
104

SSID = PWR.Support
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+
BT+
BT+

BT+

AFTP3902
AFTP3903
AFTP3904
AFTP3905
AFTP3907
AFTP3908

EC4304

1
1
1
1
1
1

EC4303
SCD1U25V2KX-GP

Batt Connecter

PD4302
SMF18AT1G-GP

DY
A

SCD1U50V3KX-GP

DY

BAT1
RN4301
4
3
2
1

[24,44] BAT_SCL
[24,44] BAT_SDA
[24,42,44] BAT_IN#

10
1
5
6
7
8

2
3
4
5
6
7
8
9
11

PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#

AFTP3901
SRN100J-4-GP

BAT_ALERT

1
1

DY

EC4305

DY

ALP-CON9-6-GP-U
AFTP3906
1
AFTP3909
1
AFTP3910
1

SC10P50V2JN-4GP

DY

EC4302
SC10P50V2JN-4GP

SC10P50V2JN-4GP

EC4301

20.81925.009
2nd = 20.81928.009

Placement: Close to Batt Connector

BAT_SCL

D4302
LBAV99LT1G-1-GP

D4303
LBAV99LT1G-1-GP

D4301
LBAV99LT1G-1-GP

75.00099.O7D

75.00099.O7D

75.00099.O7D

BAT_SDA

BAT_IN#

2nd = 75.00099.K7D

2nd = 75.00099.K7D

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

3rd = 75.00099.Q7D

3rd = 75.00099.Q7D

4th = 75.00099.D7D

4th = 75.00099.D7D

4th = 75.00099.D7D

3D3V_AUX_KBC

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

BATT CONN

Sheet

43

A00
of

104

SSID = Charger
1

PWR_CHG_CMPIN

1
1

1
PC4408
SC4D7U25V5KX-GP

11

5
6
7
8
12

PWR_CHG_SRN

1 PR4420 2
7D5R2F-GP

DY

BM#

CHG_AGND

DY

CHG_AGND

1
2

EE need check pull high

CHG_AGND

EC4402
SCD1U25V2KX-GP

EC4401
SC2200P50V2KX-2GP

SCD1U50V3KX-GP
2
1

PC4426
SC10U25V5KX-GP
2
1
PC4409

BT+

AC_IN#

PR4426
PQ4008_6

H_PROCHOT# [4,24,42,46]

0R0402-PAD

PQ4408

4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F

DY 10R2F-L-GP
2

EC code only BQ24707

PU4401_5

DY

PR4446
1 DY

BOOST_MON_1

H_PROCHOT#

DY2

PC4424
SCD1U25V2KX-GP
PU4401_4

2PU4401_6

20KR2F-L-GP

AD_IA_HW

AD_IA_HW2

45W

65W

0
0

90W

6
5
4

0R2J-2-GP

[24] BOOST_MON
PR4470
100KR2F-L1-GP

DY
PR4452

DY

PR4410

6D8R2F-GP
1

DY

PU4407
INA199A1-GP

1
2
3

DY

SC1U25V3KX-1-GP
PC4427

PR4473
10KR2F-2-GP
DY

BATTERY MON
1

4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F

PWR_CHG_ACOK

CHECK EE
follow customer circuits.

DY

PQ4410

PC4425

PR4454

DY 0R2J-2-GP

DY PR4476
0R2J-2-GP

PQ4405_5

PR4464

DY 680KR2J-GP

PR4448

DY

DY

PQ4405_2

SC1U25V3KX-1-GP
PC4434
PQ4405_6

DY

DCBATOUT

1DCBATOUT_R 1

2
1

2N7002KDW-GP
PQ4405_3

PQ4408_C
PR4475
0R2J-2-GP
1
2

PR4468
0R2J-2-GP

PR4466
0R2J-2-GP

DY

PR4436
120KR2F-L-GP

SCD01U50V2KX-1GP
2
1

2
1
2

E PQ4408_E

DY

DY
C

2
1
PD4403_K

PD4404
1N4148WS-7-F-GP
K DY
APD4403_A B
PQ4409
LMBT3906LT1G-1-GP

DY
H_PROCHOT# [4,24,42,46]

PG4405

DY

DY

GAP-CLOSE-PWR-3-GP

PR4467
1MR2J-1-GP

PG4404

DY

PR4437
PWR_CHG_CMPOUT 1
2PQ4008_2 2
160KR2F-GP

GAP-CLOSE-PWR-3-GP

PR4471
0R2J-2-GP

2N7002KDW-GP
PWR_CHG_ACOK

DY

15V_S5

Customer Request

PWR_CHG_REGN

PR4419
DY PR4428
100KR2J-1-GP 100KR2J-1-GP

PR4433

DY120KR2F-L-GP
BT+_R

1
PR4469
100KR2J-1-GP

DY

3D3V_AUX_S5

Close PR4416

AC_IN#
1

[24]

2
AD+

PC4401
SCD1U50V3KX-GP

EE need pull high and net name

PR4434
100KR2J-1-GP

PR4425

DY 100KR2J-1-GP

DY

DY

PR4465
0R2J-2-GP

3D3V_AUX_S5

PQ4406_D

PWR_CHG_CSON_1

84.2N702.031

DY
1

PWR_CHG_REGN
PR4474
100KR2J-1-GP

H_PROCHOT#

PWR_CHG_CSOP_1

CHG_AGND
1

PQ4406_G
PQ4414
2N7002K-1-GP

DY

84.00412.037

PC4421
SCD1U25V2KX-GP
1

[24]

PC4433
SCD47U6D3V2KX-1-GP

AD_IA

1+VCHGR_R

DY

DY

1
PG4411

2
PR4422
0R2J-2-GP

PC4423
SCD1U25V2KX-GP

CHG_AGND

1
1PC4422
SC220P50V2JN-3GP

GAP-CLOSE-PWR-3-GP

CHECK EE

PWR_CHG_IOUT

1 PR4424
8K45R2F-2-GP

[24,42,43]

IOUT

GND
14

GND

ACOK#

2
BAT_IN#

BT+

74.02224.073
5

21

3D3V_AUX_S5
1

1
2
CHG_AGND

100KR2F-L1-GP
PR4472

DY

3D3V_AUX_KBC

PR4435
10KR2F-2-GP

2
1

DY

3D3V_S5

PR4423
59KR2F-GP

PR4439
10KR2F-2-GP

0R0402-PAD

DY

[4,24,42,46]

65BOM charger

ILIM
SRN

2 PWR_CHG_IFAULT

13

4
3
2
1

PR4418
1

[24] BOOST_MODE#

SRP

S
S
S
G

PR4417
100KR2J-1-GP

10

PC4420
SCD1U25V2KX-GP

PWR_CHG_ILIM

1 PR4421 2
10R2F-L-GP

PU4406

PWR_CHG_SRP

64.R0105.7FL

PC4419
SCD1U50V3KX-GP

PWR_CHG_LODRV

D
D
D
D

BAT_SDA

PC4406
SC10U25V5KX-GP
2
1

68.5R610.10U

[24,43] BAT_SCL
[24,43]

3D3V_AUX_S5

5
6
7
8

PWR_CHG_BTST_R

4
3
2
1
1
2 BT+_R
IND-5D6UH-45-GP

1
PC4418
SC10U25V5KX-GP

SDA

PL4401

PWR_CHG_BAT_SDA 8
1
GAP-CLOSE-PWR-3-GP

15

DY

1
PC4417
SC10U25V5KX-GP

2
PG4408

LODRV

SCL

PC4413
SC3300P50V3KX-1GP

PWR_CHG_BAT_SCL 9
1
GAP-CLOSE-PWR-3-GP

PWR_CHG_PHASE

SIS412DN-T1-GE3-GP

2
PG4407

19

Charger Current=1.4~3.6A
PR4416
D01R3721F-GP-U

SC10U25V5KX-GP

1
2

PHASE

DY

1
PC4415
SC10U25V5KX-GP
2
1
PC4416

HIDRV
CMPIN

PWR_CHG_HIDRV

DY

65BOM charger

16
18

DY

84.00412.037

PU4405
2
PC4407
SIS412DN-T1-GE3-GP
SC1U25V3KX-1-GP

PWR_CHG_BTST

PG4410
GAP-CLOSE-PWR-3-GP
1
2

17

PG4409
GAP-CLOSE-PWR-3-GP
1
2

PC4403
SC1U25V3KX-1-GP

CMPOUT

3
4

120KR2F-L-GP
PWR_CHG_CMPIN
CHG_AGND

PR4414
3D3MR2J-GP

PR4432

ACDET
BTST
HPA02224RGRR-1-GP
REG

3K3R2F-2-GP

PR4413
84K5R2F-GP

PWR_CHG_ACDET

VCC

PWR_CHG_CMPOUT

PR4412

DY

PU4404
20

PWR_CHG_REGN
PD4401
SD103AWS-1-GP

CHG_AGND

PR4430
100KR2J-1-GP

PR4415

3K3R2F-2-GP

1
1

PC4412
SCD01U50V2KX-1GP

2
2

PR4438
100KR2J-1-GP

PR4409
0R3J-0-U-GP
1
2

CHG_AGND

PC4411
SCD047U25V2KX-GP

1
2

PWR_CHG_REGN

3D3V_AUX_S5
3D3V_AUX_KBC

PR4411
102KR2F-GP

83.1R504.A8F
2nd = 83.1R004.H8F
3rd = 83.1R504.B8F
4th = 83.2R004.08F

S
S
S
G

PWR_CHG_IOUT

GAP-CLOSE-PWR
CHARGER_SRC

1
2

10R5J-GP

GAP-CLOSE-PWR
PG4414
2
1

PC4402
SCD1U25V2KX-GP

CHG_AGND
PWR_CHG_VCC

PC4010
SCD47U25V3KX-1GP

PR4408
1

84.07121.037
2nd = 84.03605.037

D
D
D
D

PR4407
309KR2F-GP

DCBATOUT

PG4412
2

GAP-CLOSE-PWR
PG4413
2
1

GAP-CLOSE-PWR
PG4415
2
1

PWR_CHG_ACN

6
PQ4402

4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F

CHG_AGND

CHARGER_SRC

Id= -10A
Qg= -22nC
Rdson=15~18mohm

PWR_CHG_CMPIN

PR4431
47KR2F-GP

D 8
D 7
D 6
D 5

ACN

DY

PWR_CHG_ACP

PR4406
0R2J-2-GP
2

PWR_CHG_ACOK

AD+

PU4403
S
S
S
G

SI7121DN-T1-GE3-GP

PR4405
470KR2J-2-GP
PG4403
GAP-CLOSE-PWR-3-GP

ACP

DC_IN_D

2N7002KDW-GP

AD+_G_1

PWR_CHG_CMPIN_RR
PR4427
66K5R2F-GP

AD+_G_2

Id= -10A
Qg= -22nC
Rdson=15~18mohm

PG4402

84.07121.037
2nd = 84.03605.037

PR4404
3KR5J-GP

GAP-CLOSE-PWR-3-GP

6
PQ4407

AD+

SI7121DN-T1-GE3-GP

[24]

PC4404
SC1U25V3KX-1-GP
2
1

4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F

CHG_AGND

1
2
3
4

AD_IA_HW

CHG_AGND

PR4403
100KR2J-1-GP

1
2
3
4

AD_IA_HW2

PR4402
1
2
D01R3721F-GP-U

PR4401
10KR2F-2-GP

[24]

DCBATOUT
BT+

AD+
2N7002KDW-GP

AD+_TO_SYS

PU4402
S
S
S
G

8 D
7 D
6 D
5 D

PWR_CHG_CMPIN_R 2

PR4429
150KR2F-L-GP

3D3V_S5

DY

SC1U25V3KX-1-GP
PC4431

DCBATOUT

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom

CHARGER HPA02224

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

44

A00
of

104

SSID = PWR.Plane.Regulator_5v3p3v

0R0402-PAD

GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4531
2
1

1
2
3

1
2
3

PC4534

DY

SCD1U50V3KX-GP

PC4515
GAP-CLOSE-PWR
PG4543
2
1

GAP-CLOSE-PWR
PG4524
2
1

3rd = 83.BAT54.P81

15V_S5
PG4530
GAP-CLOSE-PWR-3-GP
BOOST_10V

GAP-CLOSE-PWR
PG4542
2
1
SCD1U50V3KX-GP

GAP-CLOSE-PWR
PG4521
2
1

DY

DY

15V_PWR

PC4533
SC1U25V3KX-1-GP

2 PWR_3D3V_EN2

DY

2nd = 83.00054.Y81

PD4501
BZT52C15S-GP

DY

DY
A

PR4506
1

3V_5V_EN

5V_PWR

[36]

75.00054.C7D

PD4502
BAT54SPT-1-GP

PG4525
2
1

3rd = 83.BAT54.P81

GAP-CLOSE-PWR
PG4534
2
1

75.00054.C7D

PD4503
BAT54SPT-1-GP

2
PR4507
0R0402-PAD

DY

GAP-CLOSE-PWR
PG4518
2
1

0R0402-PAD

PWR_DCBATOUT_3D3V

2nd = 83.00054.Y81

PWR_5V_EN1

PC4532

DY

DCBATOUT

1
2

GAP-CLOSE-PWR
PG4536
2
1

PR4504
PWR_5V_EN1_R

0R2J-2-GP

DY

BST15V_2

DY

SCD1U50V3KX-GP

DY

PC4514

PWR_DCBATOUT_5V
PG4520
2
1

PR4530
2

PC4521
SC1KP50V2KX-1GP

DCBATOUT

BST15V_1

PR4501
0R2J-2-GP

SCD1U50V3KX-GP

PWR_5V_VCLK

3D3V_AUX_S5

DCBATOUT
GAP-CLOSE-PWR
PWR_DCBATOUT_3D3V
PC4509

PWR_3D3V_EN2

EN2

EN1

20

PWR_5V_EN1

PWR_5V_CS1

19

PWR_5V_VCLK

PWR_3D3V_CS2
1

CS2

CS1

74.51225.073
PGOOD

GND

21

PR4531
137KR2F-1-GP

79.22710.3KLGAP-CLOSE-PWR
PG4523
2
1

GAP-CLOSE-PWR
PG4541
2
1
GAP-CLOSE-PWR
PG4540
2
1

1
2

PC4536
SC560P50V-GP

DY

GAP-CLOSE-PWR
PG4545
2
1

3D3V_PWR_2

5V_PWR_2

PR4525
0R2J-2-GP

DY

DY

PC4522
SC18P50V2JN-1-GP

1 2

PC4524
SC1U6D3V3KX-2GP

PC4526
SC4D7U6D3V3KX-GP

PR4534

DY 100KR2J-1-GP

GAP-CLOSE-PWR

PWR_3D3V_FB2_R
PC4523

DYSC18P50V2JN-1-GP

PWR_5V_FB1_R

GAP-CLOSE-PWR
PG4544
2
1
PR4527
15K4R2F-GP

1
2

1 2

GAP-CLOSE-PWR
PG4533
2
1

PT4501

3D3V_S5

PR4535

DY0R2J-2-GP

[17] 3V_5V_POK

3D3V_PWR_2

PR4526
9K76R2F-1-GP

PR4523
10KR2F-2-GP

DY

VREG3

VREG5

VCLK

DY

TPS51225RUKR-GP
PR4517
73K2R2F-GP

DY

PC4520
SC330P50V3KX-GP

1
2
3
4

3
2
1

84.00412.037

65BOM charger

PC4518
1

PWR_5V_FB1

PG4532

PWR_5V_VO1

GAP-CLOSE-PWR
PG4537
2
1

IND-2D2UH-46-GP-U

14

VFB1

PL4501

PR4529
2D2R5F-2-GP

GAP-CLOSE-PWR
PG4519
2
1
GAP-CLOSE-PWR
PG4538
2
1

5V_PWR

68.2R210.20B
1

VFB2

4
3
2
1
2

SCD1U16V2KX-3GP

1
2

PWR_5V_DRVL1

SCD1U50V3KX-GP

VO1
PWR_3D3V_FB2

PU4505

S
S
S
G

15

PWR_5V_VBST1_1

8
7
6
5

2
1PWR_3D3V_SNUB

PWR_5V_LL1

1D5R3-GP

1PWR_5V_SNUB

DRVL1

18

PR4524
1

5
6
7
8

DRVL2

13

PR4512
6K8R2F-2-GP

SW1

PWR_5V_DRVH1

1
2

12
VIN

SW2

PWR_5V_VBST1

16

PU4502

65BOM chargerSIS412DN-T1-GE3-GP

PT4501 and PT4502 manually change to 77.52271.06L

5
6
7
8

8
7
6
5
1 S
2 S
3 S
4 G

11

DRVH1

D
D
D
D

1
2
3V_FEEDBACK

PWR_3D3V_DRVL2

DRVH2

17

SE220U6D3VM-38-GP

VBST1

PG4527
2
1

Design Current=8.65A
12.98A<OCP>15.34A

GAP-CLOSE-PWR-3-GP

SCD1U16V2KX-3GP

PWR_3D3V_LL2

VBST2

S
S
S

79.22710.3KL

10

SIS780DN-T1-GE3-GP

GAP-CLOSE-PWR

PG4535

PC4516
9

PWR_3D3V_DRVH2

GAP-CLOSE-PWR
PG4529
2
1

PT4502

PR4533 DY
2D2R5F-2-GP

GAP-CLOSE-PWR-3-GP

DY

2 PWR_3D3V_VBST2
1D5R3-GP

D
D
D
D

PC4517

PL4502
1
2
IND-3D3UH-57GP

SE220U6D3VM-38-GP

GAP-CLOSE-PWR
PG4522
2
1

1PWR_3D3V_VBST2_11
SCD1U50V3KX-GP

68.3R310.20A

GAP-CLOSE-PWR
PG4517
2
1
GAP-CLOSE-PWR
PG4528
2
1

65BOM charger

5V_S5

5V_PWR

3D3V_PWR

PR4528

PC4527
SC10U25V5KX-GP

3D3V_PWR
PG4526
2
1

PU4503

PC4535

PC4529
SC4D7U25V5KX-GP

84.00412.037

PC4530
PU4501

SCD1U50V3KX-GP

PU4504

PWR_DCBATOUT_5V

SIS412DN-T1-GE3-GP
D
S
D
S
D
S
D
G

D
D
D
D

1
2

DY

65BOM charger

3D3V_S5

PC4531
SCD01U50V2KX-1GP

PC4519
SC10U25V5KX-GP

SIS412DN-T1-GE3-GP
SC4D7U25V5KX-GP

DY

SC10U25V5KX-GP

SCD1U50V3KX-GP

Design Current=3.3A
5.17A<OCP>6.11A

PC4528
PC4525

3D3V_AUX_S5

Close to VFB Pin (pin2)

PR4532
1

Close to VFB Pin (pin5)

2
0R0402-PAD

TPS51225 & TPS51285 Co-lay

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
1

TPS51225

TPS51285

PR4510 45.3KK

9.09K

PR4511 110K

22.1K

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

3V/5V TPS51225
Size
A2
Date:
A

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
E

45

of

104

SSID = CPU.Regulator
PR4614

2PW R_VCC_PRGM1

15W/28W

90K9R2F-GP
D

PR4630

1D05S_VCCST

PR4607
PW R_VCC_SDA

130R2F-1-GP
PR4620
1

2PW R_VCC_PRGM2

124KR2F-GP
PW R_VCC_SCLK

[7] H_CPU_SVIDDAT

2 PR4619 1 0R0402-PAD

PW R_VCC_SDA

2 PR4618 1 0R0402-PAD

PW R_VCC_ALERT#

2 PR4616 1 0R0402-PAD

PW R_VCC_SCLK

54D9R2F-L1-GP
PR4601

PW R_VCC_ALERT#

[7] VR_SVID_ALERT#

DY

75R2F-2-GP

PC4606
SCD1U16V2KX-3GP

[7] H_CPU_SVIDCLK

12

2 PR4621 1 0R0402-PAD

[7] H_VR_ENABLE

PR4610
1

11

17
PRGM1

SDA

PRGM2

18

19
ALERT#

SCLK

PU4601

PC4604
SC1U10V3KX-3GP

20

5V_S0

VCC

PW R_VCC_EN

VR_ON

PW R_VCC_IMON

IMON

BOOT

13

PW R_VCC_BOOT

UG

14

PW R_VCC_UG

PW R_VCC_UG [47]

PHASE

15

PW R_VCC_PHASE

PW R_VCC_PHASE [47]

LG

16

PW R_VCC_LG

PW R_VCC_BOOT [47]

100KR2F-L1-GP

ISL95813HRZ-GP

PW R_VCC_VRHOT#

PW R_VCC_LG [47]
PR4603

PR4624

1 0R0402-PAD

PW R_VCC_COMP

COMP

FB

LL=2mohm

VCC_SENSE [7]

15W/28W

1K27R2F-L-GP

1
PR4606

GND

DY

SCD1U16V2KX-3GP

ISUMP

21

5K1R2F-2-GP

PC4610
1

PW R_VCC_FB

DY

PC4601
PW R_VCC_FB_RC 1

PC4613

DY

0R2J-2-GP

SCD1U16V2KX-3GP SC1KP50V2KX-1GP

10

ISUMN

PW R_VCC_COMP_RC

SC6800P50V3KX-GP

R4622
2KR2F-3-GP
1
2

PR4613

PC4611
2
1

RTN

H_PROCHOT#

3D3V_S0

74.95813.B73

VRHOT#

DY

NTC

[4,24,42,44]

SC1KP50V2KX-1GP

1D05V_S0

PC4609

2 499R2F-2-GP

PGOOD

PR4602

PR4628

1 0R0402-PAD

[7,24] IMVP_PW RGD

PW R_VCC_POK

PR4617

PW R_VCC_ISUMP

[47]

PW R_VCC_ISUMN

[47]

PR4615
PW R_VCC_NTC_R

PW R_VCC_NTC
PW R_VCC_ISUMN

3K83R2F-GP
16KR2F-GP
PR4622

PR4604

NTC-470K-5-GP-U

VSS_SENSE [9]

10R2F-L-GP

B=4500K

PC4612

close to H/S MOSFET

PR4622 manually change to 69.60037.001

PW R_VCC_ISUMP

1
SC1KP50V2KX-1GP

PR4603

PR4614

15W

1.27K
64.12715.6DL

90.9K
64.90925.6DL

28W

1.58K
64.15815.6DL

113K
64.11335.6DL

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

ISL95813_CPUCORE(1/2)
Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

A00
46

of

104

DCBATOUT

PW R_DCBATOUT_VCCCORE

DCBATOUT

PR4701
0R3J-0-U-GP
1

[46] PW R_VCC_BOOT

PW R_VCC_BOOT_RC

PC4706

SCD22U25V3KX-GP

GAP-CLOSE-PW R
PG4704
1
2

For acoustic noice

GAP-CLOSE-PW R
PG4705
1
2
GAP-CLOSE-PW R
PG4706
1
2

FDMS3600-02-RJK0215-COLAY-GP

ZZ.00215.037
1st = 084.06970.0037

GAP-CLOSE-PW R

VCC_CORE

2nd = 84.08S36.037

PW R_VCC_PHASE

PL4701 1

2 IND-D22UH-9-GP-U

Shark Bay ULT 15W CPU

IccMAX=32A
TDC=10A
35.2A<OCP<41.6A
Frequency=750KHZ
LL=-2.0 mV/A

68.R2210.10C

PG4702
GAP-CLOSE-PW R-3-GP

PG4701
GAP-CLOSE-PW R-3-GP

ISUM_R_C

PHASE1G

PR4702
3K65R2F-1-GP

GAP-CLOSE-PW R
PG4707
1
2

[46] PW R_VCC_LG

[46] PW R_VCC_PHASE

PW R_DCBATOUT_VCCCORE
PG4703
2

GAP-CLOSE-PW R
PG4708
1
2

PT4702

DY
2

PC4704

1
2

1
2

2
7
6
5

PC4703
SC10U25V5KX-GP

2
3
4
10

[46] PW R_VCC_UG

SC10U25V5KX-GP

SC10U25V5KX-GP

PU4701

PC4702

SCD1U50V3KX-GP

PU4701 manually change to 084.06970.0037.

PC4701

SE33U25VM-10-GP

close to CHOKE
PR4703
1

4K42R2F-GP

NTC-10K-26-GP-U

B=3370K

10MR2F-GP

PC4710
SCD1U25V2KX-GP

PR4708

PR4707

PR4704
PHASE_R_R

11KR2F-L-GP

PR4705 (Cyntec)

OCP

15W

357 ohm (64.35705.6DL)

38A

28W

412 ohm (64.41205.6DL)

48A

PC4707

2
PR4705

SCD047U25V2KX-GP
PC4708
1
2 SCD1U16V2KX-3GP

15W/28W
1

PW R_VCC_ISUMN

[46]

PR4705 (Maglayers)

357R2F-GP
PC4709
1
2

PR4706
ISUM_R_R

DY
SCD1U16V2KX-3GP

DY

0R2J-2-GP

PW R_VCC_ISUMP

15W

383 ohm (64.38305.6DL)

38A

28W

464 ohm (64.46405.6DL)

48A

[46]

Change PC4723 to 10U from 22U based on PI Simulation.

1
2

1
2

1
2

1
2

EC4701
SCD1U25V2KX-GP

<Core Design>

Stuff PC4727, PC4737 for 28W.

PC4744

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

PC4743

DY
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

2
1

1
2

PC4742

SC22U6D3V5MX-2GP

PC4740

SC22U6D3V5MX-2GP

PC4739

SC22U6D3V5MX-2GP

PC4738

DY

SC22U6D3V5MX-2GP

PC4737

DY

SC22U6D3V5MX-2GP

PC4735

DY

SC22U6D3V5MX-2GP

PC4720
SC22U6D3V5MX-2GP

PC4719
SC22U6D3V5MX-2GP

Change to 79.3371V.6CL

PC4718
SC22U6D3V5MX-2GP

DY

PC4717
SC22U6D3V5MX-2GP

PT4701
SE330U2D5VM-8-GP

PC4728

DY

SC22U6D3V5MX-2GP

PC4727

DY

SC22U6D3V5MX-2GP

PC4724

SC22U6D3V5MX-2GP

PC4722

DY

SC22U6D3V5MX-2GP

PC4721

SC22U6D3V5MX-2GP

PC4741

SC22U6D3V5MX-2GP

PC4736

SC22U6D3V5MX-2GP

PC4734

SC22U6D3V5MX-2GP

PC4733

SC22U6D3V5MX-2GP

PC4732

SC22U6D3V5MX-2GP

VCC_CORE

SC22U6D3V5MX-2GP

PC4731

VCC_CORE

SC22U6D3V5MX-2GP

PC4730

SC22U6D3V5MX-2GP

DY

SC22U6D3V5MX-2GP

PC4729
SC22U6D3V5MX-2GP

PC4726
SC22U6D3V5MX-2GP

PC4725
SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

PC4723

22uF/6.3V/0805*13
330uF/2.5V/6.3*4.5/12mohm*1

ISL95813_CPUCORE(2/2)
Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

47

A00
of

104

SSID = PWR.Plane.Regulator_1p05v

DCBATOUT

1
2

1
2

5
6
7
8

GAP-CLOSE-PW R
PG4827
2
1
GAP-CLOSE-PW R

4
3
2
1
4
3
2
1

1
2

1
2
1

GAP-CLOSE-PW R
PG4824
2
1

PT4803

79.3371V.6CL

GAP-CLOSE-PW R
PG4825
2
1
GAP-CLOSE-PW R

PW R_1D05V_PW R

PC4838
SC560P50V-GP

PR4822
10KR2F-2-GP

DY

PC4823
SC18P50V2JN-1-GP

PC4824
SCD1U16V2KX-3GP

S
S
S
G

DY

PR4837
2D2R5F-2-GP

65BOM charger

1
2
IND-2D2UH-46-GP-U

84.00412.037

1PWR_1D05V_SNUB 2

DY
PU4805

74.08237.B73

GAP-CLOSE-PW R
PG4826
2
1

PL4801

5V_S5
PC4815
SC1U10V2KX-1GP

GAP-CLOSE-PW R
PG4831
2
1

1D05V_PW R

68.2R210.20B

5
6
7
8

PW R_1D05V_LGATE

GAP-CLOSE-PW R
PG4830
2
1

Design Current =4.43A

6.645A<OCP<7.97A

1
1
2

SCD1U50V3KX-GP
PR4820
PC4822
2D2R3-1-U-GP
PW R_1D05V_BOOT 1
2PW R_1D05V_BOOT_R 2
1
PW R_1D05V_UGATE
PW R_1D05V_PHASE

1D05V_S0

PG4828
2
1

SE330U2D5VM-14-GP

RT8237CZQW -2-GP

11
10
9
8
7
6

1D05V_PW R

GAP-CLOSE-PW R
PG4834
2
1

PG4832

DY

GND
BOOT
UGATE
PHASE
VCC
LGATE

SIS412DN-T1-GE3-GP

PR4824
470KR2F-GP

PGOOD
CS
EN
FB
RF

D
D
D
D

PC4821
SC1KP50V2KX-1GP

1
2
3
4
5

PW R_1D05V_PW RGD
PW R_1D05V_TRIP
PW R_1D05V_EN
PW R_1D05V_FB
PW R_1D05V_CCM

GAP-CLOSE-PW R
PG4837
2
1

GAP-CLOSE-PWR-3-GP

SCD1U50V3KX-GP

PU4806

PR4819
0R0402-PAD

PM_SLP_S3#

PC4825

84.00412.037
65BOM charger

(current limit ~ 7.3A)

[17,24,36,49,51]

PC4814

PR4817
1
105KR2F-1-GP

PC4826

DY

SC4D7U25V5KX-GP

SC10U25V5KX-GP
SIS412DN-T1-GE3-GP
D
S
D
S
D
S
D
G

[7,36] 1D05V_VTT_PW RGD

0R0402-PAD
2 PR4821 1

PW R_DCBATOUT_1D05V

PU4808

PW R_DCBATOUT_1D05V

PG4838
2
1

PW R_1D05V_FB

Vout=0.704V*(R1+R2)/R2
B

PR4823
21KR2F-GP

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780DN-T1-GE3 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

RT8237_1D05V
Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

A00
48

of

104

SSID = PWR.Plane.Regulator_1p35v0p675v

DCBATOUT
D

+PWR_SRC_1D35V
PG4903
1

GAP-CLOSE-PWR
PG4904
2
1
GAP-CLOSE-PWR
PG4905
2
1

1D35V_PWR

PG4908
2
1

TPS51716RUKR-GP

74.51716.073
+0D675V_DDR_P
0D675V_S0
PG4901
2
1
GAP-CLOSE-PWR
PG4902
2
1

SC4D7U25V5KX-GP

SC10U25V5KX-GP

1
2

SC4D7U25V5KX-GP

PC4922
SC330P50V2KX-3GP

DY

DY

DY

GAP-CLOSE-PWR
PG4915
2
1

PC4926

PC4925

PC4921

1
2

1
2

PC4924

EC4601
SCD1U50V3KX-GP

GAP-CLOSE-PWR
PG4916
2
1
GAP-CLOSE-PWR
PG4917
2
1
GAP-CLOSE-PWR
PG4918
2
1
GAP-CLOSE-PWR
PG4919
2
1

1D35V_PWR

DDR_VREF_S3
PR4911
PWR_1D35V_VTTREF 1

1
1

DY

PC4923

GAP-CLOSE-PWR
PG4920
2
1
[17,24]

PM_SLP_S4#

PWR_1D35V_EN

1 PR4907 2
0R0402-PAD

GAP-CLOSE-PWR

PC4906

DY

SCD1U16V2KX-3GP
2

GND

+0D675V_DDR_P

VTTGND

TPS51216_PHS_SET

PC4904
SC1U10V3KX-3GP

VTTSNS
GND

VTT

PC4917
SC10U6D3V3MX-GP
2
1

VTTREF

PC4918
SCD22U10V2KX-1GP
21

PC4916
SC10U6D3V3MX-GP
2
1

VLDOIN

PWR_1D35V_VTTREF5

PWR_1D35V_VDDQS

SCD1U16V2KX-3GP

DY

PC4920
SC4D7U6D3V3KX-GP

VDDQSNS

3
2
1

TRIP

PR4912
2D2R5F-2-GP

PG4907
GAP-CLOSE-PWR-3-GP

PWR_1D35V_TRIP 18

68.R6810.20B

DY

PWR_1D35V_VDDQS

65BOM charger

PU4903

84.00780.037

10

PWR_1D35V_DRVL

5
6
7
8

11

PC4915
1

30K1R2F-L-GP

DRVL
PGND

MODE

SCD1U16V2KX-3GP
2

1
PR4902
133KR2F-GP
1
2

PR4908

0R0402-PAD

1
2

2
1KR2F-3-GP

2
2 PR4901

PC4902
1

REFIN

SC22U6D3V5MX-2GP

19

GAP-CLOSE-PWR
PG4914
2
1

1
2
COIL-D68UH-5-GP

SC22U6D3V5MX-2GP

PWR_1D35V_MODE

PWR_1D35V_SW

SC22U6D3V5MX-2GP

PWR_1D35V_REFIN

13

GAP-CLOSE-PWR
PG4913
2
1

1D35V_PWR

PL4902
SW

GAP-CLOSE-PWR
PG4912
2
1

Design Current=8.65A
12.97A<OCP>15.57A

DRVH

SC4D7U25V5KX-GP

1
2D2R3-1-U-GP

VREF

GAP-CLOSE-PWR
PG4911
2
1

SC22U6D3V5MX-2GP

SIS780DN-T1-GE3-GP

PR4906

S
S
S

SCD01U50V2KX-1GP

PWR_1D35V_DRVH

PC4903
1

14

PR4905
1

D
D
D
D

PR4601_1

SCD1U16V2KX-3GP
2

PWR_1D35V_VBST

S5

PR4903
10KR2F-2-GP

15

84.00412.037

GAP-CLOSE-PWR
PG4910
2
1

VBST

GAP-CLOSE-PWR
PG4909
2
1

PWR_1D35V_VREF

V5IN

S3

PC4914
PC4913
SCD1U50V3KX-GP

DY

PGOOD

DY

16

PWR_1D35V_EN

PC4912

17

1 0R2J-2-GP

PM_SLP_S3#

10R0402-PAD DDR_VTT_PG_CTRL_R

R4910 2

PC4911

65BOM charger
S
S
S
G

[17,24,36,48,51]

R4909 2

PC4919
SCD1U50V3KX-GP

12

4
3
2
1

2
[36] 1D35V_VTT_PWRGD

PC4909

2
PU4902

PU4901
20

SIS412DN-T1-GE3-GP

PR4605_2

D
D
D
D

DY

PR4904
20KR2F-L-GP

5
6
7
8

3D3V_S0

PC4901
SC1U10V3KX-3GP

5V_S5

GAP-CLOSE-PWR

[12] DDR_VTT_PG_CTRL

1D35V_S3

+PWR_SRC_1D35V

GAP-CLOSE-PWR
PG4906
2
1

0R0603-PAD-1-GP-U

GAP-CLOSE-PWR

State

S3

S5

VDDR

VTTREF

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP IND 0.1UH M PCMC063T-R10MN 1.5~1.7mohm Isat =60Arms 68.R1010.10T
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L
MOS: FET MOS FDMS3664S NC POWER56 / 84.03664.037 / Q1: 8.5~11mohm @Vgs=4.5V Q2: 2.6~3.2mohm @Vgs=4.5V

VTT

S0

Hi

Hi

On

On

S3

Lo

Hi

On

On

Off(Hi-Z)

On

S4/S5

Lo

Lo

Off

Off

Off

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
C
Date:
5

TPS51716_1D35V_S3
Document Number

Rev

Janus HSW 40/50/70

Monday, February 10, 2014

Sheet
1

A00
49

of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Reserved

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

50

A00
of

104

SSID = PWR.Plane.Regulator_1p5v

TLV70215 for 1D5V_S0

3D3V_S5

[17,24,36,48,49]

PU5101

1
2
3

2PW R_1D5V_EN

PM_SLP_S3#

Design Current = 150mA

1D5V_PW R

OUT
NC#4

1D5V_S0

PG5105

GAP-CLOSE-PW R

TLV70215DBVR-GP

74.70215.03F

SC1U10V2KX-1GP
PC5120

PR5110
0R0402-PAD

IN
GND
EN

PC5119
SC1U10V2KX-1GP

GAP-CLOSE-PW R

PC5115

1D5V_VGA_S0
2

GAP-CLOSE-PW R
PG5103
1
2

SY8208D for 1D35V_VGA_S0(1D5V)

PW R_DCBATOUT_VRAM_PW R

GAP-CLOSE-PW R
PG5102
1
2

PC5113

1D5V_VGA_S0

PW R_DCBATOUT_VRAM_PW R
PG5101
2

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP

DCBATOUT

PU5102

1D5V_VGA_S0

IN

BS

Design Current=3.4A
OCP=8A

PC5110

VRAM_PW R_BS_R 1

1D5V_VGA_S0

1D5V_VGA_S0
8

PR5102

0R3J-0-U-GP

SCD1U50V3KX-GP

VRAM_PW R_BS

1D35V_VGA_S0

SC2D2U6D3V2MX-GP

1D5V_VGA_S0

1
2

SC22U6D3V5MX-2GP

PC5118

PC5117
SC22U6D3V5MX-2GP

DY
2

1
2

PC5116
SC22U6D3V5MX-2GP

1
2

1
2

VRAM_PW R_FBH

1D5V_VGA_S0

PC5108

DY

SC22U6D3V5MX-2GP

PC5109
SC1U10V2KX-1GP

PC5112

SC22U6D3V5MX-2GP

1D5V_VGA_S0

SY8208DQNC-GP-U

74.08208.K73

2
1
0R2J-2-GP

VRAM_PW R_LDO

PC5101

PC5114
SCD1U50V3KX-GP

1D5V_VGA_S0

1D5V_VGA_S0

PR5113
150KR2F-L-GP

PG5104

PC5111
SC220P50V2KX-3GP

LDO

1D5V_VGA_S0

GND

3D3V_S5

BYP

IND-1UH-206-GP

VRAM_PW R_BYP

1D5V_VGA_S0

1D5V_VGA_S0
Vo=0.6x(1+R1/R2)
=0.6x(1+150/100)
=1.5V

<Core Design>

PR5103
100KR2F-L1-GP

1D5V_VGA_S0: for DDR3 VRAM only

VRAM_PW R_FB

EN

9
PR5104
1MR2J-1-GP

DY

FB

PR5112

PW R_VRAM_PW R_EN

Check GPU power sequence.

ILMT

LX

VRAM_PW R_PH

2 PR5114 1
0R2J-2-GP

1D5V_VGA_S0

PG

[83] 1D35V_VGA_EN

PW R_VRAM_PW R_ILIM

10

1D5V_VGA_S0 1D5V_VGA_S0
GAP-CLOSE-PWR-3-GP

PU5102_PG

1D5V_VGA_S0
PR5111 2
470KR2F-GP

PL5101

TP5101

Wistron Corporation

1D5V_VGA_S0

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

TLV70215_1D5V / SY8208D_1D5V(VGA)
Size
A3
Date:
5

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

A00
51

of

104

INVERTER POWER
800mA

F5201

DBC_EN

[20]

SCD1U50V3KX-GP

LCD

3D3V_CAMERA_S0

CCD1
9
1
Notice:20.F2191.008

DY

1 R5205

DY
2

LCD_BRIGHTNESS
BLON_OUT_C
PANEL_SIZE_ID_CONN

TOUCH_PANEL_INTR#

[24]

TP_RS

For ESD

0R0402-PAD

R5208
10KR2J-3-GP

C5208
SC10P50V2JN-4GP

DY

PANEL_SIZE_ID

100R2J-2-GP

PLT_RST# [17,24,30,36,58,65,73,96]

0R0402-PAD
C5214
SC10P50V2JN-4GP

DY

2
3
4
5
6
7
8

USB_CAMERA#
USB_CAMERA

USB_CAMERA#

RN5202
DMIC_CLK_C
DMIC_DATA_C

1
2

DY

4
3

DMIC_CLK [27]
DMIC_DATA [27]
EC5205

SRN33J-5-GP-U

0R0402-PAD
ACES-CON40-18-GP

SRN33J-5-GP-U

USB_PP6 [16]

0R0402-PAD
RN5203
1
2
3
4

MIC_GND

8
7
6
5

BKLT_CTRL
BLON_OUT_C
EDP_HPD
R5222 1

RN5201

RN5206

3
2

1
2

4
3

USB_PN4 [16]
USB_PP4 [16]

SRN0J-6-GP
FILTER-4P-6-GP

LCD_TST

[24]

BLON_OUT

[24]

100R2J-2-GP

R5233

EDP_HPD
3D3V_S0

DY
[8] EDP_TX0_DN
[8] EDP_TX0_DP

C5203
C5210

[8] EDP_TX1_DN
[8] EDP_TX1_DP

C5211
C5213

1
1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

EDP_TX0#
EDP_TX0

EC_BRIGHTNESS

BAT54C-7-F-3-GP
2

LCDVDD

3
[24]

EC (BIST MODE)

75.00054.E7D
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81

[15]
5V_S0

D5201
TPAN_VDD

[8] EDP_AUX_DN
[8] EDP_AUX_DP

Brightness
[15] L_BKLT_CTRL

C5209
C5212

1
1

1
1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

F5203
1

R5206
1
2
0R0402-PAD

R5232

69.60040.001
2 POLYSW-1D1A24V-2-GP

0R3J-0-U-GP

EE note: Never change R5232 to short pad after MP

Reserved for one time fuse: 69.43001.201

EDP_AUX#
EDP_AUX

1
LCDVDD_EN

3
[24] LCD_TST_EN

TPAN_VDD_F
EDP_TX1#
EDP_TX1

[15] EDP_VDD_EN

R5230
0R0603-PAD-1-GP-U
2

3D3V_S0
R5202
100KR2J-1-GP

BAT54C-7-F-3-GP

75.00054.E7D
2nd = 83.R2003.W81

U5201
LCDVDD
1
2
3

3rd = 75.00054.A7D

EN
GND
VOUT

VIN#5
VIN#4

5
4
1

BKLT_CTRL

4th = 83.R2003.V81

RT9724GB-GP

C5204
SC4D7U6D3V3KX-GP

8
7
6
5

SRN100J-4-GP
EDP_HPD_CONN

eDP_BKLT_CTRL

1
2
3
4

LCD_TST_C
LCD_BRIGHTNESS
BLON_OUT_C

DY

CAM_EDP

TR5209
USB_CAMERA_EDP#

AFTP5214

USB_PN4 [16]
USB_PP4 [16]

FILTER-4P-6-GP

2 0R2J-2-GP

DY

AFTP5201
AFTP5202
AFTP5204
AFTP5209

USB_PP4_EDP

3
4

Layout Note: Reduce the stubs.

1
1
1
1

USB_PN4_EDP

DY

SRN0J-6-GP

D5202

EDP_HPD_CONN
LCDVDD_LCD
DCBATOUT_LCD
TP_RS

69.10103.041 CAM_EDP
USB_CAMERA_EDP

DY

SRN100KJ-5-GP

0R3J-0-U-GP
R5231

AFTP5203
AFTP5205
AFTP5207
AFTP5206
AFTP5208
AFTP5213
AFTP5210
AFTP5211
AFTP5212
AFTP5222
AFTP5228
AFTP5225
AFTP5226
AFTP5227

USB_PN4_CAM# 2
1
USB_PP4_CAM

69.10103.041

Layout Note: Reduce the stubs.

1
1
1
1
1
1
1
1
1
1
1
1
1
1

DY
SC6D8P50V2DN-GP

1 R5204

RN5205

USB_CAMERA

EC5206

DY
SC6D8P50V2DN-GP

USB_PP6_TPNL

RN5204
2
3
1CAM_EDP
4

USB_PN6 [16]

DMIC_CLK_EDP
DMIC_DATA_EDP

LCD_BRIGHTNESS
BLON_OUT_C
LCD_TST_C
EDP_AUX
EDP_AUX#
EDP_TX0#
EDP_TX0
EDP_TX1#
EDP_TX1
DMIC_CLK_C
DMIC_DATA_C
USB_CAMERA#
USB_CAMERA
3D3V_CAMERA_S0

0R2J-2-GP

CAM1_MIC_GND

1 R5203

Touch Panel

DY

ZZ.F2191.00801

TPAN_VDD
1 R5201

DM-ACES-CON8-44-GP-01

R5209
0R2J-2-GP

0R0402-PAD

20.K0678.040

R5207

TR5208

USB_PN6_TPNL

USB_PN6_TPNL
USB_PP6_TPNL
TP_RS
TP_RESET

[20]

For AUDIO Grade B or C selection.

3D3V_CAMERA_S0

C5207
SC4D7U6D3V3KX-GP

CAM1_MIC_GND

10
PANEL_SIZE_ID

DY

DMIC_CLK_C
DMIC_DATA_C

Camera

USB_CAMERA_EDP#
USB_CAMERA_EDP

1 R5212

R5210
PANEL_SIZE_ID_CONN
TP_RESET

MIC_GND

1
EC5210

3D3V_S0

EDP_TX1#
EDP_TX1

DMIC_CLK_EDP
DMIC_DATA_EDP

DY

69.60040.001

0R0402-PAD

C5202
SC33P50V2JN-3GP

1 R5224

C5205

2
1

1
2

DBC_EN_R
C5206
SC1U10V2KX-1GP

0R3J-0-U-GP

POLYSW-1D1A24V-2-GP

SC1KP50V2KX-1GP

EDP_TX0#
EDP_TX0

SCD1U16V2KX-3GP

DBC_EN_R
EDP_HPD_CONN
LCD_TST_C
EDP_AUX
EDP_AUX#

42

TP_RESET

R5229

Trace width = 80mil

C5201

EE note: Never change R5211 to short pad after MP

LCDVDD_LCD

DCBATOUT_LCD

3D3V_CAMERA_S0

DCBATOUT_LCD

2 0R5J-5-GP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

EE note: Never change R5229 to short pad after MP

Reserved for one time fuse: 69.43001.201
3D3V_S0

DCBATOUT

R5211

LCDVDD

LCD1
41

CAM1

LCDVDD_LCD

Layout Note:

74.09724.09F

Trace width = 80mil

eDP_BKLT_CTRL
B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

LCD/Inverter CONN
Document Number

Rev

A00

Janus HSW 40/50/70

Monday, February 10, 2014

Sheet
1

52

of

104

(Blanking)
C

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

(Reserved)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

53

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

HDMI Level Shifter/Connector

Document Number

Sheet
1

54

Rev

X02

Janus HSW 40/50/70

Friday, February 07, 2014

of

104

CRT Board Connector

5V_CRT_S0_R
5V_CRT_S0

CRT_R
CRT_G
CRT_B

1
2
3

CRT_VSYNC_CON
CRT_HSYNC_CON

14
13

DDCDATA_ID1
DDCCLK_ID3
CRT_RED
CRT_GREEN
CRT_BLUE
VSYNC
HSYNC

4
11
5V_CRT_S0_R

GND
GND
GND
GND
GND
GND
GND

5
6
7
8
10
16
17

5V_CRT_S0
D5501

F5501
1

A
RB551V30-GP

POLYSW-1D1A6V-9-GP-U

12

CRT RGB
CRT H/VSYNC
CRT SMBUS

5V_S0

13

12
15

NC#4
NC#11

DY

CRT_DDCDATA_CON
CRT_DDCCLK_CON

VCC_CRT

U5501D
11
D

TC74VHCT125AFTQK2M-GP

83.R5003.H8H

D-SUB 15P

5V_CRT_S0

69.48001.081

D-SUB-15-252-GP

2ND = 69.50011.081
3RD = 69.50013.101

020.20020.0015

Hsync & Vsync level shift

68.00084.A11
2nd = 68.00245.011

U5501C
8

TC74VHCT125AFTQK2M-GP

DY

C5511

DY SC100P50V2JN-L-GP

C5516
SCD01U16V2KX-3GP

DP_CRT_HSYNC_CON

DY

2
CRT_G

2 BLM18BB220SN-GP

DY

14

DP_CRT_G

DY
2

DY

L5501

SC18P50V2JN-1-GP
C5507

68.00084.A11
2nd = 68.00245.011

SC18P50V2JN-1-GP
C5513

CRT_R

2 BLM18BB220SN-GP

SC100P50V2JN-L-GP
C5515

DP_CRT_R

CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON

L5503

9
5V_CRT_S0

10

14

C5519
2DY 1

14

CRT1
SCD01U16V2KX-L1-GP

DY

U5501A
3

HSYNC_5

2
1

R5503

C5521
SC10U6D3V3MX-GP

7
AVCC33
1
C5517
VCCK_12
1
C5503
3D3V_S0
1
3D3V_S0
1C5520
C5522
VCCK_12
1
C5501
1
1C5504 VDD_DAC_33
1C5524
C5502
LDO_EN

24
25
5
20
19
9
21

C5527 1
C5528 1

2SCD1U16V2KX-3GP
2SCD1U16V2KX-3GP

PCH_DPC_AUXP_U
PCH_DPC_AUXN_U

26
27

[8] PCH_DPB_P0
[8] PCH_DPB_N0

C5529 1
C5526 1

2SCD1U16V2KX-3GP
2SCD1U16V2KX-3GP

PCH_DPC_P0_U
PCH_DPC_N0_U

29
30

[8] PCH_DPB_P1
[8] PCH_DPB_N1

C5530 1
C5525 1

2SCD1U16V2KX-3GP
2SCD1U16V2KX-3GP

PCH_DPC_P1_U
PCH_DPC_N1_U

31
32

[15] PCH_DPB_AUXP
[15] PCH_DPB_AUXN

CRT_HSYNC_CON
CRT_VSYNC_CON

TC74VHCT125AFTQK2M-GP

R55111
R55071

2 33R2J-2-GP
2 33R2J-2-GP

1
2

U5502

2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP2
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP2
SC2D2U10V3KX-1GP
2
SCD1U16V2KX-3GP2
SC10U6D3V3MX-GP

C5523
SC10U6D3V3MX-GP

VDD_DAC_33

0R0603-PAD-1-GP-U

DY

AVCC_33

HPD

AVCC_12

SMB_SCL
SMB_SDA

DVCC_33
DVCC_33

CLK_DP2VGA

XI
2
CRT_DEBUG

17
18

0R2J-2-GP

RRX

28

CRT_PCH_HPD

CRT_PCH_HPD

2
3

VDD_DAC_33
LDO_EN
AUX_P
AUX_N
LANE0P
LANE0N
LANE1P
LANE1N
XI/CKIN
XO

CRT_PCH_HPD

PCH_SMBCLK [12,18,62,96]
PCH_SMBDATA [12,18,62,96]

4
6

CRT_DDCCLK_CON
CRT_DDCDATA_CON

7
8

DP_CRT_VSYNC_CON
DP_CRT_HSYNC_CON

VCCK_12

R5506
[18] CLK_DP2VGA

VGA_SCL
VGA_SDA

[15]

SRN0J-6-GP
1
4
2
3

R5510
100KR2J-4-GP
2

R5504

3D3V_S0

VSYNC_5

CRT_DDCCLK_CON

Layout note:
All cap need close to chip

0R0603-PAD-1-GP-U

DY

RN5501
SRN2K2J-1-GP

AVCC33

RN5502

CRT_DDCDATA_CON
3D3V_S0

DP_CRT_VSYNC_CON

5V_CRT_S0

U5501B

TC74VHCT125AFTQK2M-GP

4
3

1
2

1
2

1
2

1
2

1 R5513

1 R5514
75R2F-2-GP 2

75R2F-2-GP 2

75R2F-2-GP 2

SC4D7P50V2BN-GP
C5518

SC4D7P50V2BN-GP
C5510

SC4D7P50V2BN-GP
C5514

68.00084.A11
2nd = 68.00245.011

SC4D7P50V2BN-GP
C5509

SC4D7P50V2BN-GP
C5512

CRT_B

2 BLM18BB220SN-GP

1
SC4D7P50V2BN-GP
C5506

1 R5501

DP_CRT_B

14

L5502

VSYNC
HSYNC
RED_P
RED_N
GREEN_P
GREEN_N
BLUE_P
BLUE_N
POL1_SDA
POL2_SCL
GND_DAC

RRX

GND

15
16

DP_CRT_R

12
13

DP_CRT_G

10
11
22
23

DP_CRT_B
POL1_SDA
POL2_SCL

14
33

RTD2168-CGT-GP

071.02168.0003
R5505
12KR2F-L-GP

3D3V_S0

R5515
4K7R2J-2-GP

R5502
4K7R2J-2-GP

U5504
A0
A1

VCC
WP

VSS

SDA

CRT_DEBUG
A2
SCL

8
7
6
5

POL2_SCL
POL1_SDA

R5516

R5512
4K7R2J-2-GP

CAT24C128WI-GT3-GP

DY

72.24128.J01

ROM4K7R2J-2-GP DY
1

1
2
3
4

LDO_EN

POL2_SCL

POL1_SDA

EEPROM/ROM

EEPROM

R5508
4K7R2J-2-GP

3D3V_S0

3D3V_S0

3D3V_S0

R5509
4K7R2J-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

(Reserved)DP to VGA Converter

Document Number

Rev

X02

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

55

of

104

SSID = SATA

SATA HDD Connector

HDD1

[19] SATA3_PTX_HDDRX_P0
[19] SATA3_PTX_HDDRX_N0
[19] SATA3_PRX_HDDTX_P0
[19] SATA3_PRX_HDDTX_N0

SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP

2
2

1 C5602
1 C5603

SATA_TXP0_R
SATA_TXN0_R

1
1

2 C5615
2 C5616

SATA_RXP0_R
SATA_RXN0_R

V5
V5
V5

P13
P14
P15

V12
V12
V12

S2
S3

TX+
TX-

S6
S5

23
24

NP1
NP2

NP1
NP2

GND
GND
GND
GND
GND
GND
GND
GND

S1
S4
S7
P4
P5
P6
P10
P12

Layout Note:
Place near HDD1

1A

U5602

5V_S0
SATA_TXP0_R
SATA_TXN0_R

SATA_TXP0_R
SATA_TXN0_R

10
9
8
7
6

LINE_1 NC#10
LINE_2
NC#9
GND DY GND
LINE_3
NC#7
LINE_4
NC#6

SATA_RXN0_R
SATA_RXP0_R

C5606

DY

RX+
RXDAS/DSS P11
SATA_HDD
SKT-SATA7P-15P-159-GP

1
2
3
4
5

SATA_RXN0_R
SATA_RXP0_R

5V_S0

23
24

P7
P8
P9

V33
V33
V33

SC10U10V5KX-2GP
2
1
C5605

P1
P2
P3

AZ1045-04F-R7G-GP
SCD1U16V2KX-3GP

75.01045.073
Swap based on the swap report.

022.10019.0001

Close to HDD1

2ND = 022.10019.0021

ME Note: New HDD conn symbol is not ready,

we will use original OAK HDD conn (22.10300.991) and shift to the correct position.

ODD Connector

SATA Zero Power ODD

ODD_PW R_5V

3D3V_S0

ODD1

2 SATA_ODD_PW RGT

SKT-SATA7P+6P-57-GP-U

5V_S0

2 0R0402-PAD

SATA_ODD_PRSNT# [19]

C5609

SATA_ODD_PRSNT#

[20] SATA_ODD_PW RGT

SATA_TXN2_R
SATA_TXP2_R

C5611 1
C5612 1

2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP

SATA_PRX_ODDTX_P2 [19]
SATA_PRX_ODDTX_N2 [19]

2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP

SATA_PTX_ODDRX_N2 [19]
SATA_PTX_ODDRX_P2 [19]

DY

R5604
10KR2J-3-GP

SC10U10V5KX-2GP

DY

2
3

IN#2
IN#3

EN/EN#

C5608 1
C5607 1

SATA_RXP2_R
SATA_RXN2_R

U5601

100KR2J-1-GP

SATA_ODD_DA# [20]

Current limit
Active High
typ =>2.5A

FLT#

OUT#6
OUT#7
OUT#8

6
7
8

GND
GND

1
9

ODD_PW R_5V

5V_S0

100 mil

ODD_PW R_5V
R5603

C5610

DY

0R5J-5-GP
SC10U10V5KX-2GP

TPS2001CDGNR-GP

74.02001.079
2nd = 74.02311.079

NP2
15

ODD_PW R_5V

R5602
SATA_ODD_DA#_C

1
S7
S6
S5
S4
S3
S2
S1

2.5A

R5607

1
6
5
4
3
2

14
NP1

20.81152.013

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

HDD/ODD

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet

56

A00
of

104

SSID = ESATA

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

ESATA
Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

57

A00
of

104

WLAN1

3D3V_S0

TP5801

TP5802
R5804 1

[24] E51_TXD
[24] WIFI_RF_EN
2

WLAN_ACT
BT_ACT

E51_RX
20R2J-2-GP E51_TX

DY

3D3V_S0

DY

R5805 1

[20] BLUETOOTH_EN
5V_S0

R5801

2 0R0402-PAD

DY

2+5V_MINI_DEBUG
0R2J-2-GP

1
1

TP5804
TP5803

R5807
0R2J-2-GP
1 DY
2

CARD_WLAN_OUT#
CARD_WPAN_OUT#

DEBUG

1.5V

3.3V/MS_V3

REFCLK+
REFCLK-

13
11

CLK_PCIE_WLAN_P3 [18]
CLK_PCIE_WLAN_N3 [18]

MS_TX+/PERN0
MS_TX-/PERP0

23
25

PCIE_PRX_WLANTX_N3 [16]
PCIE_PRX_WLANTX_P3 [16]

MS_RX-/PETN0
MS_RX+/PETP0

31
33

PCIE_PTX_WLANRX_N3_C [16]
PCIE_PTX_WLANRX_P3_C [16]

28
48

+1.5V
+1.5V

52

+3.3V/MS_V3

24

+3.3VAUX/MS_V3

USB_DUSB_D+

36
38

3
5
8
10
12
14
16
17
19
20
37
39
41
43
45
47
49
51

RESERVED#3
SMB_CLK
RESERVED#5
SMB_DATA
RESERVED#8
RESERVED#10
RESERVED#12
WAKE#
RESERVED#14
CLKREQ#
RESERVED#16
PERST#
RESERVED#17
RESERVED#19
RESERVED#20
GND
RESERVED#37
GND
RESERVED#39/MS_V3
GND
RESERVED#41/MS_V3
GND
RESERVED#43
GND
RESERVED#45
GND
RESERVED#47
GND
RESERVED#49
GND
RESERVED#51
GND
GND
GND
LED_WWAN#
GND
LED_WLAN#
GND
LED_WPAN#
GND

30
32

42
44
46

MINI_PCI 52P

USB_PN5_R
USB_PP5_R

1
7
22

CLK_PCIE_WLAN_REQ3# [15,18]
PLT_RST#
[17,24,30,36,52,65,73,96]

4
9
15
18
21
26
27
29
34
35
40
50
53
54

NP1
NP2

3D3V_S0

Mini Card Connector(802.11a/b/g)

SSID = Wireless

R5806
0R2J-2-GP
BT_ACT 1

NP1
NP2

SKT-MINI52P-81-GP-U1

62.10043.C81

1.1A
3D3V_S0

SCD1U16V2KX-3GP

C5804
2

SC10U10V5KX-2GP

C5803
2

SCD1U16V2KX-3GP

C5802

USB_PN5_R
USB_PP5_R

R5802 1

2 0R0402-PAD

USB_PN5

R5803 1

2 0R0402-PAD

USB_PP5 [16]

[16]

<Core Design>

WLAN_ACT

2
5

Wistron Corporation

C5807

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

SCD1U16V2KX-3GP

DY
A

Title

Mini Card (WLAN)

Size
A4

Document Number

Date: Friday, February 07, 2014

4

Rev

Janus HSW 40/50/70

2

Sheet

A00
58

of
1

104

(Blanking)
3

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

A

Reserved

Sheet

59

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)

Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Sheet

60

of
1

A00
104

SSID = User.Interface

Power button
SW1

R6102
1

[24] KBC_PWRBTN#

KBC_PWRBTN#_C

100R2J-2-GP
AFTP6801

4
3
2
1

EC6104
SCD1U25V2KX-GP

DY

5
ETY-CON4-34-GP

20.K0465.004

AFTP6802

2nd = 20.K0422.004

Battery LED1 (AMBER_LED)

Low actived from KBC GPIO

3RD = 20.K0382.004
C

5V_S5
Q6104
R2
1 R6104

2CHG_AMBER_LED_R# B

R1

[24] CHG_AMBER_LED#

E
C

0R0402-PAD

R6103
AMBER_LED_BAT

BAT_AMBER

499R2F-2-GP

DDTA144VCA-7-F-GP
1

AMBER

DY
2

84.00144.N11

EC6105
SC220P50V2KX-3GP

BAT_AMBER

[63]

BAT_WHITE

[63]

5V_S5
Q6103
R2
1 R6105

2BATT_WHITE_LED_R# B

R1

[24] BATT_WHITE_LED#

E
C

0R0402-PAD

R6101
WHITE_LED_BAT

BAT_WHITE

WHITE

330R2J-3-GP
1

DDTA144VCA-7-F-GP

DY EC6103
SC220P50V2KX-3GP
2

84.00144.N11

<Core Design>

Battery LED2 (WHITE_LED)

Low actived from KBC GPIO

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LED Bard/Power Button

Size
A4

Document Number

Date:
5

Sheet

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

61

of
1

104

SSID = Touch.Pad

Internal Keyboard Connector (DVC40)

3D3V_S5

BDW: Support PTP

3D3V_S0

R6213
0R2J-2-GP

R6212
0R2J-2-GP

HSW

BDW

PS2

20.K0592.030

[24]
[24]

I2C

2nd = 20.K0565.030

[20]
[20]

3rd = 20.K0621.030

RN6202 1
2

TPCLK
TPDATA

RN6203 2
1

I2C1_SCL
I2C1_SDA

2
1

TPCLK_C

1
9

5V_S0

DY
DY

2 R6204
2 R6210

I2C1_SCL_R
I2C1_SDA_R

AFTP6235

3D3V_S0

R6216
0R2J-2-GP

ATTN

GPIO

DAT(PS2)

CLK(PS2)

20.K0665.008
2nd = 20.K0667.008

Need to check if it is Active High or Active Low

and check if there is PH on TPAD side.
C

TP side has pull high

2

I2C1_SCL_R

INT_TP#

BDW

I2C1_SDA_R

I2C1_SDA

TP_VDD
TPCLK_C
TPDATA_C
I2C1_SCL_R
I2C1_SDA_R
INT_TP#
TP_LID_CLOSE#

AFTP6239
AFTP6238
AFTP6236
AFTP6237
AFTP6240
AFTP6241
AFTP6242

1
1
1
1
1
1
1

KBBL C6202

R6205

Q6204

69.50007.921

1KBBL

GND

10KR2J-3-GP

DY

CLK(I2C)

R6203
Q6204_G

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

+5V_KB_BL
F6201

DAT(I2C)

ETY-CON10-22-GP-U

2N7002KDW-GP
I2C1_SCL

Keyboard Backlight (DVC70)

POLYSW-D5A6V-1-GP

VDD

TP_VDD

RN6204
SRN10KJ-5-GP

3
4

1
2

DY

SC33P50V2JN-3GP
EC6205

DY

5V_S0

DY

R6217
0R2J-2-GP

2
1

1KR2J-1-GP

8
7
6
5
4
3
2

TP_LID_CLOSE#
TPDATA_C

0R2J-2-GP 1
0R2J-2-GP 1

[12,18,96] PCH_SMBCLK
[12,18,96] PCH_SMBDATA

0R3J-0-U-GP

SCD1U16V2KX-3GP
KBLIT1
5
1
R6206

KB Backlight Power Consumption: 285mA max.

C6203

KBBL

1
31

6
ACES-CON4-56-GP

20.K0800.004

2ND = 20.K0841.004

AFTP6245
B

Q6202
DMN3404L-7-GP

84.03404.C31

DY

R6208
100KR2J-1-GP

ACES-CON30-10-GP

KBBL

[24] KB_BL_CTRL

20.K0592.030
2nd = 20.K0565.030
3rd = 20.K0621.030

2
3
4

51KR2J-1-GP

R6207
DY
100KR2J-1-GP

KBBL

SCD1U16V2KX-3GP

[20] KB_LED_BL_DET

KB_LED_DET_C

KBBL 2

KB_BL_CTRL#

DY

SC33P50V2JN-3GP
EC6206

KB2
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

I2C1_SCL_R
I2C1_SDA_R

SMBUS

CAP_LED

Internal Keyboard Connector (DVC50/DVC70)

KROW7
KROW6
KROW4
KROW2
KROW5
KROW1
KROW3
KROW0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
CAP_LED

3
4

[15,20,24] INT_TP#
[24] TP_LID_CLOSE#

10
I2C1_SDA_R
I2C1_SCL_R

R6211
4K7R2J-2-GP

TP_VDD
1

Need to check with SW.

KB_DET#

DY

DY DY

84.00144.N11

[20]

HSW

SRN33J-5-GP-U

R6201
CAP_LED_Q

Pin number Pin name

TPAD1

SCD1U16V2KX-3GP
1

DDTA144VCA-7-F-GP

SRN33J-5-GP-U
TPCLK_C
4
TPDATA_C
3

R1

Touch Pad Connector

E
C

0R2J-2-GP

R2

0R0402-PAD

SC33P50V2JN-3GP
EC6204

TP_LID_CLOSE#

DY

R6209

C6201

SC33P50V2JN-3GP
EC6203

CAP_LED_R#

TP_VDD

5V_S0

Q6201
2

DY

10KR2J-3-GP

RN6201
SRN10KJ-5-GP

SC33P50V2JN-3GP
EC6202

1 R6202

R6215

TP_VDD

EC6201
SC33P50V2JN-3GP

[24] CAP_LED#

84.02130.031
2ND = 84.03413.A31

ACES-CON30-10-GP

CAP LED Control

LOW actived from KBC GPIO

TP_VDD
2

Q6203
DMP2130L-7-GP

1
31

1KR2J-1-GP
R6214
1
2 TP_ON#_GATE

TP_VDD

TP_ON#

TP_ON#

AFTP6201

[24]

KCOL[0..16]

C6204
SCD1U16V2KX-3GP
Q6203_S
1
2

2
1

[24]

KB1
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

KROW7
KROW6
KROW4
KROW2
KROW5
KROW1
KROW3
KROW0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
CAP_LED

3
4

KROW[0..7]

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

[24]

AFTP6221
AFTP6222
AFTP6230
AFTP6218
AFTP6214
AFTP6227
AFTP6234
AFTP6228
AFTP6215
AFTP6224
AFTP6213
AFTP6223
AFTP6231
AFTP6208
AFTP6206
AFTP6226
AFTP6207
AFTP6233
AFTP6225
AFTP6229
AFTP6203
AFTP6216
AFTP6219
AFTP6220
AFTP6232

AFTP6202

KB_DET#

[20]

SSID = KBC

+5V_KB_BL
KB_LED_DET_C
KB_BL_CTRL#

1
1
1

AFTP6248
AFTP6246
AFTP6247

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

Key Board/Touch Pad

Document Number

Sheet
1

62

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

of

104

CON1
USB20_VCCB
17

TR6301

USB_PN2_IOBD1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

69.10103.041

3D3V_S0

USB_PP2_IOBD1

USB_PN2 [16]

USB_PP2 [16]

FILTER-4P-6-GP
USB_PN2_IOBD1
USB_PP2_IOBD1

USB2.0 Port3

USB_PN7_IOBD1
USB_PP7_IOBD1

Card Reader
BAT_AMBER
BAT_WHITE

[61]
[61]

LED

18
PTWO-CON16-2-GP
TR6302

20.K0382.016

USB_PN7_IOBD1

69.10103.041
USB_PP7_IOBD1

USB_PN7 [16]

USB_PP7 [16]

FILTER-4P-6-GP
B

The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA

USB20_VCCB

DY

TC6301
SC100U6D3V6MX-GP

78.10710.52L

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

IO Board Connector

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

Sheet

A00

63

of
1

104

SSID = User.Interface
3D3V_S5
D

R6401
100KR2J-1-GP

DY
LID_CLOSE#

[24] LID_CLOSE#

3D3V_S5

C6402

1
2
3

VSS
VDD
OUT

LIDSW1

S-5712ACDL1-M3T1U-GP
2

C6401
SCD047U25V2KX-GP
SCD1U16V2KX-3GP

DY

74.05712.0BB

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Hall Sensor

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

A00

Janus HSW 40/50/70

2

Sheet

64

of
1

104

SSID = DEBUG PORT

Debug Connector

Layout Note:

Place near trace separated point 3D3V_S0

[18,24] LPC_AD[3..0]

LPC_AD[3..0]
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

[18,24] LPC_FRAME#
[17,24,30,36,52,58,73,96] PLT_RST#

R6501
R6502

1
2
3
4

11
1

RN6501
SRN0J-7-GP-U
8
7
DEBUG6
5

1
DEBUG
1
DEBUG

DB1

2
2 0R2J-2-GP
0R2J-2-GP

LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R
LPC_FRAME#_DEBUG
PLT_RST#_DEBUG

2
3
4
5
6
7
8
9
10
12

[18] CLK_PCI_LPC

PAD-10P-177042-GP

ZZ.00PAD.Y41
20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41
DB1 Optional: New one smaller LPC connector is 20.F1180.010.

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Dubug connector

Sheet

65

A00
of

Rev
104

(Blanking)
C

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Rev

Janus HSW 40/50/70

Date: Friday, February 07, 2014

5

Reserved

Sheet

66

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

67

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

RESERVED

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

A00
68

of

104

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

USB3.0 PORT

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

69

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

70

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

71

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

72

A00
of

104

3V3_AON_S0

PDP-06877-006

R7312
GC6_20 10KR2J-3-GP

dGPU Reset
1

[15] DGPU_HOLD_RST#
[17,24,30,36,52,58,65,96]

PLT_RST#

A
B

GPU_PEX_RST#

1
GPU_PEX_RST_D#

GC6_20

SYS_PEX_RST_MON#

BAT54A-1-GP

[76]

75.00054.X7D

To GPIO8

OPS

R7306
100KR2F-L1-GP

1D05V_VGA_S0

Place close Chip

3rd = 75.BAT54.07D
4th = 75.00054.Y7D

AG9
AG10

[16] dGPU_RXP_C_CPU_TXP3
[16] dGPU_RXN_C_CPU_TXN3

AB13
AC13
AF10
AE10
AD14
AC14
AE12
AF12
AC15
AB15

AB16
AC16
AF13
AE13

GPIO0

AD17
AC17
AE15
AF15

GPIO45 (PCH)
GPIO96(KBC)
GPIO47 (PCH)

GPIO6

GPIO51(KBC)

AC18
AB18
AG15
AG16
AB19
AC19

GPIO54(PCH)
GPIO8

AF16
AE16
AD20
AC20

GPIO21

AE18
AF18
AC21
AB21
AG18
AG19
AD23
AE23
AF19
AE19

PEX_RST#

AG21
AG22

SC10U6D3V3MX-GP
2

SC10U6D3V3MX-GP
2

SC10U6D3V3MX-GP
2

1
2

SC10U6D3V3MX-GP
2
1

SC10U6D3V3MX-GP
2

OPS

PEX_RX4
PEX_RX4#
PEX_TX5
PEX_TX5#

PEX_PLL_HVDD
PEX_PLL_HVDD

PEX_RX5
PEX_RX5#
PEX_SVDD_3V3

AA8
AA9

3.3V +/- 5%
210mA

3V3_AON_S0

AB8

PEX_TX6
PEX_TX6#

Place close Chip

OPS

PEX_RX6
PEX_RX6#
PEX_TX7
PEX_TX7#
PEX_RX7
PEX_RX7#
PEX_TX8
PEX_TX8#

NC
NC

PEX_RX8
PEX_RX8#

NC
NC

PEX_TX9
PEX_TX9#

NC
NC

VDD_SENSE

PEX_RX9
PEX_RX9#

NC
NC

GND_SENSE

PEX_TX10
PEX_TX10#

NC
NC

PEX_RX10
PEX_RX10#

NC
NC

PEX_TX11
PEX_TX11#

NC
NC

PEX_RX11
PEX_RX11#

NC
NC

PEX_TX12
PEX_TX12#

NC
NC

PEX_RX12
PEX_RX12#

NC
NC

PEX_TX13
PEX_TX13#

NC
NC

PEX_RX13
PEX_RX13#

NC
NC

PEX_TX14
PEX_TX14#

NC
NC

PEX_RX14
PEX_RX14#

NC
NC

PEX_TX15
PEX_TX15#

NC
NC

PEX_RX15
PEX_RX15#

NC
NC

GF119

GF117
GK208

C7315 OPS C7324 OPS

F2

VGACORE_VDD_SENSE_1

[82]

F1

VGACORE_GND_SENSE_1

[82]

POWER IC
B

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

AF22 PEXTSTCLK_OUT
AE22 PEXTSTCLK_OUT#

R7307
200R2F-L-GP
DY 2

L7301
1D05V_VGA_S0

Place close VDD ball

PEX_PLLVDD
PEX_PLLVDD

AA14
AA15

Place close Chip

VCC1R05VIDEO_PEX_PLLVDD

C7317

OPS

R7302

OPS
PEX_TERMP

OPS
2

1.05V +/- 30mV

150mA

68.00335.151
C7318

TESTMODE

MHC1608S121PBP-GP
1

AD9 TESTMODE 1 OPS

2
10KR2F-2-GP

R7301
AF25 PEX_TERMP 1 OPS
2K49R2F-GP

OPS

C7319
SC1U10V2KX-1GP

AE21
AF21
AG24
AG25

C7328

OPS

PEX_TX4
PEX_TX4#

SC4D7U6D3V3KX-GP

AF24
AE24

C7327

OPS

PEX_RX3
PEX_RX3#

SC4D7U6D3V3KX-GP

AG12
AG13

PEX_TX3
PEX_TX3#

SC4D7U6D3V3KX-GP

GPIO51(PCH)

GPIO5

PEX_RX2
PEX_RX2#

C7321

OPS

AC12
AB12

C7320

OPS

dGPU_TXP_CPU_RXP3
dGPU_TXN_CPU_RXN3

OPS

C7309

SC10U6D3V3MX-GP
2

2SCD22U10V2KX-1GP
2SCD22U10V2KX-1GP

OPS

C7314

C7307 1OPS
C7308 1OPS

[16] CPU_RXP_C_dGPU_TXP3
[16] CPU_RXN_C_dGPU_TXN3

OPS

C7311

[16] dGPU_RXP_C_CPU_TXP2
[16] dGPU_RXN_C_CPU_TXN2

PEX_TX2
PEX_TX2#

SC10U6D3V3MX-GP
2

AE9
AF9

PEX_RX1
PEX_RX1#

SC10U6D3V3MX-GP
2

AD11
AC11

SC4D7U6D3V3KX-GP

dGPU_TXP_CPU_RXP2
dGPU_TXN_CPU_RXN2

SC1U10V2KX-1GP

2SCD22U10V2KX-1GP
2SCD22U10V2KX-1GP

SC1U10V2KX-1GP

C7305 1OPS
C7306 1OPS

[16] CPU_RXP_C_dGPU_TXP2
[16] CPU_RXN_C_dGPU_TXN2

PEX_TX1
PEX_TX1#

Place close Chip

AF7
AE7

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AB10
AC10

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

dGPU_TXP_CPU_RXP1
dGPU_TXN_CPU_RXN1

OPS

1D05V_VGA_S0

Place close VDD ball

PEX_RX0
PEX_RX0#

2SCD22U10V2KX-1GP
2SCD22U10V2KX-1GP

PEX_TX0
PEX_TX0#

C7326

OPS

1.05V +/- 30mV

3.3A

C7303 1OPS
C7304 1OPS

[16] CPU_RXP_C_dGPU_TXP1
[16] CPU_RXN_C_dGPU_TXN1

PEX_REFCLK
PEX_REFCLK#

C7325

OPS

AG6
AG7

[16] dGPU_RXP_C_CPU_TXP0
[16] dGPU_RXN_C_CPU_TXN0

[16] dGPU_RXP_C_CPU_TXP1
[16] dGPU_RXN_C_CPU_TXN1

AC9
AB9

dGPU_TXP_CPU_RXP0
dGPU_TXN_CPU_RXN0

AA22
AB23
AC24
AD25
AE26
AE27

C7322

OPS

SCD1U16V2KX-3GP
2

AE8
AD8

2SCD22U10V2KX-1GP
2SCD22U10V2KX-1GP

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_CLKREQ#

AC6

NC

PEX_RST#

GPU_CLKREQ#

PEX_WAKE#

C7323

C7316

C7301 1OPS
C7302 1OPS

[16] CPU_RXP_C_dGPU_TXP0
[16] CPU_RXN_C_dGPU_TXN0

DY

AC7

[18] CLK_PCIE_VGA
[18] CLK_PCIE_VGA#

84.2N702.J31

R7305
0R2J-2-GP

GPU_PEX_RST#

2N7002K-2-GP

OPS

AB6

NON_GC6
1
0R2J-2-GP

SCD1U16V2KX-3GP

SYS_PEX_RST_MON#

R7313

OPS 10KR2J-3-GP

2
R7303
G
D

OPS

C7310
SC4D7U6D3V3KX-GP

Q7301

[18] PEG_CLKREQ#

GK208/GF117/GF119

OPS

C7313
SC1U10V2KX-1GP

1/14 PCI_EXPRESS

OPS

C7312
SC1U10V2KX-1GP

1 OF 14

GPU1A

GPU_PEX_RST# [76]

3V3_AON_S0

R7304

2ND = 73.7SZ08.EAH
3RD = 73.01G08.L04
1
DY 2 0R2J-2-GP

Place close VDD ball

2nd = 75.00054.R7D

73.01G08.EHG

[76]

SYS_PEX_RST_MON#

0R2J-2-GP

U74LVC1G08G-AL5-R-GP-U

OPS

GPU_PEX_RST_HOLD

GC6_20

VCC

GND

D7301
R7308

3V3_AON_S0
U7301

From GPIO21

2
A

N14M-GE-S-A2-GP

71.0N14M.B0U
<Core Design>

N15V-GM-S-A2: 071.0N15V.0A0U
N15V-GM-S is GF117.
N15S-GT is GM108.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_PCIE/STRAPPING(1/5)
Size
A2
Date:
5

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet

73

of

A00
104

LVDS Interface
7 OF 14

GPU1G
4/14 IFPAB

GM108

GF117

GM108
AA6

IFPAB_PLLVDD

V7
W7

GF119/GK208

GF117

IFPAB_RSET

NC

GF119/GK208
NC
NC

IFPA_TXC#
IFPA_TXC

NC
NC

IFPA_TXD0#
IFPA_TXD0

GF119/GK208

U6

GF117
GF117

NC

IFPD_RSET

NC
NC

T7
R7

IFPD_PLLVDD

NC

IFPD_PLLVDD

NC

NC
NC

AA1
AB1

IFPA_TXD2#
IFPA_TXD2

NC
NC

IFPC_PLLVDD

AA2
AA3

IFPA_TXD1#
IFPA_TXD1

NC
NC

AA5
AA4

IFPA_TXD3#
IFPA_TXD3

IFPD
GM108
W6

NC
NC

IFPB_TXD4#
IFPB_TXD4

NC
NC

IFPB_TXD5#
IFPB_TXD5

NC
NC

IFPB_TXD6#
IFPB_TXD6

NC
NC

IFPB_TXD7#
IFPB_TXD7

AB4
AB5

NC

IFPB_IOVDD

NC

RN7402
SRN10KJ-5-GP

AB2
AB3

IFPC_IOVDD

AD2
AD3

DP

DY

AD1
AE1

I2CX_SDA IFPD_AUX_I2CX_SDA#
I2CX_SCL
IFPD_AUX_I2CX_SCL

NC
NC

TXC
TXC

IFPD_L3#
IFPD_L3

NC
NC

TXD0
TXD0

IFPD_L2#
IFPD_L2

NC
NC

TXD1
TXD1

IFPD_L1#
IFPD_L1

NC
NC

TXD2
TXD2

IFPD_L0#
IFPD_L0

P4
P3
R5
R4
T5
T4
U4
U3
V4
V3

GM108
R6

IFPD_IOVDD

NC

GF119/GK208

GF117

NC

GPIO17

D4

RN7401
SRN10KJ-5-GP
N14M-GE-S-A2-GP

71.0N14M.B0U

1
2

1
2

DY

IFPB_TXC#
IFPB_TXC

GF117

IFPA_IOVDD

4
3

Y6

NC
NC

4
3

GF119/GK208

IFPAB_IOVDD

GF119/GK208
DVI/HDMI

GM108

NC

IFPAB_PLLVDD

6/14 IFPD

Y3
Y4

NC

IFPAB_PLLVDD

9 OF 14

GPU1I

AC4
AC3

AD5
AD4

OPS

GM108
NC

IFPAB

B3

GPIO14

N14M-GE-S-A2-GP

71.0N14M.B0U
OPS
10 OF 14

GPU1J
7/14 IFPEF

GM108

HDMI Interface

GF119

IFPEF_PLLVDD
8 OF 14

GPU1H

T6

5/14 IFPC

GM108

GF119/GK208

GF117

GM108

IFPC_RSET

NC

GF117

IFPC_PLLVDD
IFPC_PLLVDD

NC
NC

NC
NC

K7

I2CW_SDA IFPC_AUX_I2CW_SDA#
I2CW_SCL
IFPC_AUX_I2CW_SCL

NC
NC

TXC
TXC

IFPC_L3#
IFPC_L3

NC
NC

TXD0
TXD0

IFPC_L2#
IFPC_L2

NC
NC

TXD1
TXD1

IFPC_L1#
IFPC_L1

NC
NC

TXD2
TXD2

IFPC_L0#
IFPC_L0

N5
N4

IFPC_IOVDD

NC

NC

GPIO15

DVI-DL

DVI-SL/HDMI

DP

NC
NC

I2CY_SDA
I2CY_SCL

I2CY_SDA
I2CY_SCL

NC
NC

TXC
TXC

TXC
TXC

IFPE_L3#
IFPE_L3

NC
NC

TXD0
TXD0

TXD0
TXD0

IFPE_L2#
IFPE_L2

NC
NC

TXD1
TXD1

TXD1
TXD1

IFPE_L1#
IFPE_L1

NC
NC

TXD2
TXD2

TXD2
TXD2

IFPE_L0#
IFPE_L0

IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL

NC

NC

R3
R2
NC

IFPEF_IOVDD

H6
J6

K3
K2
M3
M2
M1
N1

HPD_E

GM108
GPIO18

HPD_E

C2

GF117
GK208

GF119

T3
T2

J1
K1

NC FOR GK208

IFPE

R1
T1

J3
J2

IFPE_IOVDD

NC

IFPF_IOVDD

NC

C3

GF119/GK208

GF117

GM108

DVI-DL

NC
NC

DVI-SL/HDMI
I2CZ_SDA
I2CZ_SCL

DP

IFPF_AUX_I2CZ_SDA#
IFPF_AUX_I2CZ_SCL

H4
H3

RN7404
SRN10KJ-5-GP

71.0N14M.B0U

NC
NC

4
3

4
3

N14M-GE-S-A2-GP

OPS

DY

RN7403
SRN10KJ-5-GP

TXC
TXC

IFPF_L3#
IFPF_L3

NC
NC

TXD3
TXD3

TXD0
TXD0

IFPF_L2#
IFPF_L2

NC
NC

TXD4
TXD4

TXD1
TXD1

IFPF_L1#
IFPF_L1

NC
NC

TXD5
TXD5

TXD2
TXD2

IFPF_L0#
IFPF_L0

J5
J4
K5
K4

1
2

DY

P6

IFPEF_RSET

N3
N2

GM108
IFPD_IOVDD

IFPEF_PLLVDD

GM108

NC

DP

K6
M7
N7

IFPEF_PLLVDD

GF117
GK208

IFPC
GF119/GK208
DVI/HDMI

IFPD_PLLVDD

J7

GF119/GK208

GF117

1
2

IFPF

L4
L3
M5
M4

NC FOR GK208

GF117
NC

GM108
HPD_F

GPIO19

F7

N14M-GE-S-A2-GP

71.0N14M.B0U
OPS
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

GPU Memory(2/5)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

74

of

A00
104

DY
GPU1B

F19
C14
A16
A22
P25
W22
AB27
T27

GM108
FBA_CMD34 FBA_DEBUG0
FBA_CMD35 FBA_DEBUG1

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#

F22
J22

FBA_DEBUG0
FBA_DEBUG1

D24
D25
N22
M22

FBA_CLK0P
FBA_CLK0N
FBA_CLK1P
FBA_CLK1N

R7501 1
R7503 1

DY
DY

1
2

1
2

1
2

10KR2F-2-GP

10KR2F-2-GP

1
2

10KR2F-2-GP

1D35V_VGA_S0

Near GPU

GPU1D
12/14 FBVDDQ

C7520

C7517

SC10U10V5KX-2GP
1
2

C7514

SC4D7U6D3V3KX-GP
2
1

C7513

SC4D7U6D3V3KX-GP
2
1

SC1U10V2KX-1GP
2

C7507

OPS OPS OPS OPS OPS OPS

C

1D35V_VGA_S0

C7515

C7516 C7519

C7521

C7530

C7527

C7528

C7511

C7526

C7504

OPS OPS OPS OPS

C7503

Close to DRAM

C7531

OPS OPS OPS OPS OPS OPS OPS OPS

SC1U10V2KX-1GP
2

1D35V_VGA_S0

C7525

GM108
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON

C7502

OPS OPS

TPAD14-OP-GP

C7501

TPAD14-OP-GP

TP7502

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21

SC1U10V2KX-1GP
2

TP7505

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

SC1U10V2KX-1GP
2

TPAD14-OP-GP

Under GPU
4 OF 14

SC1U10V2KX-1GP
2

TP7504

1.5V +/- 3%
4.88A

TPAD14-OP-GP

SCD1U16V2KX-3GP
2

FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

TP7501

R7512

FBA_CMD15
FBA_CMD16

1
[78]
[78]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
1
[78,79]
[79]
1
[79]
[79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]
[78,79]

OPS

SCD1U16V2KX-3GP
2

FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13

R7511

OPS

SC1U10V2KX-1GP
2

FBA_CMD0 [78]

R7510

OPS

SC1U10V2KX-1GP
2

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

R7509

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

OPS

10KR2F-2-GP

R7508

OPS

SC1U10V2KX-1GP
2

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

E19
C15
B16
B22
R25
W23
AB26
T26

FBA_CMD5
FBA_CMD2
FBA_CMD3
FBA_CMD19
FBA_CMD18

SC1U10V2KX-1GP
2

[78]
[78]
[78]
[78]
[79]
[79]
[79]
[79]

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

10KR2J-3-GP

SC1U10V2KX-1GP
2

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

D19
D14
C17
C22
P24
W24
AA25
U25

OPS

SCD1U16V2KX-3GP
2

[78]
[78]
[78]
[78]
[79]
[79]
[79]
[79]

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

SCD1U16V2KX-3GP
2

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

F3

GF117/GK208

SCD1U16V2KX-3GP
2

[78]
[78]
[78]
[78]
[79]
[79]
[79]
[79]

FB_CLAMP

[20,24,76,83]

SC22U6D3V5MX-2GP

NC
GF119

GC6_FB_EN

SCD1U16V2KX-3GP
2

[79] FBA_D[32..63]

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FB_CLAM

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25

2
0R2J-2-GP
R7518

2/14 FBA

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

R7519
1

2 OF 14

10KR2F-2-GP

[78] FBA_D[0..31]

2 60D4R2F-GP
2 60D4R2F-GP

FBA_CLK0P [78]
FBA_CLK0N [78]
FBA_CLK1P [79]
FBA_CLK1N [79]

D18
C18
D17
D16
T24
U24
V24
V25

1D35V_VGA_S0

Under GPU
R7505
2

OPS

FB_CAL_PD_VDDQ

D22

FB_CAL_PU_GND

C24

FB_CAL_TERM_GND

B25

FB_CAL_PD_VDDQ

40D2R2F-GP

D23

FB_VREF_PROBE
N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

68.00335.051

R7507

OPS

2nd = 68.00334.051

30ohm@100MHZ(ESR=0.01ohm)

R7506

OPS
2

SCD1U16V2KX-3GP
2

71.0N14M.B0U

MHC1608S300QBP-GP
C7518

OPS

51D1R2F-GP

C7506

C7505

FB_CAL_TERM_GND
N14M-GE-S-A2-GP

GF119/GK208

SCD1U16V2KX-3GP
2

TP7503

OPS
OPS OPS

FB_VREF

42D2R2F-GP

H22

GF117

FB_DLLAVDD

Near GPU
FBA_PLL_AVDD

FB_CAL_PU_GND

1D05V_VGA_S0
L7501

35mA

FB_PLLAVDD

Under GPU

P22

SC22U6D3V5MX-2GP
2

FB_PLLAVDD

62mA

FB_PLLAVDD

F16

Sourcer suggest to change to

68.00335.051 from 68.00084.H41.

OPS

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

GPU_DP/LVDS/CRT/GPIO(3/5)
Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

75

of

Rev

A00
104

1D05V_VGA_S0
3V3_AON_S0

DACA_GREEN

NC

DACA_BLUE

L7602
MCB1608S181FBP-GP

OPS 2

1
AG3

1
1

N14M-GE-S-A2-GP

71.0N14M.B0U
OPS

C7604

CORE_PLLVDD
SP_PLLVDD

N6:On co-layout designs,

this ball can be connected
to power rail filter.

C7602

OPS

SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

AF3

L6
M6
N6

68.00909.261
C7601
180ohm@100MHz
C7603
DCR=0.3 ohm
OPS DY
Max current = 300mA

AF4

GPU_PLL_VDD
SP_PLLVDD

111mA

NC

AE3
AE4

(DS-06814-001)

VID_PLLVDD

NC

GF119/GK208

GF117

DY

R7617
49K9R2F-L-GP

DACA_RED

3V3_AON_S0

9/14 XTAL_PLL

VIDEO_CLK_XTAL_SS

OPS

A10

XTAL_SSIN

XTAL_OUTBUFF

C10 N12P_XTAL_OUTBUFF
PDP-06877-006

C11

XTAL_IN

XTAL_OUT

N14M-GE-S-A2-GP

20PF 5% 50V +/-0.25PF 0402

71.0N14M.B0U

OPS R7601
10KR2J-3-GP

OPS

R7603
1MR2J-1-GP
1 DY
2

OPS

27MHZ_IN

27MHZ_OUT

OPS

R7604

0R2J-2-GP

27MHZ_OUT_R

GM:
R7604 = 64.15005.6DL
GT:
C7607 = 78.18034.1FL
C7608 = 78.22034.1FL
R7604 = 64.18015.6DL

OPS
XTAL-27MHZ-85-GP-U

C7608
SC15P50V2JN-2-GP

82.30034.641

2ND = 82.30034.651
3RD = 82.30034.681

OPS

R7602
49K9R2F-L-GP

X7601

C7607
SC15P50V2JN-2-GP

B10
1

DACA_HSYNC
DACA_VSYNC

NC

13 OF 14

GPU1M

NC
NC

OPS

C7606
SC2D2U6D3V2MX-GP

NC

68.00335.051
2nd = 68.00334.051

C7605

OPS

DACA_RSET

MHC1608S300QBP-GP

SRN2K2J-1-GP

Straps

OPS

2
1

DY

SCD1U16V2KX-3GP

TSEN_VREF NC

3
4

AF2

DACA_VREF

I2CA_SCL
I2CA_SDA

B7
A7

AE2

52mA

L7601

RN7603

I2CA_SCL
I2CA_SDA

NC
NC

NC

SCD1U16V2KX-3GP

DACA_VDD

W5

GF119/GK208

GF117

GM108

GF117

3/14 DACA

SC4D7U6D3V3KX-GP

GM108

GF119/GK208

11 OF 14

GPU1K

30ohm@100MHz
DCR=0.04 ohm
Max current = 3000mA

OPS

(RVL-06891-001)N15V-

GM -S

DDR3L Recommended Memories

Strap

3V3_AON_S0

R7613
10KR2J-3-GP

[73] GPU_PEX_RST#

OPS

R7645
10KR2J-3-GP

VGA_CORE IC not support ALERT#.

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

Q7602
2N7002KDW-GP

OPS

OPS

F12

C9
C8

I2CB_SCL
I2CB_SDA

3
4

NC
NC

DY

I2CB_SCL
I2CB_SDA

DY

4
3

GPIO1
GPIO2
GPIO3
GPIO4
(3V3_MAIN_EN) GPIO5
(GPU_EVENT#/FB_CLAMP_TGL_REQ#) GPIO6
GK208
GPIO7
OVERT
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

RN7602
SRN10KJ-5-GP

1
2

OPS

GK208

GF117

GPIO16
GPIO20
GPIO8

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4

GC6_FB_EN_GPU

Q7601_G

NC
NC
NC

GPIO16
GPIO20
GPIO21

3V3_AON_S0

R7636

GPIO5_GC6_PWR_EN

0R2J-2-GP

VGA_CORE_VID

PWR_LEVEL

VGA_CORE_PSI

3V3_AON_S0

GC6_20

GPU_PEX_RST_HOLD_GPU# 1

[82]

AC_PRESENT

[18,24,26]

SML1_CLK

OVER_CURRENT_P8#

OPS
GPU_PEX_RST_HOLD

[73]

2 STRAP_REF0_GND_N9

F6

N15V-GS supports Binary Mode.

N15S-GT supports Multi-Level Strap. F4

F5

Samsung

0x9

K4W4G1646D-BC1A

[24]

1SS400GPT-GP

(RVL-06891-001)N15V-

83.00400.C1F
2ND = 83.27101.01F
3RD = 83.01426.01F

GT -S

DDR3L Recommended Memories

Strap

ROM_SI
ROM_SO
ROM_SCLK

0x9

H5TC2G63FFR-11C

Micron

0xA

MT41K128M16JT-107G:K

Samsung

0xB

K4W2G1646E-BY11

Hynix

0x3

H5TC4G63AFR-11C

0x4

MT41K256M16HA-107G:E

0x5

K4W4G1646D-BC1A

128Mx16 DDR3L

OPS

Hynix
R7610
100KR2J-1-GP

D12 ROM_CS#
B12 ROM_SI
A12 ROM_SO
C12 ROM_SCLK

3V3_AON_S0

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

R7626
10KR2J-3-GP

ROM_CS#

DY

GF117
GK208

256Mx16 DDR3L Micron

R7643
10KR2J-3-GP

NC

MULTI_STRAP_REF0_GND
GF117
GK208

GF119

MULTI_STRAP_REF1_GND

NC

MULTI_STRAP_REF2_GND

NC

PGOOD

GF117
GK208

R7628

NC

STRAP5

BUFRST#

N15S-GT

NC
NC

VMON_IN0
VMON_IN1

GF119

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

D7602

DY

GF117/GF119/GK208

C1

SMBC_THERM_NV

[17,24]

1SS400GPT-GP

GC6_20
2 R7630
0R2J-2-GP

DY

[82]

10/14 MISC2

R7607
40K2R2F-GP

MT41K256M16HA-107G:E

GPIO10_FBVREF
12 OF 14

GPU1L

D1
D2
E4
E3
D3

H5TC4G63AFR-11C

0xD

3D3V_VGA_S0

OPS

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

0x4

Micron

OPS

71.0N14M.B0U

10KR2J-3-GP

N14M-GE-S-A2-GP

E10
F10

2N7002KDW-GP

D7601

DA-05691-001_V05 P15
GPIO20/21 NC : for ALL

GM108

83.00400.C1F
2ND = 83.27101.01F
3RD = 83.01426.01F

R7605
100KR2J-1-GP

OPS

R7631

D5
E6
C4

SMBD_THERM_NV

[83]

GC6_20

GF119

RN7601

Q7601

[18,24,26] SML1_DATA

K4W2G1646E-BY11

OPS SRN4K7J-8-GP

GPIO5_GC6_PWR_EN_GPU

OVERT_GPU#
GPIO9_ALERT
GPIO10_FBVREF

0x5

R7624

3V3_MAIN_EN is an open-drain GPIO.

GPIO5_GC6_PWR_EN_GPU
GPU_EVENT_GPU#

Samsung

0R0402-PAD

(GC6_FB_EN/FB_CLAMP_MON) GPIO0

(DS-06814-001)

GC6_20 10KR2J-3-GP

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

3V3_AON_S0

2 RN7605
1 SRN2K2J-1-GP

AE5
AD6
AE6
AF6
AG4

[24,26,36]

3V3_AON_S0

SRN2K2J-1-GP

MT41K128M16JT-107G:K

3V3_AON_S0

N12P_JTAG_TCK
N12P_JTAG_TMS
N12P_JTAG_TDI
N12P_JTAG_TDO
N12P_JTAG_TRST

1
1
1

3V3_AON_S0

10KR2J-3-GP

R7633
TP7602
TP7605
TP7601

PURE_HW_SHUTDOWN#
C7610
SC2700P50V2KX-1-GP

DY

OPS

2
1

OPS

0R2J-2-GP

R7612
RN7604

3
4

GF119
GK208

GF117

THERMDN
THERMDP

I2CC_SCL
I2CC_SDA

H5TC2G63FFR-11C

0x1

1
2

P2800_VGA_DXP

TP7604

E12

SMBC_THERM_NV
SMBD_THERM_NV

A9
B9

P2800_VGA_DXN

D9
D8

0xC

4
3

I2CC_SCL
I2CC_SDA

Hynix
Micron

256Mx16 DDR3L Hynix

I2CS_SCL
I2CS_SDA

GPIO9_ALERT

8/14 MISC1

TP7603

P_H_S#

STRAP0

C7609
SC2700P50V2KX-1-GP

OPS

R7653
3V3_AON_S0

14 OF 14

GPU1N

STRAP1

OVERT_GPU#

0R2J-2-GP

TP7606

OVERT#

STRAP2

128Mx16 DDR3L

R7652

DY

VIDEO_THERM_OVERT#

STRAP3

D11 BUFRST#

D10

10KR2J-3-GP

OPS

GF119

R7629

GPIO8

NC
GF117
GK208
GF119

Samsung

SYS_PEX_RST_MON_GPU#

CEC

E9

SYS_PEX_RST_MON_GPU#

GC6_20
1

0R2J-2-GP

SYS_PEX_RST_MON#

[73]

GM108

Connect to SYS_PEX_RST_MON#
if GC62.0 is implemented.
Leave NC for GC6 1.0.

N14M-GE-S-A2-GP

71.0N14M.B0U
NPN-06912

NPN-06975

OPS

2
R7649
10KR2J-3-GP

2GC6_FB_EN_GPU

R7648
10KR2J-3-GP

Q7606

GPU_EVENT_GPU#

GC6_20
GPU_EVENT#

2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031

Multi Strap:RAM_CFG[3:0]

STRAP0

1
R7635
DY 10KR2J-3-GP

STRAP3

STRAP2

Samsung/Micron/Micron4Gb/Samsung4Gb
R7625
10KR2J-3-GP

R7646
49K9R2F-L-GP

Hynix/Micron4Gb/Samsung4Gb DY

N15S-GT

R7634
10KR2J-3-GP

R7615
10KR2J-3-GP

Samsung/Hynix/Hynix4Gb/Micron4Gb

3V3_AON_S0

R7606
10KR2J-3-GP

STRAP4
STRAP1

R7621
10KR2J-3-GP

<Core Design>
R7622
10KR2J-3-GP

Hynix/Hynix4Gb

Wistron Corporation

N15V-GM

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

OPS

Micron/Samsung4Gb

R7632
10KR2J-3-GP

R7609
10KR2J-3-GP

R7637
10KR2J-3-GP

Micron/Samsung/Hynix4Gb

R7638
15KR2F-GP

R7639
20KR2F-L-GP

N15S-GT_Micron

2
1
R7642
30K1R2F-L-GP

R7641
24K9R2F-L-GP

N15V-GM-S: Binary Strap for VRAMs.

N15S-GT-S: PH 49.9k ohm on STRAP0.

N15S-GT_Micron4Gb

N15S-GT_Samsung4Gb N15S-GT_Samsung

1
1

R7640
20KR2F-L-GP

R7618
10KR2F-2-GP

N15V-GM

GC6_FB_EN_GPU

SORx_EXPOSED=0000

DY

R7651
4K99R2F-L-GP

R7647
10KR2J-3-GP

N15S-GT

R7620
10KR2F-2-GP

ROM_SI

N15V_GM

ROM_SO

FB_CLAMP_MON_S

ROM_SCLK

1
6

DY

DY

3D3V_VGA_S0

DY

N15S-GT_Hynix

DY

R7650
10KR2J-3-GP

84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.F3F

N15S-GT_Hynix4Gb

10KR2J-3-GP

Q7603
2N7002KDW-GP

R7614
10KR2F-2-GP

DY

N15V_GM

R7611
4K99R2F-L-GP

R7644
3D3V_S0

Reserved for GC6 1.0 (N14P-GV2)

3D3V_VGA_S0

R7619
10KR2F-2-GP

3V3_AON_S0

GC6_20

DY

1
R7608
10KR2F-2-GP

R7627
10KR2J-3-GP

GC6_FB_EN

[20]

0R2J-2-GP

1
R7616
4K99R2F-L-GP

GC6_FB_EN

N15S-GT

GC6_FB_EN

3V3_AON_S0

GC6_20

[20,24,75,83]

GC6_20

R7623

3D3V_S0

3V3_AON_S0

Title

GPU_POWER(4/5)

No VBIOS ROM
Size
Custom
Date:
5

Document Number

Rev

Janus HSW 40/50/70

Monday, February 10, 2014

1

Sheet

76

of

A00
104

6 OF 14

GPU1F
13/14 GND

VGA_CORE

Under GPU

GPU1E

5 OF 14

11/14 NVVDD

C7701

C7719

C7720

SC4D7U6D3V3KX-GP
2

OPS

SC4D7U6D3V3KX-GP
2

SC4D7U6D3V3KX-GP
2

OPS

OPS

OPS

OPS

OPS

SC4D7U6D3V3KX-GP
2

OPS

SC4D7U6D3V3KX-GP
2

DY

SC4D7U6D3V3KX-GP
2

OPS

SC4D7U6D3V3KX-GP
2

OPS

C7711
SCD1U16V2KX-3GP

C7712
SCD1U16V2KX-3GP

C7713
SCD1U16V2KX-3GP

C7714
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
2

OPS

C7721

C7725

C7709

C7702

OPS

SC4D7U6D3V3KX-GP
2

OPS

SC4D7U6D3V3KX-GP
2

DY

C7723

C7708

C7722
D

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N14M-GE-S-A2-GP

71.0N14M.B0U
OPS

Near GPU

C7710

OPS

SC47U6D3V5MX-1-GP
2
1

C7717

OPS

SC22U6D3V5MX-2GP
2
1

C7724

OPS

SC4D7U6D3V3KX-GP
2

C7726

OPS

C7730

SC4D7U6D3V3KX-GP
2

DY

SC4D7U6D3V3KX-GP
2

C7731

OPS

SC4D7U6D3V3KX-GP
2

C7732

DY

SC10U6D3V3MX-GP

ST330U2VDM-4-GP
2
1

C7733

OPS

A2
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
A26
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AB11
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
AB14
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

GND
GND

AA7
AB7

N14M-GE-S-A2-GP

71.0N14M.B0U
OPS

G10,G12:
If GC62.0 is implemented, connect to a 3V3 rail that will be on in GC6.
If GC62.0 is NOT implemented, connect to the same rail as VDD33.

3V3_AON_S0
GPU1C

3 OF 14

14/14 XVDD/VDD33

3D3V_VGA_S0

V1
V2

3.3V +/- 5%
85mA

NC#G1
NC#G2
NC#G3
NC#G4
NC#G5
NC#G6
NC#G7

OPS

C7728

OPS

OPS

OPS

C7727

C7729

C7703

OPS

SC4D7U6D3V3KX-GP
2

* nc on substrate

C7734

SC1U10V2KX-1GP

NC#V5
NC#V6

POWER CHANNELS

Near GPU

3V3AUX

CONFIGURABLE

G1
G2
G3
G4
G5
G6
G7

Under GPU

SCD1U16V2KX-3GP
2
1

V5
V6

G10
G12
G8
G9

SCD1U16V2KX-3GP
2
1

F11

NC#AD10(GM108:3V3_AON) VDD33
NC#AD7 (GM108:3V3_AON) VDD33
NC#B19 FBA_CMD32
VDD33
VDD33

SCD1U16V2KX-3GP
2
1

AD10
AD7
B19

NC#V1
NC#V2

<Core Design>

W1
W2
W3
W4

NC#W1
NC#W2
NC#W3
NC#W4

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

N14M-GE-S-A2-GP

Title

71.0N14M.B0U

Size
Custom

OPS
5

Date:
4

GPU_DPPWR/GND(5/5)

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

77

of

Rev

A00
104

FBA_CLK0P
FBA_CLK0N

J7
K7

CK
CK#

[75]

FBA_CMD3

FBA_CMD3

K9

CKE

L3
K3
J3

WE#
CAS#
RAS#

[75,79] FBA_CMD13
[75,79] FBA_CMD15
[75,79] FBA_CMD30

1
2

1
2

1
2

1
2

1
2

1
2
1
2

1
2

1
2

1
2

1
2

1
2

2
1

1
2
1
2

OPS

OPS

C7834 SCD1U16V2KX-3GP

OPS

C7835 SCD1U16V2KX-3GP

OPS

1D35V_VGA_S0

C7833 SCD1U16V2KX-3GP

OPS

C7836 SCD1U16V2KX-3GP

SC10U6D3V3MX-GP
C7815

C7816
SC1U6D3V3KX-2GP

OPS

R7810
162R2F-GP

R7807
1K33R2F-GP

C7803
SC820P50V2KX-1GP

OPS

OPS

C7811
SC1U6D3V3KX-2GP

FBA_VREF_0

FBA_CLK0P

OPS

C7817
SC1U6D3V3KX-2GP

FBCLK Termination place on VRAM side

R7806
1K33R2F-GP

OPS

OPS

OPS

MT41K256M16HA-107G-E-GP

1D35V_VGA_S0

OPS

Place close VRAM1VDDQ ball

MT41K256M16HA-107G-E-GP

Frame Buffer Patition A-Lower Half

OPS

OPS

Change to 10U 0603 for height limit issue.

OPS
B

OPS

FBA_CLK0P
FBA_CLK0N

OPS

[75]
[75]

OPS

LDM
UDM

1D35V_VGA_S0

Change to 10U 0603 for height limit issue.

WE#
CAS#
RAS#

B1
B9
D1
D8
E2
E8
F9
G1
G9

OPS

E7
D3

L3
K3
J3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

BA0
BA1
BA2

OPS

C7821

Place close VRAM1VDDQ ball

CKE

72.41K26.00U

OPS

C7820

K9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

FBA_DQM2
FBA_DQM3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CK
CK#

[75]
[75]

FBA_CMD20 [75,79]
FBA_CMD4 [75,79]

J7
K7

OPS

NC#J1
NC#J9
NC#L1
NC#L9
NC#M7
NC#T3
NC#T7

LDM
UDM

M2
N8
M3

[75,79] FBA_CMD12
[75,79] FBA_CMD27
[75,79] FBA_CMD26

FBA_CMD0 [75]
FBA_CMD5 [75,79]

J1
J9
L1
L9
M7
T3
T7

BA0
BA1
BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

72.41K26.00U

FBA_CMD20 [75,79]
FBA_CMD4 [75,79]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28

FBA_CMD2 [75]

L2
T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]

K1

CS#
RESET#

OPS

J1
J9
L1
L9
M7
T3
T7

ODT

VREFDQ
VREFCA
ZQ

1D35V_VGA_S0

NC#J1
NC#J9
NC#L1
NC#L9
NC#M7
NC#T3
NC#T7

H1
M8
L8

Place close VRAM2 VDD ball

CS#
RESET#

FBA_CMD0 [75]
FBA_CMD5 [75,79]

FBA_EDC3
[75]
FBA_DQS_RN3 [75]

C7830 SCD1U16V2KX-3GP

FBA_CMD2 [75]

L2
T2

C7
B7

C7804

C7831 SCD1U16V2KX-3GP

K1

UDQS
UDQS#

C7827

OPS

C7822
SC1U6D3V3KX-2GP

ODT

FBA_VREF_0
R7809
1 OPS 2FBA_ZQ1
243R2F-2-GP

FBA_EDC2
[75]
FBA_DQS_RN2 [75]

OPS

C7805
SC1U6D3V3KX-2GP

FBA_EDC1 [75]
FBA_DQS_RN1 [75]

LDQS
LDQS#

F3
G3

OPS

SCD1U16V2KX-3GP

Check

C7
B7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

C7829 SCD1U16V2KX-3GP

[75,79] FBA_CMD13
[75,79] FBA_CMD15
[75,79] FBA_CMD30

UDQS
UDQS#

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_D21
FBA_D17
FBA_D20
FBA_D16
FBA_D22
FBA_D19
FBA_D23
FBA_D18
FBA_D30
FBA_D25
FBA_D31
FBA_D26
FBA_D29
FBA_D24
FBA_D28
FBA_D27

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

C7832 SCD1U16V2KX-3GP

FBA_CMD3

FBA_EDC0 [75]
FBA_DQS_RN0 [75]

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1D35V_VGA_S0

[75]

SC10U6D3V3MX-GP
C7813

FBA_CMD3

F3
G3

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBA_D[0..31]

C7814
SC1U6D3V3KX-2GP

E7
D3

FBA_DQM0
FBA_DQM1

LDQS
LDQS#

1D35V_VGA_S0

VRAM2

C7810
SC1U6D3V3KX-2GP

M2
N8
M3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

1D35V_VGA_S0

C7812
SC1U6D3V3KX-2GP

[75,79] FBA_CMD12
[75,79] FBA_CMD27
[75,79] FBA_CMD26

FBA_CLK0P
FBA_CLK0N
[75]

VREFDQ
VREFCA
ZQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7

[75]
[75]
[75]
[75]

H1
M8
L8

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28

[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]
[75,79]

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

SCD1U16V2KX-3GP

FBA_VREF_0
R7808
1 OPS 2 FBA_ZQ0
243R2F-2-GP

A1
A8
C1
C9
D2
E9
F1
H2
H9

Place close VRAM1 VDD ball

[75]

FBA_D0
FBA_D4
FBA_D2
FBA_D7
FBA_D1
FBA_D5
FBA_D3
FBA_D6
FBA_D10
FBA_D13
FBA_D8
FBA_D12
FBA_D11
FBA_D15
FBA_D9
FBA_D14

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

SCD1U16V2KX-3GP

1D35V_VGA_S0

FBA_D[0..31]

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SCD1U16V2KX-3GP

VRAM1

B2
D9
G7
K2
K8
N1
N9
R1
R9

1D35V_VGA_S0

OPS
FBA_CLK0N

Layout Note: Place in the end.

FBVREF Termination
<Core Design>
A

Type

FBVREF%

Voltage

GPU_GPIO10

Un-termination

50%

0.749V

High

Termination

70%

1.0617V

Low

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

20110613

Size
A3
Date:

GPU-VRAM1,2 (1/4)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

78

of

A00
104

FBA_CMD19

FBA_CMD19

[75,78] FBA_CMD13
[75,78] FBA_CMD15
[75,78] FBA_CMD30

E7
D3

LDM
UDM

J7
K7

CK
CK#

K9

CKE

L3
K3
J3

WE#
CAS#
RAS#

OPS

[75] FBA_DQM5
[75] FBA_DQM6

LDM
UDM

FBA_CLK1P
FBA_CLK1N

FBA_CLK1P
FBA_CLK1N

J7
K7

CK
CK#

[75]

FBA_CMD19

FBA_CMD19

K9

CKE

L3
K3
J3

WE#
CAS#
RAS#

1
2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

1
2

1
2

1
2

OPS

1D35V_VGA_S0

OPS
1

DY

OPS

OPS

OPS OPS

OPS

OPS

OPS

E7
D3

OPS

Place close VRAM3 VDDQ ball

BA0
BA1
BA2

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

72.41K26.00U

[75]
[75]

[75,78] FBA_CMD13
[75,78] FBA_CMD15
[75,78] FBA_CMD30

FBA_CMD20 [75,78]
FBA_CMD4 [75,78]

M2
N8
M3

NC#J1
NC#J9
NC#L1
NC#L9
NC#M7
NC#T3
NC#T7

B1
B9
D1
D8
E2
E8
F9
G1
G9

[75,78] FBA_CMD12
[75,78] FBA_CMD27
[75,78] FBA_CMD26

FBA_CMD16 [75]
FBA_CMD5 [75,78]

J1
J9
L1
L9
M7
T3
T7

BA0
BA1
BA2

L2
T2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

72.41K26.00U

FBA_CMD20 [75,78]
FBA_CMD4 [75,78]

ODT
CS#
RESET#

OPS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

FBA_CMD18 [75]

C7925 SCD1U16V2KX-3GP

[75]

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7

FBA_EDC6
[75]
FBA_DQS_RN6 [75]

K1

1D35V_VGA_S0

C7911
SC1U6D3V3KX-2GP

FBA_CLK1P
FBA_CLK1N

NC#J1
NC#J9
NC#L1
NC#L9
NC#M7
NC#T3
NC#T7

J1
J9
L1
L9
M7
T3
T7

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28

[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]

UDQS
UDQS#

C7906
SC1U6D3V3KX-2GP

[75]
[75]

FBA_CMD16 [75]
FBA_CMD5 [75,78]

VREFDQ
VREFCA
ZQ

Place close VRAM4 VDD ball

C7923 SCD1U16V2KX-3GP

[75] FBA_DQM4
[75] FBA_DQM7

L2
T2

H1
M8
L8

C7
B7

DY

C7912 SCD1U16V2KX-3GP

M2
N8
M3

CS#
RESET#

FBA_VREF_1
R7913
1 OPS 2FBA_ZQ3
243R2F-2-GP

FBA_EDC5
[75]
FBA_DQS_RN5 [75]

C7922 SCD1U16V2KX-3GP

[75,78] FBA_CMD12
[75,78] FBA_CMD27
[75,78] FBA_CMD26

ODT

FBA_CMD18 [75]

F3
G3

C7921 SCD1U16V2KX-3GP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

FBA_EDC7
[75]
FBA_DQS_RN7 [75]

K1

LDQS
LDQS#

OPS

C7918
SC10U10V5KX-2GP

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7

UDQS
UDQS#

C7
B7

FBA_EDC4
[75]
FBA_DQS_RN4 [75]

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1D35V_VGA_S0

OPS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

C7919
SC1U6D3V3KX-2GP

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28

F3
G3

A1
A8
C1
C9
D2
E9
F1
H2
H9

Place close VRAM3 VDD ball

[75]

C7915
SC1U6D3V3KX-2GP

VREFDQ
VREFCA
ZQ

LDQS
LDQS#

1D35V_VGA_S0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

FBA_D[32..63]
FBA_D41
FBA_D45
FBA_D43
FBA_D47
FBA_D40
FBA_D46
FBA_D42
FBA_D44
FBA_D49
FBA_D53
FBA_D51
FBA_D54
FBA_D50
FBA_D55
FBA_D48
FBA_D52

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

C7916
SC1U6D3V3KX-2GP

H1
M8
L8

[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]
[75,78]

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VRAM4

B2
D9
G7
K2
K8
N1
N9
R1
R9

C7913 SCD1U16V2KX-3GP

FBA_VREF_1
R7912
1 OPS 2FBA_ZQ2
243R2F-2-GP

A1
A8
C1
C9
D2
E9
F1
H2
H9

1D35V_VGA_S0

[75]

C7909 SCD1U16V2KX-3GP

1D35V_VGA_S0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

FBA_D[32..63]
FBA_D32
FBA_D39
FBA_D35
FBA_D36
FBA_D34
FBA_D38
FBA_D33
FBA_D37
FBA_D58
FBA_D61
FBA_D56
FBA_D63
FBA_D57
FBA_D62
FBA_D59
FBA_D60

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

C7910 SCD1U16V2KX-3GP

VRAM3

B2
D9
G7
K2
K8
N1
N9
R1
R9

1D35V_VGA_S0

Place close VRAM4 VDDQ ball

1D35V_VGA_S0

MT41K256M16HA-107G-E-GP

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

R7914
162R2F-GP

1
2

1
2

OPS

C7927 SCD1U16V2KX-3GP

OPS

C7930 SCD1U16V2KX-3GP

OPS

C7928 SCD1U16V2KX-3GP

C7920
SC10U10V5KX-2GP

OPS

DY

FBA_CLK1P

R7904
1K33R2F-GP

C7902
SC820P50V2KX-1GP

OPS

R7903
1K33R2F-GP

OPS
FBA_VREF_1

C7924
SC1U6D3V3KX-2GP

FBCLK Termination place on VRAM side

1D35V_VGA_S0

OPS OPS

C7926
SC1U6D3V3KX-2GP

Frame Buffer Patition A-Lower Half

OPS

C7917
SC1U6D3V3KX-2GP

OPS

C7929 SCD1U16V2KX-3GP

MT41K256M16HA-107G-E-GP

OPS
FBA_CLK1N

Layout Note: Place in the end.

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

GPU-VRAM3,4 (2/4)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

79

of

A00
104

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

GPU-VRAM5,6 (3/4)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

80

of

A00
104

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

GPU-VRAM7,8 (4/4)

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

81

of

A00
104

PG8207
2

VSNS

GND

RGND

12

PWR_VGA_CORE_VSNS

10

PWR_VGA_CORE_RGND

2
1

1
2

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
2

2
1
2

2
1

PC8221

OPS

N15-S-GT-S
Config B

N15V-GM-S
Config D

value

R1 (PR8222)

27K
64.27025.6DL

R2 (PR8206)

7.5K
64.75015.6DL

20K
64.20025.6DL

20K
64.20025.6DL
0
2K
63.R0034.1DL
64.20015.6DL
7.87K
18K
R4+R5 (PR8209) 64.78715.6DL 64.18025.6DL
R3 (PR8208)

C (PC8223)

2.7nF
78.27224.2FL

5.6nF
78.56222.2FL

OPS
1

1
2

OPS

1
2

PR8221

PC8222
SC47P50V2JN-3GP

VGACORE_VDD_SENSE_1

[73]

VGACORE_GND_SENSE_1

[73]

0R0402-PAD

DY
PR8220

1
PC8217
SC47P50V2JN-3GP

2
0R0402-PAD

13KR2F-GP

DY

PC8219
SC47P50V2JN-3GP

PC8225

Check

OPS
1

PWR_VGA_CORE_EN

2
1KR2J-1-GP
SCD1U25V2KX-GP

DY

VGA_CORE

PR8256

PR8260

OPS

DY

1
2
1

DY

PR8212
100R2F-L1-GP-U

PWR_VGA_SNUB2
PC8218
SC330P50V2KX-3GP

PR8259
10KR2J-3-GP

DY

3D3V_VGA_S0

DY
1

PT8208
PR8215
2D2R5F-2-GP

3
2
1

84.SRA12.037
OPS(65BOM VGA)
S
S
S

0R0402-PAD
PC8226

PU8209

OPS

VGA_CORE

PWR_VGA_CORE_PSI

PC8204
SCD01U50V2KX-1GP

OPS

S
S
S

SIRA12DP-T1-GE3-GP

84.SRA12.037
OPS(65BOM VGA)
G

PWR_VGA_CORE_RGND

PU8207

PR8258
10KR2J-3-GP

[15,83] DGPU_PWR_EN

PC8224

SE330U2D5VM-14-GP

74.08812.073

[76] VGA_CORE_PSI

OPS

PL8202 OPS
1
2

3V3_AON_S0

OPS

PR8257

OPS(65BOM VGA)

D
D
D
D

RT8812AGQW-GP

PWR_VGA_CORE_RGND

84.A14DP.037

PC8215

IND-D33UH-7-GP

SC5600P25V2KX-1GP

DY

5
6
7
8

1
5
6
7
8

DY
4

5
6
7
8

21

PC8205
SC1KP50V2KX-1GP

DY

OPS

SC4D7U25V5KX-GP

PWR_VGA_CORE_LGATE2

5
6
7
8

5
6
7
8

PWR_VGA_CORE_PHASE2

17

SS

16

SC4D7U25V5KX-GP

LGATE2

3
2
1

PHASE2

REFADJ

S
S
S

11

REFIN

PU8208

PWR_VGA_CORE_SS

OPS

N15V_GM_S
Config D

Component

PC8213

OPS

PU8206

2PWR_VGA_CORE_BOOT2_1 1
2
OPS
0R3J-0-U-GP
PC8216
SCD1U50V3KX-GP

D
D
D
D

PWR_VGA_CORE_BOOT2 1

D
D
D
D

PWR_VGA_CORE_UGATE2

15

S
S
S

PR8222
27KR2F-L-GP

BOOT2

PWR_VGA_CORE_RGND

OPS

14

SIRA14DP-T1-GE3-GP

PWR_VGA_CORE_REFADJ

VREF

SCD1U25V2KX-GP

PR8209
7K87R2F-GP

UGATE2

PR8211

OPS PC8223

VID

PC8212

2
0R2J-2-GP

R4+R5

OPS should be in DUMMY column.

SIRA14DP-T1-GE3-GP

R1
OPS

PR8208

OPS

PWR_VGA_CORE_VREF
PWR_VGA_CORE_REFIN

R3
1

PWR_VGA_CORE_VID

PT8207

PWR_DCBATOUT_VGA_CORE2

OPS OCP setting (current limit ~ 61.5A)

SIRA12DP-T1-GE3-GP

SC1KP50V2KX-1GP

OPS

REFIN_VREF

8K06R2F-GP

2 SCD1U16V2KX-3GP

PR8206
7K5R2F-1-GP

PR8224

SCD1U25V2KX-GP

DY2

D
D
D
D

R2

LGATE1

OPS

Design Current=33.5A
56.65A <OCP< 66.7A

SC10U25V5KX-GP

DY

PSI

OPS

SIRA12DP-T1-GE3-GP

PWR_VGA_CORE_LGATE1

3
2
1

PWR_VGA_CORE_PHASE1

19

5
6
7
8

20

SC10U25V5KX-GP

PC8201
PWR_VGA_CORE_RGND

PHASE1

2
0R0402-PAD

PC8203 1
C

EN

PWR_VGA_SNUB1

DYPC8206
SC330P50V2KX-3GP

5
6
7
8

2PWR_VGA_CORE_BOOT1_1 1
2
OPS
0R3J-0-U-GP
PC8211
SCD1U50V3KX-GP

3
2
1

PWR_VGA_CORE_BOOT1 1

3
2
1

3
2
1

PWR_VGA_CORE_PSI
PR8207
1

[76] VGA_CORE_VID

SIRA12DP-T1-GE3-GP

BOOT1

PWR_VGA_CORE_UGATE2

PWR_VGA_CORE_EN

3
2
1

3
2
1
1
2

DGPU_PWROK

PWR_VGA_CORE_UGATE1

5
6
7
8

1
2
18
PVCC
PGOOD

OPS

SE330U2D5VM-14-GP

13

100KR2J-1-GP
[15,24,83]

PT8206
SE330U2D5VM-14-GP

PWR_VGA_CORE_UGATE1

PR8210
2

SIRA14DP-T1-GE3-GP

UGATE1

S
S
S

TON

OPS

IND-D33UH-7-GP

PR8216
DY 2D2R5F-2-GP 68.R3310.201

84.SRA12.037
OPS(65BOM VGA)
G

S
S
S

OPS

2 PWR_VGA_CORE_TON
499KR2F-1-GP

PU8205

84.SRA12.037
OPS(65BOM VGA)
G

3V3_AON_S0

PR8203

OPS

VGA_CORE

SCD1U50V3KX-GP
PU8203

OPS

PC8220

PL8201 OPS
1
2

D
D
D
D

PR8201

OPS

2
2D2R2F-GP

S
S
S

PR8202

OPS

PC8207

D
D
D
D

PU8201

OPS(65BOM VGA)
G

2PWR_VGA_CORE_TON_1

D
D
D
D

OPS

SCD1U25V2KX-GP

DCBATOUT

S
S
S

RT8812_PVCC

GAP-CLOSE-PWR

DY

OPS

PC8202

OPS

SIRA14DP-T1-GE3-GP

D
D
D
D

PR8223
2D2R3J-2-GP

84.A14DP.037

PC8214

GAP-CLOSE-PWR
PG8212
1
2

5V_S0

PC8210

GAP-CLOSE-PWR
PG8206
1
2

OPS

GAP-CLOSE-PWR
PG8211
1
2

PC8209

OPS

PU8204

GAP-CLOSE-PWR
PG8205
1
2

PC8208
PU8202

GAP-CLOSE-PWR
PG8210
1
2

GAP-CLOSE-PWR
PG8204
1
2

PWR_DCBATOUT_VGA_CORE1

GAP-CLOSE-PWR
PG8209
1
2

SCD1U25V2KX-GP

GAP-CLOSE-PWR
PG8203
1
2

PU8203, PU8205, PU8207 and PU8209 manually change to 84.SRA12.037

SC10U25V5KX-GP

GAP-CLOSE-PWR
PG8208
1
2

SC10U25V5KX-GP

GAP-CLOSE-PWR
PG8202
1
2

GAP-CLOSE-PWR

PWR_DCBATOUT_VGA_CORE1

DCBATOUT

PG8201
2

PWR_DCBATOUT_VGA_CORE2

DCBATOUT

DY

PR8213
100R2F-L1-GP-U
2

For tuning VGA_CORE sequence.

OPS

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL
H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037
L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

RT8812_VGACORE

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

82

of

104

3D3V_VGA_S0
1D05V_VGA_S0
3D3V_VGA_S0 should ramp-up before VGA_Core
VGA_Core should ramp-up before 1D5V_VGA_S0
1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0
3D3V_VGA_S0

1
2
1
2

4
3

PQ8307
2N7002K-2-GP

S G D

84.2N702.J31

OPS
1D05V_VGA_S0_DISCHG

[15,82] DGPU_PWR_EN

1
2

OPS

GPIO5_GC6_PWR_EN# 2

2
GC6_20

GC6_20

C8301
SCD01U50V2KX-1GP

GPIO5_GC6_PWR_EN_R#

0R2J-2-GP

1
SCD1U16V2KX-3GP
2

R8303

Q8301

[76] GPIO5_GC6_PWR_EN

0R2J-2-GP

GC6_20

R8302

GC6_20 10KR2J-3-GP

DY

OPS

VGA_CORE_DISCHG
10R2J-2-GP
PR8316

DGPU_PWR_EN#

3V3_AON_S0
R8315

DY

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

OPS

GC6_20

D G S

PQ8305
2N7002KDW-GP

GAP-CLOSE-PWR
C8310
C8306

OPS

DGPU_PWR_EN#

DMP2130L-7-GP

C8311

3V3_MAIN_EN is an open-drain GPIO.

OPS2

PR8313
100KR2J-1-GP

PG8315
1
2

3D3V_VGA_S0

Q8302

Cold Boot/Optimus: 3V3_AON&3V3_MAIN==>NVDD&PEX_1.05V==>FBVDD/Q

GC6 2.0 Exit: 3.3V_MAIN==>NVDD&PEX1.05V

3D3V_S0
C

GAP-CLOSE-PWR

OPS

SCD1U16V2KX-3GP
2

074.05016.0093

1
2

C8304

DY

C8308

C8307

SC10U10V5KX-2GP

SC1U10V2KX-1GP

DY

SC1U10V2KX-1GP

C8302

DY

C8316

OPS

PR8317
10R2J-2-GP

1D05V_VGA_S0

OPS

G5016KD1U-GP

3D3V_AUX_S5

PG8314
1
2

GAP-CLOSE-PWR

GND
GND

11
15

IN2#6
IN2#7
EN2

PG8312
1
2
C8305

3D3V_VGA_OUT1
VTT_CT_3VC_1

GAP-CLOSE-PWR

8
9
10

3V3_AON_S0

SCD1U16V2KX-3GP

OUT2#8
OUT2#9
CT2

OPS

VGA_CORE

PG8313
1
2

1D05V_VGA_OUT2

SC10U10V5KX-2GP

[15,82] DGPU_PWR_EN

VTT_CT_105VC_2

SC2200P50V2KX-2GP

6
7
5

3D3V_S0

DY

IN1#1
IN1#2
EN1

13
14
12

SC470P50V2KX-3GP

1D05V_VGA_EN
C8309
SCD1U16V2KX-3GP

OUT1#13
OUT1#14
CT1

0R2J-2-GP

NON_GC6

VBIAS

1
2
3

5V_S0

1D05V_VGA_EN

GC6_20

R8313

VGA_CORE&1D05V_VGA_S0 Discharge Circuit

1D05V_VGA_S0

U8301
1D05V_S0

PR8301
1KR2J-1-GP

[15,24,82] DGPU_PWROK

3D3V_S0 to 3D3V_VGA_S0
1D05V_S0 to 1D05V_VGA_S0

C8303
SCD1U16V2KX-3GP

DY

3V3_AON_S0

2nd = 84.00102.031
3rd = 84.03413.B31

GC6_20

R8304

2
0R5J-5-GP

NON_GC6

R8301
100KR2J-1-GP DY

3D3V_VGA_S0

84.02130.031

GT: R8303 = 0 ohm (63.R0034.1DL); C8301 = 0.01u (78.10324.2FL)

2N7002K-2-GP

Could also be used for tuning sequence.

AO4468, SO-8
Id=?A, Qg=9~12nC
Rdson=17.4~22m ohm

PC8303
SC10U6D3V3MX-GP

1D35V_VGA_S0

PQ8308

8
7
6
5

D
D
D
D

S
S
S

1
2
3

1D35V_VGA_S0

1.35V +/- 3%.

5.6A

1D35V_S3

1D35V_VGA_S0

G
SIRA06DP-T1-GE3-GP

1D35V_VGA_S0

PC8307
SC10U6D3V3MX-GP

1D35V_VGA_S0

84.SRA06.037
2nd = 84.08057.037

3D3V_AUX_KBC

1D35V_VGA_EN

75.00054.E7D

R8312
0R2J-2-GP

NON_GC6

PR8312
330KR2J-L1-GP

PR8310
100KR2J-1-GP

PQ8306
2N7002K-2-GP

1D35V_VGA_S0

<Core Design>

84.2N702.J31

1D35V_ENABLE

BAT54C-7-F-3-GP

DY

OPS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

GC6_20
[15,24,82] DGPU_PWROK

S G D

D8301

DIS_1D35V_VGA_S0

DCBATOUT

GC6_FB_EN

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F

4th = 83.R2003.V81
[20,24,75,76]

15V_S5

PQ8304
2N7002KDW-GP

3rd = 75.00054.A7D

OPS
10R2J-2-GP
PR8315

D G S
OPS

PR8311
100KR2J-1-GP

2nd = 83.R2003.W81

1D35V_VGA_S0

Discharge Circuit

OPS

750KR2J-GP

1D35V_VGA_S0

1
2
1D35V_VGA_S0

PC8302
SCD01U50V2KX-1GP

PR8314
100KR2J-1-GP

3D3V_AUX_S5

1D35V_ENABLE_RC
R8314
1D35V_VGA_EN#

DY

1D35V_VGA_EN#
1D35V_VGA_EN

Title

[51]

Rev

Janus HSW 40/50/70

Date:
5

DISCRETE VGA POWER

Size
Document Number
Custom

1
2
R8305 GC6_20
1MR2J-1-GP

Monday, February 10, 2014

Sheet
1

83

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

84

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

85

A00
of

104

SSID = Mechanical
H4
HOLE256R115-GP

H3
HOLE335R115-GP

H1
HOLE335R115-GP

H6
HT85BE85R29-U-5-GP

H5
HT85BE85R29-U-5-GP

34.4CK01.001

2nd = 34.4CK01.601

3rd = 34.4CK01.501

3rd = 34.4CK01.501

ZZ.00PAD.D01 ZZ.00PAD.D01
ZZ.00PAD.D01

ZZ.00PAD.D41

SPR4

SPR5
SPRING-63-GP

C1
C2
HOLE197R166-1-GP HOLE197R166-1-GP

34.41V01.001

34.4Y806.001

34.41V01.001

C3
HOLE197R166-1-GP

SPRING-43-GP-U

SPRING-102-GP

SPR3

SPRING-102-GP

SPR2

ZZ.00PAD.D41

ZZ.00PAD.D11

34.15J03.001

2nd = 34.4CK01.601

34.4CK01.001

H2
HOLE335R115-GP

S2
STF237R117H83-1-GP

S1
STF237R117H83-1-GP

ZZ.00PAD.V71 ZZ.00PAD.V71

ZZ.00PAD.V71

SSID = EMI
Mind the voltage rating of the caps.

AUD_AGND

EC9749
SCD1U25V2KX-GP

EC9748

DY
1

DY
2

SCD1U25V2KX-GP

EC9747

DY

SCD1U25V2KX-GP

DY

2
1

EC9742

EC9724

DY
2

EC9732

EC9733

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

UNUSED PARTS/EMI Capacitors

Size
A3

Date:
4

<Core Design>
SC1U10V2KX-1GP

DY
2

EC9734

SC1U10V2KX-1GP

DY
2

EC9738

SC1U10V2KX-1GP

DY

SC1U10V2KX-1GP

EC9736
SC1U10V2KX-1GP

DY

EC9735

DY

SC1U10V2KX-1GP

EC9737
SC1U10V2KX-1GP

DY

5V_S5

3D3V_S0

DY

EC9722

EC9741

DY

SCD1U25V2KX-GP

EC9740

DY

EC9745

EC9743

EC9744

DY

1
2

1
2

1
2

1
2

EC9739

1
2

SCD1U25V2KX-GP
2

1
2

1
2

1
2

1
2

DY

EC9731

DY

DCBATOUT

SC1U10V2KX-1GP

EC9721

1
2

1
2

1
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

SCD1U25V2KX-GP
2

DY

SC1U10V2KX-1GP

DY

SC1U10V2KX-1GP

EC9723
SC1U10V2KX-1GP

DY

EC9729

DY

SCD1U25V2KX-GP

EC9718
SC1U10V2KX-1GP

DY

EC9728

DY

SCD1U25V2KX-GP

EC9719
SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

EC9730

DY

SCD1U25V2KX-GP

DY

SC1KP50V2KX-1GP

EC9720

EC9726

DY

EC9714

EC9715

5V_S0

DY

EC9725

DY

SC1KP50V2KX-1GP

SCD1U25V2KX-GP
2

EC9727

SC1KP50V2KX-1GP

DY

SC1U10V2KX-1GP

DY

EC9710

DY

SC1U10V2KX-1GP

EC9716

EC9709

DY

SC1U10V2KX-1GP

DY

EC9707

SC1U10V2KX-1GP

EC9713

EC9706

SC1KP50V2KX-1GP

DY

EC9705

SC1U10V2KX-1GP

DY

SC1U10V2KX-1GP

EC9712

SC1KP50V2KX-1GP

DY

DY

SC1U10V2KX-1GP

EC9711

EC9717

EC9708

EC9704

SC1KP50V2KX-1GP

DY

SC1KP50V2KX-1GP

EC9703

SC1KP50V2KX-1GP

DY

EC9702

EC9701

1D35V_VGA_S0

DCBATOUT

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

86

Rev

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

87

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

88

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

(Reserved)Finger Print

Size
A4

Document Number

Date: Friday, February 07, 2014

5

Rev

Janus HSW 40/50/70

2

Sheet

89

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Free Fall Sensor

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

90

Rev

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

91

A00
of

104

(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Reserved

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

92

A00
of

104

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Express Card

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

93

A00
of

104

(Blanking)

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

LVDS_Switch

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

Rev

A00
94

of

104

(Blanking)

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CRT_Switch

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
1

95

A00
of

104

SSID = XDP

CPU XDP

[6]

CFG[19:0]

[4] XDP_BPM[7:0]
[4]
[4]
[4]
[4]
[4]
[4]

[7] H_VCCST_PWRGD
[17,24] PM_PWRBTN#
C

[7] PWR_DEBUG
[17,24] SYS_PWROK

R9601 1
R9603 1
R9604 1
R9605 1

[12,18,62] PCH_SMBDATA
[12,18,62] PCH_SMBCLK
[4]

DY
DY
DY
DY1

XDP_TCLK

[18] PCIE_CLK_XDP_P
[18] PCIE_CLK_XDP_N

1
1

TP9648 TPAD14-OP-GP
TP9645 TPAD14-OP-GP

2 0R2J-2-GP
2 0R2J-2-GP
RN9601
4
2
DY 3

XDP_PWR_DEBUG
XDP_SYS_PWROK

1
1

TP9647 TPAD14-OP-GP
TP9644 TPAD14-OP-GP

XDP_SMBDAT
XDP_SMBCLK

1
1

TP9646 TPAD14-OP-GP
TP9649 TPAD14-OP-GP

SRN0J-6-GP

XDP_TCLK

TP9650 TPAD14-OP-GP

PCIE_CLK_XDP_P
PCIE_CLK_XDP_N
0R2J-2-GP 2

DY

XDP_RST
1 R9602
XDP_DBRESET#

C9602

1
1

TP9652 TPAD14-OP-GP
TP9651 TPAD14-OP-GP

1
1

TP9654 TPAD14-OP-GP
TP9653 TPAD14-OP-GP

DY

XDP_PRDY#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

VCCST_PWRGD_XDP
BP_PWRGD_RST#

2 1KR2J-1-GP
2 0R2J-2-GP

SCD1U16V2KX-3GP
2
1

[17,24,30,36,52,58,65,73] PLT_RST#
[17] XDP_DBRESET#

XDP_PREQ#

CFG[19:0]
XDP_BPM[7:0]
XDP_PREQ#

TP9601 TPAD14-OP-GP

XDP_PRDY#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

1
1
1
1
1

TP9602
TP9624
TP9621
TP9623
TP9611

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7

1
1
1
1
1
1
1
1

TP9612
TP9613
TP9614
TP9615
TP9616
TP9617
TP9618
TP9619

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

TP9626
TP9627
TP9620
TP9622
TP9630
TP9631
TP9629
TP9628
TP9634
TP9635
TP9633
TP9632
TP9637
TP9639
TP9638
TP9636
TP9640
TP9643
TP9642
TP9641

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU/PCH XDP

Size
A4

Document Number

Date:
5

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014
Sheet
96
2

of
1

104

Shark Bay Platform Power Sequence

(DC mode)

Red Words: Controlled by EC GPIO

+RTC_VCC

t01 >9ms

RTC_RST#
DCBATOUT
3D3V_AUX_S5
D

Press Power button

Sense the power button status

Platform to KBC PSL_IN2

KBC_PWRBTN#

PSL_OUT#(GPIO71) keep low

3D3V_AUX_KBC

KBC GPIO34 control power on by 3V_5V_EN

S5_ENABLE
5V_S5
V5REF_Sus must be powered up before
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.

5V_S5 & 3D3V_S5 need meet 0.7V difference

3D3V_S5

5V_S5 & 3D3V_S5 need meet 0.7V difference

+5VA_PCH_VCC5REFSUS

Ta

KBC GPIO43 to PCH

PM_RSMRST#(RSMRST#_RST)
In case of a non-Deep S4/S5 Platform
timing t42 should be added to t07
which will make it 100mS minimum.

t05 >10ms

t07 >100ms

PCH to KBC GPIO00

PCH_SUSCLK_KBC

KBC GPIO20 to PCH

PM_PWRBTN#

DC PM_PWRBTN#

After Power Button

PCH to KBC GPIO44

PM_SLP_S4#

t10

PM_SLP_S3#

PCH to KBC GPIO01

>30us

KBC GPIO47 to LAN

PM_LAN_ENABLE

Enable by PM_SLP_S4#

1D5V_S3
C

DDR_VREF_S3(0.75V)

5V_S0 & 3D3V_S0 need meet 0.7V difference

5V_S0
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V.

3D3V_S0
+5VS_PCH_VCC5REF

Tb

1D5V_S0
1D8V_S0
0D75V_S0

1D8V_S0 & 1D5V_S3 power ready

RUNPWROK
1D05V_PCH
VCCP_CPU
1D05_VTT_PWRGD
0D85V_S0

0D85V_S0
D85V_PWRGD
SetVID

CPU SVID BUS

ACK

50us< t36 <2000us

VCC_CORE
VCC_GFXCORE

t37
<5ms

IMVP_PWRGD
B

PCH_CLOCK_OUT
This signal represents the Power
Good for all the non-CORE and
non-graphics power rails.

ALL_SYS_PWRGD=D85V_PWRGD

t14 >99ms

PWROK(S0_PWR_GOOD)

KBC GPIO77 to PCH

t18

D85V_PWRGD

>0us

PCH to CPU

2ms<t17 <650ms

DRAMPWROK(VDDPWRGOOD)

t19 >1ms
1D8V_S0

t20 >2ms
5ms<t13 <650ms

PCH to CPU

UNCOREPWRGOOD(H_CPUPWRGD)

t21+t22 >1ms+60us

SYS_PWROK
1ms<
PLT_RST#

t25 <100ms

PCH to all system

t39 <200us

DMI

N14P-GT Power-Up/Down Sequence

3D3V_S0

PCH GPIO54 output

DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
A

8209A_EN/DEM_VGA(Discrete only)

VGA_CORE(NVVDD)

tNVVDD >0ms

RT8208 PGOOD

DGPU_PWROK(Discrete only)
1D5V_VGA_S0(FBVDDQ)

tNV-FBVDDQ

1D05V_VGA_S0(PEX_VDD)

>0ms
tNV-PEX_VDD >0ms

VGA_CORE,1D05V_VGA_S0
1D5V_VGA_S0,3D3V_VGA_S0

First rail to power down

<Core Design>

Wistron Corporation

Last rail to power down

tPOWER-OFF

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

<10ms
Title
Size
A1

For power-down, reversing the ramp-up sequence is recommended.

Date:
5

Power Sequence

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014
1

Sheet

A00
97

of

104

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

D

DC
Battery

BT+

SWITCH

PM_SLP_S4#

Page44

Page43

-7

-3
AC
Adapter in
Page42

+DC_IN

DCBATOUT
DCBATOUT

SWITCH
Page44

4a
VIN

AD+
EN1

-5
Charger

DCBATOUT

BQ24715
ACOK

3a

S5_ENABLE

EN2

3D3V_S5

PM_SLP_S3#

TPS51225CRUKR

VIN

DC/DC

Page44

TPS51367

TPS51367
PGOOD

EN

RUNPWROK

RUNPWROK

PGOOD

Page48

Page48

-2

(3.3V/5V)

1D35V_S3

SW

1D05V_S0

SW

EN

VIN

4b
4b

5V_S5

1D35V_S3

Page41

3D3V_AUX_S5
SWITCH

-4

GPIO34

4b

S5_ENABLE
DDR_PG_CTL

VR_EN

KBC
NPCE985

-1

PSL_IN2#
GPIO8

PM_SLP_S3#

GPIO43
GPIO20

GPIO01

DPWROK

RSMRST#_KBC

VIDSOUT

Haswell ULT CPU

with
Lynx Point PCH

RSMRST#

PM_PWRBTN#

PWRBTN#

GPIO80

Level
Shifter

RUNPWROK

H_VR_ENABLE

H_VCCST_PWRGD

Page7
H_CPU_SVIDDAT

3D3V_S5

PLTRST#

S0_PWR_GOOD

10

Page36

12
APWROK

SWITCH

11

Page24

SLP_S3# de-assert, delay 20ms;

PCH_PWROK assert.

3D3V_S0

RUNPWROK

PM_SLP_S4#

-3

PSL_IN1#

KBC_PWRBTN#

Page36

Page46

3D3V_AUX_KBC
AC_IN

SWITCH

0D675V_S0

TPS51206

Page24

-6

5V_S0

RUNPWROK

4
DDR_VTT_PG_CTRL

PCH_PWROK

SLP_S3# de-assert, delay 200ms;

S0_PWR_GOOD assert.

VCCST_PWRGD

SYS_PWROK

4a

PCI_PLTRST#

VIN

VR_READY

PM_SLP_S3#

EN

1D5V_S0

VOUT

TPS51312

RUNPWROK

PGOOD

Page51

5
PCH_PWROK

4b

H_VCCST_PWRGD

SYS_PWROK be asserted after S0_PWR_GOOD

assertion and CPU core VR power good
assertion.

11

S0_PWR_GOOD

H_CPU_SVIDDAT

VDIO

TPS51622

H_VR_ENABLE

VR_ON

IMVP_PWRGD

PGOOD

Page46
PWR_VCC_PWM1

DCBATOUT

CSD97374
VSW

VCC_CORE

Page47

<Core Design>

3a

4a

4b

10

11

12

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:

Power Sequence Diagram

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

98

A00
of

104

DCBATOUT

Adapter

RT8237

TPS51216RUKR

ISL95813

AP3211

Charger
1D05V_S0

BQ24717

1D35V_S3

+PBATT

Battery

TPS22966

TLV70215

1D05V_VGA_S0

1D5V_S0

0D675V_S0

VCC_CORE

VGA_CORE

SIRA06DP

1D35V_VGA_S0

TPS51125ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5

5V_S5

AP2182SG

USB30_VCCA
USB30_VCCB

AP2301M8G

+5V_USB1

3D3V_S5

TPS22966

TPS22966

TLV70215
3D3V_S0

5V_S0

1D5V_S0

AO3403

3D3V_LAN_S5

SY6288

RT9724

ODD_PWR_5V

TPS22966

Power Shape
LCDVDD

3D3V_VGA_S0

Regulator

LDO

Switch

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Power Block Diagram

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

99

Rev

A00
of

104

PCH SMBus Block Diagram

3D3V_S5_PCH

TP_VDD

3D3V_S0

SRN2K2J-1-GP

SRN10KJ-5-GP

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

KBC SMBus Block Diagram

3D3V_S0

PCH_SMBCLK
PCH_SMBDATA

DIMM 1

SRN10KJ-5-GP

TouchPad Conn.

SCL
SDA

SMBus Address:0xA0/0xA1

PSDAT1

TPDATA

PSCLK1

TPCLK

TPDATA

TPDATA

TPCLK

TPCLK

2N7002SPT

3D3V_AUX_KBC

TPAD
PCH_SMBCLK

3D3V_S5_PCH

SCL

PCH_SMBDATA

SDA
SRN4K7J-8-GP

SMBus Address:0x58/0x59

Battery Conn.

SRN33J-7-GP
GPIO17/SCL1

PTN3355

SRN2K2J-1-GP
PCH_SMBCLK

GPIO22/SDA1

VDDA33_DP

PCH_SMBDATA

TMS

SML0CLK SML0_CLK

BAT_SCL
BAT_SDA

PBAT_SMBCLK1

CLK_SMB

PBAT_SMBDAT1

DAT_SMB

(Janus Only)

HPA02224RGRR

SMBus Address:0xC0H/0x40H

SML0DATA SML0_DATA

SMBus address:16

KBC
NPCE285P

SCL
SDA

SMBus address:12

GPIO73/SCL2
GPIO74/SDA2

PCH

3D3V_S0

SMBus Address:
0x94/0x95/0x96/0x97

3D3V_S5_PCH

3D3V_S0

SRN2K2J-8-GP

SML1CLK
SML1DATA

SML1_CLK

SRN2K2J-8-GP

THM_SML1_CLK

SML1_DATA

SCL

THM_SML1_DATA

SMBus Address:0x82/0x83

SDL

Thermal
NCT7718W

SMBus Address:0x98/0x99
2N7002SPT

3D3V_VGA_S0

SRN4K7J-8-GP
3D3V_VGA_S0

dGPU

SMBC_Therm_NV
SMBD_Therm_NV

I2CS_SCL
I2CS_SDA

SMBus Address:0x9E/0x9F

3D3V_S0

5V_S0

0R2J-2-GP

DY

3D3V_S0
SRN2K2J-1-GP

SRN2K2J-1-GP

PCH_HDMI_CLK
PCH_HDMI_DATA

DDPB_CTRLCLK
DDPB_CTRLDATA

DDC_CLK_HDMI

DDC_DATA_HDMI

GPIO47/SCL4A

PROCHOT_EC

GPIO53/SDA4A

LCD_TST_EN

LCD_TST_EN

H_PROCHOT_EC

0R2J-2-GP
LCD_TST

HDMI CONN

2N7002DW-1-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
A

SMBUS Block Diagram

Document Number

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
E

Rev

A00
100

of

104

CLK Block Diagram

Intel CPU
Haswell/Broadwell ULT

D
M_A_DIMA_CLK_DDR0

CK0

DDR3L

DIMM1

CK0#

M_A_DIMA_CLK_DDR#0

M_A_DIMA_CLK_DDR1

CK1
CK1#

M_A_DIMA_CLK_DDR#1

SA_CLK0
SA_CLK#0

SA_CLK1
SA_CLK#1

CLK_PCIE_WLAN_P3

CLKOUT_PCIE_P2
CLKOUT_PCIE_N2

VRAM1

CK
CK#

FBA_CLK0P

VRAM2

CK
CK#

FBA_CLK0N

FBA_CLK0
FBA_CLK0#

PEX_REFCLK#

PEX_REFCLK

REFCLK_P
REFCLK_N

LANXIN
CLK_PCIE_VGA#

CLK_PCIE_VGA

VRAM3

CK
CK#

XTAL_IN

FBA_CLK1N

CK
CK#

FBA_CLK1N

CKXTAL1

X3001
25MHz

CLKOUT_PCIE_P4
CKXTAL2

27MHZ_IN

X7601
27MHz

FBA_CLK1P

VRAM4

CLKOUT_PCIE_N4

LANXOUT
FBA_CLK1P

WLAN
NGFF

LAN
RTL8106E/RTL8111G

CLK_PCIE_LAN_N4

CLKOUT_PCIE_N3

VGA
N15V-GM-S-A2
GB2-64 (23x23)

FBA_CLK0N

REFCLKN0

CLK_PCIE_LAN_P4

CLKOUT_PCIE_P3
FBA_CLK0P

REFCLKP0

CLK_PCIE_WLAN_N3

FBA_CLK1
FBA_CLK1#

XTAL_OUT

27MHZ_OUT

HDA_BCLK/I2S0_SCLK

RN2102

HDA_BITCLK

HDA_CODEC_BITCLK

BITCLK

Audio
Realtek
ALC3223

SRN33J-5-GP-U

RTC_X1

RTCX1
R5815

X1901
32.768KHz

SUSCLK_NGFF

0R2J-2-GP

RTC_X2

NGFF

SUS_CLK

RTCX2

KBC
NPCE285P

XTAL24_IN
XTAL24_IN
SUSCLK/GPIO62

X1801
24MHz

CLKOUT_LPC_1
XTAL24_OUT

CLKOUT_LPC_0

XTAL24_OUT

SUS_CLK_PCH R1710 SUS_CLK

0R2J-2-GP
R1805

CLK_PCI_KBC_R

R2441

R1804

CLK_PCI_LPC

GPIO0/EXTCLK/F_SDIO3
LCLK/GPIOF5

0R2J-2-GP

CLK_PCI_LPC_R

0R2J-2-GP

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P

SUS_CLK_KBC

0R2J-2-GP

CLK_PCI_KBC

LPC

Test Point

A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:

CLK Block Diagram

Document Number

Rev

A00

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet

101

of

104

Thermal Block Diagram

Audio Block Diagram

3D3V_S5_PCH

PCH

3D3V_S0

PAGE28

D+

NCT7718_DXP
SC2200P50V2KX-2GP

SML1_DATA

SML1DATA/GPIO74

2N7002

SML1_CLK

SML1CLK/GPIO75

Thermal
NCT7718

THM_SML1_DATA

SDA

THM_SML1_CLK

SCL

D-

SPKR_L+
SPKR_LSPKR_RSPKR_R+

MMBT3904-3-GP

Place near CPU

PWM CORE

Codec
ALC3223

MMBT3904-3-GP

SML1_CLK

SML1_DATA

T_CRIT#

GPIO4

EN

3V/5V

SLEEVE

PCH_PWROK

RING2
2

PAGE86

SMBD_THERM_NV

I2CS_SCL

SMBC_THERM_NV

I2CS_SDA

2N7002

VGA

GPIO0/DMIC_DATA
GPIO1/DMIC_CLK

DMIC_DATA_R

DMIC_CLK_R

R2714
0R2J-2-GP
R2716

Digital
MIC

DMIC_DATA

DMIC_CLK

0R2J-2-GP

N15V-GM-S-A2
GB2-64 (23x23)

FAN1_DAC_1

FAN_TACH1

GPIO56

PURE_HW_SHUTDOWN#

Put under CPU(T8 HW shutdown)

GPIO73

GPIO94

2N7002

GPIO74

KBC
NPCE285P

THERM_SYS_SHDN#

PAGE27

AUD_HP1_JACK_R

3D3V_S0

HP MIC
COMBO

AUD_HP1_JACK_L

T8

PAGE20

SPEAKER

NCT7718_DXN

TACH

FAN_VCC1

FAN
5V

VIN

VSET

VIN

VOUT

FAN CONTROL

APL5606AKI
PAGE28

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Audio Block Diagram

Size
Document Number
Custom
Date:
A

Friday, February 07, 2014

Sheet
E

102

Rev

A00

Janus HSW 40/50/70

of

104

Change notes DATE

VERSON

DATE

Page

Modify List

OWNER

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Change History

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet
1

103

A00
of

104

5
VERSION DATA

PAGE

Change Iteam

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

Change History

Document Number

Rev

Janus HSW 40/50/70

Friday, February 07, 2014

Sheet

104

A00
of

104