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Project Namel: Gambit MLK SFF


PCB Number: 17530
PCBA Ver.: A00
SCH Ver.: A00
Project Code : 3PD06M010001 Vinafix.com
D PCB Size: 285.7 x 200mm, 1.6mm, 4 Layers D

PAGE TITLE PAGE TITLE Jumper Setting


01 Cover Page 56 HDMI
02 Block Diagram 57 (R) Pin 1-2 With Jumper to ME Disable
03 CPU_DDRA_DDRB 58 VGA_(RTD2166) JMP1 Pin 3-4 Without Jumper to Clear Password
04 CPU_CFG/CLOCK 59 (R)
05 CPU_(PCIE) 60 HDD/ODD Pin 5-6 With Jumper to Clear CMOS
06 CPU_(VSS) 61 (R) DB1 PD 1K PD 1K to GND for Debug, All Power-On
07 CPU_(VCC_CORE/SENCE) 62 NGFF
08 CPU_(DDI/EDP) 63 PCI_SLOT
09 CPU_(POWER CAP) 64 PWR BTM/LED BOM Configuration Power sates
10 CPU_(R) 65 (R)
11 DDR4 CHA DIMM 0 66 (R) (R_): Unmount Name G3 DSW S5 S4 S3 S0
12
13
(R)
DDR4 CHB DIMM 0
67
68
(R)
LPC/UART Port
(X_): Debug +12V V_12P0_A O O O O O
14 (R) 69 (R) (GAM_): Gambit MLK SFF +12V O
15 PCH_(Audio/SMBUS/JTAG/GPIO) 70 (R) (EAG_): Eagle SFF V_12V_CPU_S0 O O O O O
C
16
17
PCH_(CLK)
PCH_(SATA/PCIE/HOST)
71
72
(R)
(R)
(TPM_): With TPM -12V -12V O C

18 PCH_(DMI/USB2/USB3/PCIE) 73 (R) (NONTPM_): Without TPM 5V_S0


USBVCC12
O
19 PCH_(DDI/USB3/GPIO) 74 (R) USBVCC34 O O O O
20 PCH_(UART/GPIO/I2C) 75 (R) +5V USBVCC78
21 PCH_(Strap Pin) 76 (R) 5V_S5
22 PCH_(VCC) 77 (R) V_5_CODEC O O O O O
23 PCH_(VSS/GPIO) 78 (R) 3P3V_S0
24 SIO_(SMSC5533) 79 (R) 3P3V_AUD_S0 O
25 SPI/RTC/BAT 80 (R) 3P3V_SB
26 FAN Control/Thermal sensor 81 (R) 3P3V_SPI
27 AUDIO_(ALC3820) 82 (R) 3.3V 3P3V_LAN O O O O
28 (R) 83 (R) 3P3V_M2VAUX
29 AUDIO JACK 84 (R) 3P3V_PCIVAUX
30 (R) 85 (R) 3P3V_S5 O O O O O
31 LAN_(RTL8111H) 86 (R) 3P0V_BAT_VREG
32 RJ45+USB2.0 87 (R) VBAT1
VBAT O O O O O O
33 Card Reader_(RTS5170) 88 (R) VBAT2
34 (R) 89 (R) +VCCPLL_OC
VDDQ O
35 (R) 90 (R) V_SM
B O O B
36 Rear USB2.0 91 TPM V_SM_VTT
37 (R) 92 (R) DIMM O
V_VPP
38 (R) 93 PCIeX16 V1P0_PCH_SB
39 Front USB3.0 94 PCIeX1 +V1P0A_VCCAPLL
40 (R) 95 (R) +V1P0A_VCCF24_1P0
41 ATX CONNECTOR 96 (R) PCH +V1P0A_VCCAMPHYPLL O O O O
42 (R) 97 (R) V_CPU_ST_PLL
43 3P3V_SB & 5V_S0 Power 98 (R) V_CPU_CORE
44 VCORE/V_GT_(NCP81203) 99 XDP & APS V_CPU_GT
45 VCORE OUTPUT_(NCP81166) 100 (R) V_CPU_IO
CPU O
46 V_GT OUTPUT_(NCP81166) 101 (R) V_CPU_SA
47 VCCSA_(RT8237C) 102 Power Sequence +VCCFUSEPRG
48 VCCIO_(APL5611A) 103 Power Block Diagram
49 5V_S5/3P3V_S5_(RT6575D) 104 Power Good & Reset Diagram
50 DDR_PWR_(RT8231A) 105 Clock Diagram
51 PCH_1D0V_(RT8237C) 106 Reset Flow Chart
52 DDR_2D5V_VPP 107 Change Histroy
53 MINUS 12V_(NCP3063)
A 54 3P3V_S0 Power A

55 Sequence Circuit

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Cover Page
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 1 of 107
5 4 3 2 1
5 4 3 2 1

ATX-6PIN CONN
PCB BOARD SIZE Channel A
285.7 x 200mm PCIE X16 SLOT PCI EXPRESS Gen3 INTEL 64 bit
Coffee Lake-S DDR4 UDIMM *1
4 Layer Vinafix.com (65W 4C + GT2) 2666MHz

D CPU-4PIN CONN D

SKT H4 LGA1151 Channel B


HDMI PORT v1.4 DDI1 64 bit
42.5 mm x 42.5 mm
2666MHz DDR4 UDIMM *1

eDP to VGA eDP(1.4)


D-SUB PORT
Realtek RTD2166
IMVP8
(Vcore 4 Phase + VGT 2 Phase)

DMI
C C

SATA 3.0 Realtek


(Port 0) SATA3.0 PCIE Interface RJ45 Conn.
RTL8111H
INTEL PCH
SATA 2.0 Canonlake
(Port 1) SATA3.0 PCH-H370
PCIE Gen2 Interface PCIE X1 SLOT
SATA 2.0 FCBGA 837PIN
(Port 2) SATA3.0
23 mm x 23 mm
PCIE Interface
Front USB 3.0*2 USB3.0 WLAN NGFF Conn.
USB2.0

Rear USB 2.0*2 USB2.0


(RJ45 USB Conn.) CNVI

Rear USB 2.0*2 USB2.0


(DUAL USB Conn.)
SATA3.0 SSD M.2 E KEY Conn.
B B

Realtek USB2.0 SPI BUS SPI Flash ROM


3 in 1 Card reader
RTS5170 (32MB)

Rear AUDIO Nuvoton TPM


Line - In
Line - Out HDA CODEC
NPCT750 Eagle only
Mic - In Realtek HDA
ALC3820
Front AUDIO
CTIA (Apple) SIO
LPC BUS SMSC SCH5553 CPU FAN CNTL CPU 1X4 FAN
Standard Headset

32.768KHz
32.768KHz
Debug Conn.
A
24MHz A
24MHz

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 2 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

CPU1C 3 OF 12

Lake-S

PEG_RX_CPU_P0 B8 A5 PEG_TX_CPU_P0
[93] PEG_RX_CPU_P0 PEG_RX_CPU_N0 PEG_RXP_0 PEG_TXP_0 PEG_TX_CPU_N0 PEG_TX_CPU_P0 [93]
[93] PEG_RX_CPU_N0 B7 A6 PEG_TX_CPU_N0 [93]
PEG_RXN_0 PEG_TXN_0
PEG_RX_CPU_P1 C7 B4 PEG_TX_CPU_P1
[93] PEG_RX_CPU_P1 PEG_RX_CPU_N1 PEG_RXP_1 PEG_TXP_1 PEG_TX_CPU_N1 PEG_TX_CPU_P1 [93]
[93] PEG_RX_CPU_N1 C6 B5 PEG_TX_CPU_N1 [93]
PEG_RXN_1 PEG_TXN_1
PEG_RX_CPU_P2 D6 C3 PEG_TX_CPU_P2
[93] PEG_RX_CPU_P2 PEG_RX_CPU_N2 PEG_RXP_2 PEG_TXP_2 PEG_TX_CPU_N2 PEG_TX_CPU_P2 [93]
D5 C4
[93] PEG_RX_CPU_N2 PEG_RXN_2 PEG_TXN_2 PEG_TX_CPU_N2 [93]
PEG_RX_CPU_P3 E5 D2 PEG_TX_CPU_P3
[93] PEG_RX_CPU_P3 PEG_RX_CPU_N3 PEG_RXP_3 PEG_TXP_3 PEG_TX_CPU_N3 PEG_TX_CPU_P3 [93]
E4 D3
[93] PEG_RX_CPU_N3 PEG_RXN_3 PEG_TXN_3 PEG_TX_CPU_N3 [93]
PEG_RX_CPU_P4 F6 E1 PEG_TX_CPU_P4
[93]
[93]
PEG_RX_CPU_P4
PEG_RX_CPU_N4
PEG_RX_CPU_N4 F5 PEG_RXP_4
PEG_RXN_4
PEG_TXP_4
PEG_TXN_4
E2 PEG_TX_CPU_N4 PEG_TX_CPU_P4
PEG_TX_CPU_N4
[93]
[93] SKYLAKE SOCKET
PEG_RX_CPU_P5 G5 F2 PEG_TX_CPU_P5
[93] PEG_RX_CPU_P5 PEG_RX_CPU_N5 PEG_RXP_5 PEG_TXP_5 PEG_TX_CPU_N5 PEG_TX_CPU_P5 [93]
[93] PEG_RX_CPU_N5 G4 F3 PEG_TX_CPU_N5 [93] SKT301 SKT302
PEG_RXN_5 PEG_TXN_5
PEG_RX_CPU_P6 H6 G1 PEG_TX_CPU_P6
[93] PEG_RX_CPU_P6 PEG_RX_CPU_N6 PEG_RXP_6 PEG_TXP_6 PEG_TX_CPU_N6 PEG_TX_CPU_P6 [93]
C [93] PEG_RX_CPU_N6 H5 G2 PEG_TX_CPU_N6 [93] C
PEG_RXN_6 PEG_TXN_6
PEG_RX_CPU_P7 J5 H2 PEG_TX_CPU_P7
[93] PEG_RX_CPU_P7 PEG_RX_CPU_N7 PEG_RXP_7 PEG_TXP_7 PEG_TX_CPU_N7 PEG_TX_CPU_P7 [93]
J4 H3
[93] PEG_RX_CPU_N7 PEG_RXN_7 PEG_TXN_7 PEG_TX_CPU_N7 [93]
PEG_RX_CPU_P8 K6 J1 PEG_TX_CPU_P8
[93] PEG_RX_CPU_P8 PEG_RX_CPU_N8 PEG_RXP_8 PEG_TXP_8 PEG_TX_CPU_N8 PEG_TX_CPU_P8 [93]
K5 J2
[93] PEG_RX_CPU_N8 PEG_RXN_8 PEG_TXN_8 PEG_TX_CPU_N8 [93]
PEG_RX_CPU_P9 L5 K2 PEG_TX_CPU_P9
[93] PEG_RX_CPU_P9 PEG_RX_CPU_N9 PEG_RXP_9 PEG_TXP_9 PEG_TX_CPU_N9 PEG_TX_CPU_P9 [93]
L4 K3
[93] PEG_RX_CPU_N9 PEG_RXN_9 PEG_TXN_9 PEG_TX_CPU_N9 [93]
PEG_RX_CPU_P10 M6 L1 PEG_TX_CPU_P10
[93] PEG_RX_CPU_P10 PEG_RX_CPU_N10 PEG_RXP_10 PEG_TXP_10 PEG_TX_CPU_N10 PEG_TX_CPU_P10 [93]
[93] PEG_RX_CPU_N10 M5 L2 PEG_TX_CPU_N10 [93] Load Plate
PEG_RXN_10 PEG_TXN_10 (22.78003.021) Back Plate
PEG_RX_CPU_P11 N5 M2 PEG_TX_CPU_P11 (22.78006.031)
[93] PEG_RX_CPU_P11 PEG_RX_CPU_N11 PEG_RXP_11 PEG_TXP_11 PEG_TX_CPU_N11 PEG_TX_CPU_P11 [93]
[93] PEG_RX_CPU_N11 N4 M3 PEG_TX_CPU_N11 [93]
PEG_RXN_11 PEG_TXN_11
PEG_RX_CPU_P12 P6 N1 PEG_TX_CPU_P12 SKT303 SKT304
[93] PEG_RX_CPU_P12 PEG_RX_CPU_N12 PEG_RXP_12 PEG_TXP_12 PEG_TX_CPU_N12 PEG_TX_CPU_P12 [93]
P5 N2
[93] PEG_RX_CPU_N12 PEG_RXN_12 PEG_TXN_12 PEG_TX_CPU_N12 [93]
PEG_RX_CPU_P13 R5 P2 PEG_TX_CPU_P13
[93] PEG_RX_CPU_P13 PEG_RX_CPU_N13 PEG_RXP_13 PEG_TXP_13 PEG_TX_CPU_N13 PEG_TX_CPU_P13 [93]
R4 P3
[93] PEG_RX_CPU_N13 PEG_RXN_13 PEG_TXN_13 PEG_TX_CPU_N13 [93]
PEG_RX_CPU_P14 T6 R2 PEG_TX_CPU_P14
[93] PEG_RX_CPU_P14 PEG_RX_CPU_N14 PEG_RXP_14 PEG_TXP_14 PEG_TX_CPU_N14 PEG_TX_CPU_P14 [93]
T5 R1
[93] PEG_RX_CPU_N14 PEG_RXN_14 PEG_TXN_14 PEG_TX_CPU_N14 [93]
PEG_RX_CPU_P15 U5 T2 PEG_TX_CPU_P15
[93] PEG_RX_CPU_P15 PEG_RX_CPU_N15 PEG_RXP_15 PEG_TXP_15 PEG_TX_CPU_N15 PEG_TX_CPU_P15 [93]
[93] PEG_RX_CPU_N15 U4 T3 PEG_TX_CPU_N15 [93]
0D95V_CPU_VCCIO PEG_RXN_15 PEG_TXN_15
R301 24D9R2F-L-GP
1 2 PEG_RCOMP_CPU L7
PEG_RCOMP
ILMCOVER ASSY BACK PLATE
(22.78005.281)
(60.3EQ19.002)
DMI_RX_CPU_P0 Y3 AC2 DMI_TX_CPU_P0
[16] DMI_RX_CPU_P0 DMI_RX_CPU_N0 DMI_RXP_0 DMI_TXP_0 DMI_TX_CPU_N0 DMI_TX_CPU_P0 [16]
Y4 AC1
[16] DMI_RX_CPU_N0 DMI_RXN_0 DMI_TXN_0 DMI_TX_CPU_N0 [16]
B DMI_RX_CPU_P1 DMI_TX_CPU_P1 B
AA4 AD3
[16] DMI_RX_CPU_P1 DMI_RX_CPU_N1 DMI_RXP_1 DMI_TXP_1 DMI_TX_CPU_N1 DMI_TX_CPU_P1 [16]
AA5 AD2
[16] DMI_RX_CPU_N1 DMI_RXN_1 DMI_TXN_1 DMI_TX_CPU_N1 [16]
DMI_RX_CPU_P2 AB4 AE2 DMI_TX_CPU_P2
[16] DMI_RX_CPU_P2 DMI_RX_CPU_N2 DMI_RXP_2 DMI_TXP_2 DMI_TX_CPU_N2 DMI_TX_CPU_P2 [16]
[16] DMI_RX_CPU_N2 AB3 AE1 DMI_TX_CPU_N2 [16]
DMI_RXN_2 DMI_TXN_2
DMI_RX_CPU_P3 AC4 AF2 DMI_TX_CPU_P3
[16] DMI_RX_CPU_P3 DMI_RX_CPU_N3 DMI_RXP_3 DMI_TXP_3 DMI_TX_CPU_N3 DMI_TX_CPU_P3 [16]
[16] DMI_RX_CPU_N3 AC5 AF3 DMI_TX_CPU_N3 [16]
DMI_RXN_3 DMI_TXN_3

SKYLAKE-1,SKL-S,LAKE-S

PCH HSINK D7 AURAS


(R_)

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(PCIE/DMI)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 3 of 107
5 4 3 2 1
5 4 3 2 1

PLACE NEAR CPU

R401 56D2R2F-GP
V_CPU_ST_PLL 1 2

R403
1
100R2F-L1-GP-U
2
Vinafix.com
CPU1E 5 OF 12
D SKL_PCUDEBUG_0 [99] D

R404 1KR2F-3-GP PCH_CPU_BCLK_DP W5 Lake-S H15 SKL_PCUDEBUG_0 1 TP404


[18] PCH_CPU_BCLK_DP PCH_CPU_BCLK_DN BCLKP CFG_0 SKL_PCUDEBUG_1
20170417 1 2 W4 F15 1 TP405
add R2422 [18] PCH_CPU_BCLK_DN BCLKN CFG_1 F16 SKL_PCUDEBUG_2 1 TP406
PCH_CPU_PCIBCLK_DP W1 CFG_2 H16 SKL_PCUDEBUG_3 1 TP407
[18] PCH_CPU_PCIBCLK_DP PCH_CPU_PCIBCLK_DN PCI_BCLKP CFG_3 SKL_PCUDEBUG_4
W2 F19 R424 1 2 1KR2J-1-GP
[18] PCH_CPU_PCIBCLK_DN PCI_BCLKN CFG_4 H18 SKL_PCUDEBUG_5 1 TP408
R405 220R2F-GP PCH_CPU_NSSC_CLK_DP K9 CFG_5 G21 SKL_PCUDEBUG_6 1 TP409
VIDALERT#_CPU_R 1 2 VIDALERT#_CPU [18] PCH_CPU_NSSC_CLK_DP PCH_CPU_NSSC_CLK_DN J9 CLK24P CFG_6 H20 SKL_PCUDEBUG_7 1
[44] VIDALERT#_CPU_R TP410
[18] PCH_CPU_NSSC_CLK_DN CLK24N CFG_7 SKL_PCUDEBUG_8
G16 1 TP411
CFG_8 E16 SKL_PCUDEBUG_9 R425 1 2 1KR2J-1-GP (R_)
CFG_9 SKL_PCUDEBUG_10 0D95V_CPU_VCCIO
R407 0R0402-PAD-2-GP F17 1 TP412 20170607
VIDSCK_CPU_R 1 2 VIDSCK_CPU CFG_10 H17 SKL_PCUDEBUG_11 1 TP413 Remove R406 & C401
[44] VIDSCK_CPU_R CFG_11 SKL_PCUDEBUG_12
G20 1 TP414
CFG_12 F20 SKL_PCUDEBUG_13 1 TP415
R408 0R0402-PAD-2-GP CFG_13 F21 SKL_PCUDEBUG_14 R426 1 2 1KR2J-1-GP (R_)
VIDSOUT_CPU_R 1 2 VIDSOUT_CPU VIDALERT#_CPU E39 CFG_14 H19 SKL_PCUDEBUG_15 1 TP416
[44] VIDSOUT_CPU_R VIDSCK_CPU VIDALERT# CFG_15
E38
VIDSOUT_CPU E40 VIDSCK F14 SKL_PCUSTB_0_DP 1 TP419
R409 499R2F-2-GP PROCHOT#_CPU C39 VIDSOUT CFG_17 E14 SKL_PCUSTB_0_DN 1 TP420
PROCHOT#_CPU_R 1 2 PROCHOT#_CPU PROCHOT# CFG_16 F18 SKL_PCUSTB_1_DP 1 TP421
[24,44] PROCHOT#_CPU_R SM_PGCNTL CFG_19 SKL_PCUSTB_1_DN
AC36 G18 1 TP422
H_SKTOCC_CPU AC38 DDR_VTT_CNTL CFG_18
[24] H_SKTOCC_CPU SKTOCC# D16 BPM_CPU_N0 1 TP417
BPM#_0 D17 BPM_CPU_N1 1 TP418
BPM#_1 G14 BPM_CPU_N2 1 TP401
VCCST_GD_CPU U2 BPM#_2 H14 BPM_CPU_N3 1 TP402
VCCST_PWRGD BPM#_3 H_TDO R402 1 2 100R2F-L1-GP-U
H_PWRGD V_CPU_ST_PLL
F8
[20,99] H_PWRGD PLTRST_CPU_N PROCPWRGD H_TDO PCH_JTAG_TDO
E7 H13 R410 1 2 0R0402-PAD-2-GP PCH_JTAG_TDO [20]
[17,99] PLTRST_CPU_N PM_SYNC_CPU RESET# PROC_TDO H_TDI PCH_JTAG_TDI
E8 G12 R411 1 2 0R0402-PAD-2-GP
[17] PM_SYNC_CPU PM_DOWN_CPU PM_SYNC PROC_TDI H_TMS PCH_JTAG_TMS PCH_JTAG_TDI [20]
D8 F13 R412 1 2 0R0402-PAD-2-GP
PECI_CPU PM_DOWN PROC_TMS H_TCK PCH_JTAG_TMS [20]
G7 F11 H_TCK [20]
[24] PECI_CPU THERMTRIP#_CPU D11 PECI PROC_TCK
[17] THERMTRIP#_CPU THERMTRIP# F12 H_TRST_N R417 1 2 0R0402-PAD-2-GP H_TRST_N_R
PROC_TRST# H_PREQ_N H_TRST_N_R [22]
B9
SKL_CNL_N PROC_PREQ# H_PRDY_N H_PREQ_N [99]
R422 1 2 10KR2J-3-GP AB36 B10
0D95V_CPU_VCCIO PROC_SELECT# PROC_PRDY# H_PRDY_N [99]
C (R_) C
TP403 1 CATERR#_CPU D13 R418 49D9R2F-GP
CATERR#

1
M11 TPEV_CFG_RCOMP 1 2
CFG_RCOMP R427 R415
51R2F-2-GP 51R2F-2-GP
(R_)

2
SKYLAKE-1,SKL-S,LAKE-S

R423
1K5R2F-2-GP
For EMI
H_PWRGD
C402 SCD1U16V2KX-L-GP SKL_PCUDEBUG_3 1 2 XDP_PCUDEBUG_3
XDP_PCUDEBUG_3 [99]
R419 6K04R2F-GP 1 2
VCCST_GD_DRIVER 1 2 VCCST_GD_CPU (R_)
[40,99] VCCST_GD_DRIVER
1

R420
2K8R2F-GP C403 SCD1U16V2KX-L-GP
PLTRST_CPU_N 1 2
(R_)
2

R421 20R2F-GP
PM_DOWN_PCH 1 2 PM_DOWN_CPU
[17] PM_DOWN_PCH

B B

3D3V_SB

3D3V_SB

1
R413

1
10KR2J-3-GP
R414
100KR2J-1-GP

2
U401
DDR_VTT_CNTL_GATE 6 1

2
R416 10KR2J-3-GP
5 2 DDR_VTT_CNTL_R 1 2 SM_PGCNTL

4 3 DDR_VTT_CNTL_CPU
DDR_VTT_CNTL_CPU [40]
MMDT3904-2-GP

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(THERMAL/CLOCK/PM/CFG)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 4 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

CPU1A 1 OF 12
[11] M_A_DQ[0..63] M_A_DQ5 M_A_CLK0
AE38 Lake-S AW18
M_A_DQ1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0 M_A_CLK#0 M_A_CLK0 [11]
AE37 AV18
M_A_DQ2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0 M_A_CLK1 M_A_CLK#0 [11]
AG38 AW17 M_A_CLK1 [11]
M_A_DQ3 AG37 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1 AY17 M_A_CLK#1
M_A_DQ4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1 M_A_CLK#1 [11]
AE39 AW16
M_A_DQ0 AE40 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_2 AV16
M_A_DQ6 AG39 DDR0_DQ_5/DDR0_DQ_5 DDR0_CKN_2 AT16
M_A_DQ7 AG40 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKP_3 AU16
M_A_DQ13 AJ38 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKN_3
M_A_DQ9 AJ37 DDR0_DQ_8/DDR0_DQ_8 AY24 M_A_CKE0
M_A_DQ10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0 M_A_CKE1 M_A_CKE0 [11]
AL38 AW24
M_A_DQ11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1 M_A_CKE1 [11]
AL37 AV24
M_A_DQ8 AJ40 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2 AV25
M_A_DQ12 AJ39 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3
M_A_DQ14 AL39 DDR0_DQ_13/DDR0_DQ_13 AW12 M_A_CS#0
M_A_DQ15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0 M_A_CS#1 M_A_CS#0 [11]
AL40 AU11
M_A_DQ21 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1 M_A_CS#1 [11]
AN38 AV13
M_A_DQ16 AN40 DDR0_DQ_16/DDR0_DQ_32 DDR0_CS#_2 AV10
M_A_DQ18 AR38 DDR0_DQ_17/DDR0_DQ_33 DDR0_CS#_3
M_A_DQ19 AR37 DDR0_DQ_18/DDR0_DQ_34 AW11 M_A_ODT0
M_A_DQ20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0 M_A_ODT1 M_A_ODT0 [11]
AN39 AU14
M_A_DQ17 DDR0_DQ_20/DDR0_DQ_36 DDR0_ODT_1 M_A_ODT1 [11]
AN37 AU12
M_A_DQ22 AR39 DDR0_DQ_21/DDR0_DQ_37 DDR0_ODT_2 AY10
M_A_DQ23 AR40 DDR0_DQ_22/DDR0_DQ_38 DDR0_ODT_3
M_A_DQ25 AW37 DDR0_DQ_23/DDR0_DQ_39 AY13 M_A_BS0
M_A_DQ28 DDR0_DQ_24/DDR0_DQ_40 DDR0_BA_0 M_A_BS1 M_A_BS0 [11]
AU38 AV15
M_A_DQ27 DDR0_DQ_25/DDR0_DQ_41 DDR0_BA_1 M_A_BG0 M_A_BS1 [11]
AV35 AW23
M_A_DQ31 DDR0_DQ_26/DDR0_DQ_42 DDR0_BG_0 M_A_BG0 [11]
C AW35 C
M_A_DQ29 AU37 DDR0_DQ_27/DDR0_DQ_43 AW13 M_A_A16
M_A_DQ24 DDR0_DQ_28/DDR0_DQ_44 DDR0_MA_16 M_A_A14 M_A_A16 [11]
AV37 AV14 M_A_A14 [11]
M_A_DQ30 AT35 DDR0_DQ_29/DDR0_DQ_45 DDR0_MA_14 AY11 M_A_A15
M_A_DQ26 DDR0_DQ_30/DDR0_DQ_46 DDR0_MA_15 M_A_A15 [11]
AU35
M_A_DQ32 AY8 DDR0_DQ_31/DDR0_DQ_47 AW15 M_A_A0
M_A_DQ36 DDR0_DQ_32/DDR1_DQ_0 DDR0_MA_0 M_A_A1 M_A_A0 [11]
AW8 AU18
M_A_DQ34 DDR0_DQ_33/DDR1_DQ_1 DDR0_MA_1 M_A_A2 M_A_A1 [11]
AV6 AU17 M_A_A2 [11]
M_A_DQ35 AU6 DDR0_DQ_34/DDR1_DQ_2 DDR0_MA_2 AV19 M_A_A3
M_A_DQ33 DDR0_DQ_35/DDR1_DQ_3 DDR0_MA_3 M_A_A4 M_A_A3 [11]
AU8 AT19
M_A_DQ37 DDR0_DQ_36/DDR1_DQ_4 DDR0_MA_4 M_A_A5 M_A_A4 [11]
AV8 AU20 M_A_A5 [11]
M_A_DQ39 AW6 DDR0_DQ_37/DDR1_DQ_5 DDR0_MA_5 AV20 M_A_A6
M_A_DQ38 DDR0_DQ_38/DDR1_DQ_6 DDR0_MA_6 M_A_A7 M_A_A6 [11]
AY6 AU21 M_A_A7 [11]
M_A_DQ44 AY4 DDR0_DQ_39/DDR1_DQ_7 DDR0_MA_7 AT20 M_A_A8
M_A_DQ40 DDR0_DQ_40/DDR1_DQ_8 DDR0_MA_8 M_A_A9 M_A_A8 [11]
AV4 AT22
M_A_DQ47 DDR0_DQ_41/DDR1_DQ_9 DDR0_MA_9 M_A_A10 M_A_A9 [11]
AT1 AY14 M_A_A10 [11]
M_A_DQ43 AT2 DDR0_DQ_42/DDR1_DQ_10 DDR0_MA_10 AU22 M_A_A11
M_A_DQ41 DDR0_DQ_43/DDR1_DQ_11 DDR0_MA_11 M_A_A12 M_A_A11 [11]
AV3 AV22 M_A_A12 [11]
M_A_DQ45 AW4 DDR0_DQ_44/DDR1_DQ_12 DDR0_MA_12 AV12 M_A_A13
M_A_DQ46 DDR0_DQ_45/DDR1_DQ_13 DDR0_MA_13 M_A_BG1 M_A_A13 [11]
AT4 AV23
M_A_DQ42 DDR0_DQ_46/DDR1_DQ_14 DDR0_BG_1 M_A_ACT# M_A_BG1 [11]
AT3 AU24 M_A_ACT# [11]
M_A_DQ49 AP2 DDR0_DQ_47/DDR1_DQ_15 DDR0_ACT#
M_A_DQ54 AM4 DDR0_DQ_48/DDR1_DQ_32 AY15 M_A_PARITY
M_A_DQ53 DDR0_DQ_49/DDR1_DQ_33 DDR0_PAR M_A_ALERT# M_A_PARITY [11]
AP3 AT23
M_A_DQ50 DDR0_DQ_50/DDR1_DQ_34 DDR0_ALERT# M_A_ALERT# [11]
AM3
M_A_DQ52 AP4 DDR0_DQ_51/DDR1_DQ_35
M_A_DQ51 AM2 DDR0_DQ_52/DDR1_DQ_36 AF39 M_A_DQS_DN0
M_A_DQ48 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSN_0/DDR0_DQSN_0 M_A_DQS_DN1 M_A_DQS_DN0 [11]
AP1 AK39 M_A_DQS_DN1 [11]
M_A_DQ55 AM1 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_1/DDR0_DQSN_1 AP39 M_A_DQS_DN2
M_A_DQ61 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSN_2/DDR0_DQSN_4 M_A_DQS_DN3 M_A_DQS_DN2 [11]
AK3 AU36
M_A_DQ63 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_3/DDR0_DQSN_5 M_A_DQS_DN4 M_A_DQS_DN3 [11]
AH1 AW7 M_A_DQS_DN4 [11]
M_A_DQ60 AK4 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSN_4/DDR1_DQSN_0 AU3 M_A_DQS_DN5
M_A_DQ59 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQSN_5/DDR1_DQSN_1 M_A_DQS_DN6 M_A_DQS_DN5 [11]
AH2 AN3 M_A_DQS_DN6 [11]
M_A_DQ62 AH4 DDR0_DQ_59/DDR1_DQ_43 DDR0_DQSN_6/DDR1_DQSN_4 AJ3 M_A_DQS_DN7
M_A_DQ57 DDR0_DQ_60/DDR1_DQ_44 DDR0_DQSN_7/DDR1_DQSN_5 M_A_DQS_DN7 [11]
AK2
M_A_DQ58 AH3 DDR0_DQ_61/DDR1_DQ_45 AF38 M_A_DQS_DP0
M_A_DQ56 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 M_A_DQS_DP1 M_A_DQS_DP0 [11]
AK1 AK38
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 M_A_DQS_DP2 M_A_DQS_DP1 [11]
AP38 M_A_DQS_DP2 [11]
B
AU33 DDR0_DQSP_2/DDR0_DQSP_4 AV36 M_A_DQS_DP3 B
DDR0_ECC_0 DDR0_DQSP_3/DDR0_DQSP_5 M_A_DQS_DP4 M_A_DQS_DP3 [11]
AT33 AV7
DDR0_ECC_1 DDR0_DQSP_4/DDR1_DQSP_0 M_A_DQS_DP5 M_A_DQS_DP4 [11]
AW33 AU2 M_A_DQS_DP5 [11]
AV31 DDR0_ECC_2 DDR0_DQSP_5/DDR1_DQSP_1 AN2 M_A_DQS_DP6
DDR0_ECC_3 DDR0_DQSP_6/DDR1_DQSP_4 M_A_DQS_DP7 M_A_DQS_DP6 [11]
AU31 AJ2 M_A_DQS_DP7 [11]
AV33 DDR0_ECC_4 DDR0_DQSP_7/DDR1_DQSP_5
AW31 DDR0_ECC_5 AV32
AY31 DDR0_ECC_6 DDR0_DQSP_8/DDR0_DQSP_8 AU32
DDR0_ECC_7 DDR0_DQSN_8/DDR0_DQSN_8

DDR CHANNEL A

SKYLAKE-1,SKL-S,LAKE-S

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(DDR_CHA)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 5 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

CPU1B 2 OF 12

[12] M_B_DQ[0..63] M_B_DQ4 M_B_CLK0


AD34 Lake-S AM20
M_B_DQ5 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0 M_B_CLK#0 M_B_CLK0 [12]
AD35 AM21 M_B_CLK#0 [12]
M_B_DQ7 AG35 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0 AP22 M_B_CLK1
M_B_DQ3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1 M_B_CLK#1 M_B_CLK1 [12]
AH35 AP21 M_B_CLK#1 [12]
M_B_DQ1 AE35 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1 AN20
M_B_DQ0 AE34 DDR1_DQ_4/DDR0_DQ_20 DDR1_CKP_2 AN21
M_B_DQ6 AG34 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKN_2 AP19
M_B_DQ2 AH34 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKP_3 AP20
M_B_DQ13 AK35 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKN_3
M_B_DQ9 AL35 DDR1_DQ_8/DDR0_DQ_24 AY29 M_B_CKE0
M_B_DQ14 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0 M_B_CKE1 M_B_CKE0 [12]
AK32 AV29
M_B_DQ15 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1 M_B_CKE1 [12]
AL32 AW29
M_B_DQ12 AK34 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2 AU29
M_B_DQ8 AL34 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3
M_B_DQ10 AK31 DDR1_DQ_13/DDR0_DQ_29 AP17 M_B_CS#0
M_B_DQ11 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0 M_B_CS#1 M_B_CS#0 [12]
AL31 AN15
M_B_DQ16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1 M_B_CS#1 [12]
AP35 AN17
M_B_DQ20 AN35 DDR1_DQ_16/DDR0_DQ_48 DDR1_CS#_2 AM15
M_B_DQ22 AN32 DDR1_DQ_17/DDR0_DQ_49 DDR1_CS#_3
M_B_DQ23 AP32 DDR1_DQ_18/DDR0_DQ_50 AM16 M_B_ODT0
M_B_DQ17 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0 M_B_ODT1 M_B_ODT0 [12]
AN34 AL16
M_B_DQ21 DDR1_DQ_20/DDR0_DQ_52 DDR1_ODT_1 M_B_ODT1 [12]
AP34 AP15
M_B_DQ18 AN31 DDR1_DQ_21/DDR0_DQ_53 DDR1_ODT_2 AL15
M_B_DQ19 AP31 DDR1_DQ_22/DDR0_DQ_54 DDR1_ODT_3
M_B_DQ28 AL29 DDR1_DQ_23/DDR0_DQ_55 AN18 M_B_A16
M_B_DQ24 DDR1_DQ_24/DDR0_DQ_56 DDR1_MA_16 M_B_A14 M_B_A16 [12]
AM29 AL17
M_B_DQ30 DDR1_DQ_25/DDR0_DQ_57 DDR1_MA_14 M_B_A15 M_B_A14 [12]
AP29 AP16 M_B_A15 [12]
M_B_DQ26 AR29 DDR1_DQ_26/DDR0_DQ_58 DDR1_MA_15
M_B_DQ25 DDR1_DQ_27/DDR0_DQ_59 M_B_BS0
For DDR4 Modify
AM28 AL18 M_B_BS0 [12]
M_B_DQ29 AL28 DDR1_DQ_28/DDR0_DQ_60 DDR1_BA_0 AM18 M_B_BS1
M_B_DQ27 DDR1_DQ_29/DDR0_DQ_61 DDR1_BA_1 M_B_BG0 M_B_BS1 [12]
AR28 AW28
M_B_DQ31 DDR1_DQ_30/DDR0_DQ_62 DDR1_BG_0 M_B_BG0 [12]
C AP28 C
M_B_DQ32 AR12 DDR1_DQ_31/DDR0_DQ_63 AL19 M_B_A0
M_B_DQ33 DDR1_DQ_32/DDR1_DQ_16 DDR1_MA_0 M_B_A1 M_B_A0 [12]
AP12 AL22 M_B_A1 [12]
M_B_DQ38 AM13 DDR1_DQ_33/DDR1_DQ_17 DDR1_MA_1 AM22 M_B_A2
M_B_DQ34 DDR1_DQ_34/DDR1_DQ_18 DDR1_MA_2 M_B_A3 M_B_A2 [12]
AL13 AM23
M_B_DQ36 DDR1_DQ_35/DDR1_DQ_19 DDR1_MA_3 M_B_A4 M_B_A3 [12]
AR13 AP23 M_B_A4 [12]
M_B_DQ37 AP13 DDR1_DQ_36/DDR1_DQ_20 DDR1_MA_4 AL23 M_B_A5
M_B_DQ39 DDR1_DQ_37/DDR1_DQ_21 DDR1_MA_5 M_B_A6 M_B_A5 [12]
AM12 AW26 M_B_A6 [12]
M_B_DQ35 AL12 DDR1_DQ_38/DDR1_DQ_22 DDR1_MA_6 AY26 M_B_A7
M_B_DQ44 DDR1_DQ_39/DDR1_DQ_23 DDR1_MA_7 M_B_A8 M_B_A7 [12]
AP10 AU26
M_B_DQ45 DDR1_DQ_40/DDR1_DQ_24 DDR1_MA_8 M_B_A9 M_B_A8 [12]
AR10 AW27 M_B_A9 [12]
M_B_DQ46 AR7 DDR1_DQ_41/DDR1_DQ_25 DDR1_MA_9 AP18 M_B_A10
M_B_DQ42 DDR1_DQ_42/DDR1_DQ_26 DDR1_MA_10 M_B_A11 M_B_A10 [12]
AP7 AU27 M_B_A11 [12]
M_B_DQ41 AR9 DDR1_DQ_43/DDR1_DQ_27 DDR1_MA_11 AV27 M_B_A12
M_B_DQ40 DDR1_DQ_44/DDR1_DQ_28 DDR1_MA_12 M_B_A13 M_B_A12 [12]
AP9 AR15
M_B_DQ47 DDR1_DQ_45/DDR1_DQ_29 DDR1_MA_13 M_B_BG1 M_B_A13 [12]
AR6 AY28 M_B_BG1 [12]
M_B_DQ43 AP6 DDR1_DQ_46/DDR1_DQ_30 DDR1_BG_1 AU28 M_B_ACT#
M_B_DQ52 DDR1_DQ_47/DDR1_DQ_31 DDR1_ACT# M_B_ACT# [12]
AM10 For DDR4 Modify
M_B_DQ53 AL10 DDR1_DQ_48/DDR1_DQ_48 AL20 M_B_PARITY
M_B_DQ55 DDR1_DQ_49/DDR1_DQ_49 DDR1_PAR M_B_ALERT# M_B_PARITY [12]
AM7 AY25
M_B_DQ51 DDR1_DQ_50/DDR1_DQ_50 DDR1_ALERT# M_B_ALERT# [12]
AL7
M_B_DQ48 AM9 DDR1_DQ_51/DDR1_DQ_51
M_B_DQ49 AL9 DDR1_DQ_52/DDR1_DQ_52 AF34 M_B_DQS_DN0
M_B_DQ54 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSN_0/DDR0_DQSN_2 M_B_DQS_DN1 M_B_DQS_DN0 [12]
AM6 AK33
M_B_DQ50 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_1/DDR0_DQSN_3 M_B_DQS_DN2 M_B_DQS_DN1 [12]
AL6 AN33
M_B_DQ61 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSN_2/DDR0_DQSN_6 M_B_DQS_DN3 M_B_DQS_DN2 [12]
AJ6 AN29 M_B_DQS_DN3 [12]
M_B_DQ56 AJ7 DDR1_DQ_56/DDR1_DQ_56 DDR1_DQSN_3/DDR0_DQSN_7 AN13 M_B_DQS_DN4
M_B_DQ63 DDR1_DQ_57/DDR1_DQ_57 DDR1_DQSN_4/DDR1_DQSN_2 M_B_DQS_DN5 M_B_DQS_DN4 [12]
AE6 AR8 M_B_DQS_DN5 [12]
M_B_DQ58 AF7 DDR1_DQ_58/DDR1_DQ_58 DDR1_DQSN_5/DDR1_DQSN_3 AM8 M_B_DQS_DN6
M_B_DQ60 DDR1_DQ_59/DDR1_DQ_59 DDR1_DQSN_6/DDR1_DQSN_6 M_B_DQS_DN7 M_B_DQS_DN6 [12]
AH7 AG6
M_B_DQ57 DDR1_DQ_60/DDR1_DQ_60 DDR1_DQSN_7/DDR1_DQSN_7 M_B_DQS_DN7 [12]
AH6
M_B_DQ59 AE7 DDR1_DQ_61/DDR1_DQ_61 AF35 M_B_DQS_DP0
M_B_DQ62 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 M_B_DQS_DP1 M_B_DQS_DP0 [12]
AF6 AL33 M_B_DQS_DP1 [12]
DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 AP33 M_B_DQS_DP2
DDR1_DQSP_2/DDR0_DQSP_6 M_B_DQS_DP3 M_B_DQS_DP2 [12]
AR25 AN28
DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 M_B_DQS_DP4 M_B_DQS_DP3 [12]
AR26 AN12 M_B_DQS_DP4 [12]
AM26 DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 AP8 M_B_DQS_DP5
DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 M_B_DQS_DP6 M_B_DQS_DP5 [12]
AM25 AL8 M_B_DQS_DP6 [12]
B
AP26 DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 AG7 M_B_DQS_DP7 B
DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 M_B_DQS_DP7 [12]
AP25 R601 2R2F-GP
AL25 DDR1_ECC_5 AN25 V_SM_VREF_CNT 1 2 DIMM_CA_VREF_A
DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 DIMM_CA_VREF_A [11]
AL26 AN26
DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8

1
C601 C602
DDR CHANNEL B SCD1U16V2KX-3DLGP SCD022U16V2KX-3DLGP

2
AB40 V_SM_VREF_CNT DIMM_CA_CPU_VREF_RC
DDR_VREF_CA AC40 M_VREF_DQ_DIM0 1 TP601

1
DDR0_VREF_DQ AC39 M_VREF_DQ_DIM1
DDR1_VREF_DQ M_VREF_DQ_DIM1 [12]
R602
SKYLAKE-1,SKL-S,LAKE-S 24D9R2F-L-GP

2
M_VREF_DQ_DIM1 C603 1 2 SCD1U16V2KX-3DLGP

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(DDR_CHB)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 6 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

CPU1D 4 OF 12

HDMI_DATA_CPU_P0 C21 Lake-S E10


[56] HDMI_DATA_CPU_P0 HDMI_DATA_CPU_N0 D21 DDI1_TXP_0 EDP_TXP_0 D10
[56] HDMI_DATA_CPU_N0 HDMI_DATA_CPU_P1 D22 DDI1_TXN_0 EDP_TXN_0 D9
[56] HDMI_DATA_CPU_P1 HDMI_DATA_CPU_N1 E22 DDI1_TXP_1 EDP_TXP_1 C9
[56] HDMI_DATA_CPU_N1 HDMI_DATA_CPU_P2 B23 DDI1_TXN_1 EDP_TXN_1 H10 DDI_VGA_DATA_CPU_N2
[56] HDMI_DATA_CPU_P2 HDMI_DATA_CPU_N2 A23 DDI1_TXP_2 EDP_TXN_2 G10 DDI_VGA_DATA_CPU_P2 DDI_VGA_DATA_CPU_N2 [59]
C C
[56] HDMI_DATA_CPU_N2 HDMI_DATA_CPU_P3 C23 DDI1_TXN_2 EDP_TXP_2 G9 DDI_VGA_DATA_CPU_N3 DDI_VGA_DATA_CPU_P2 [59]
[56] HDMI_DATA_CPU_P3 HDMI_DATA_CPU_N3 D23 DDI1_TXP_3 EDP_TXN_3 F9 DDI_VGA_DATA_CPU_P3 DDI_VGA_DATA_CPU_N3 [59]
[56] HDMI_DATA_CPU_N3 DDI1_TXN_3 EDP_TXP_3 DDI_VGA_DATA_CPU_P3 [59]
B13 D12 DP_AUX_CPU_P
DDI1_AUXP EDP_AUXP DP_AUX_CPU_N DP_AUX_CPU_P [59]
C13 E12
DDI1_AUXN EDP_AUXN DP_AUX_CPU_N [59]
B18
A18 DDI2_TXP_0
D18 DDI2_TXN_0 D14 DISP_UTIL_CPU 1 TP701
E18 DDI2_TXP_1 EDP_DISP_UTIL 0D95V_CPU_VCCIO
C19 DDI2_TXN_1 R701 24D9R2F-L-GP
D19 DDI2_TXP_2 M9 FDI_COMP 1 2
D20 DDI2_TXN_2 DISP_RCOMP
E20 DDI2_TXP_3
DDI2_TXN_3
A12
B12 DDI2_AUXP
DDI2_AUXN
B14
A14 DDI3_TXP_0
C15 DDI3_TXN_0
B15 DDI3_TXP_1
B16 DDI3_TXN_1
A16 DDI3_TXP_2
C17 DDI3_TXN_2
B17 DDI3_TXP_3
DDI3_TXN_3 V3 AUD_AZACPU_SCLK
PROC_AUDIO_CLK AUD_AZACPU_SDO AUD_AZACPU_SCLK [20]
B11 V2
C11 DDI3_AUXP PROC_AUDIO_SDI U1 AUD_AZACPU_SDI 1 2 AUD_AZACPU_SDI_R AUD_AZACPU_SDO [20]
DDI3_AUXN PROC_AUDIO_SDO AUD_AZACPU_SDI_R [20]
R702
SKYLAKE-1,SKL-S,LAKE-S 20R2J-3-GP

B B

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(DDI/EDP)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 7 of 107
5 4 3 2 1
5 4 3 2 1

CPU1G 7 OF 12 CPU1H 8 OF 12 CPU1I 9 OF 12

A25 Lake-S H32 AA34 Lake-S AA7 Lake-S AT18


1V_CPU_CORE VCC1 VCC90 1V_CPU_CORE 1V_CPU_GT VCCGT1 1D05V_CPU_SA VCCSA2 VDDQ1 1D2V_SM_S3
A26 J21 AA35 AB6 AT21
A27 VCC2 VCC93 F32 AA36 VCCGT2 AB7 VCCSA3 VDDQ2 AU13
A28 VCC3 VCC68 F33 AA37 VCCGT3 AB8 VCCSA4 VDDQ3 AU15
A29 VCC4 VCC69 F34 AA38 VCCGT4 AC7 VCCSA5 VDDQ4 AU19

Vinafix.com
A30 VCC5 VCC70 G23 AB33 VCCGT5 AC8 VCCSA6 VDDQ5 AU23
B25 VCC6 VCC73 G24 AB34 VCCGT6 N7 VCCSA7 VDDQ6 AV11
B27 VCC24 VCC74 G25 G36 VCCGT7 P7 VCCSA8 VDDQ7 AV17
B29 VCC25 VCC75 G26 G37 VCCGT8 R7 VCCSA9 VDDQ8 AV21
B31 VCC26 VCC76 G27 G38 VCCGT9 T7 VCCSA10 VDDQ9 AW10
D
B32 VCC27 VCC77 G28 G39 VCCGT10 U7 VCCSA11 VDDQ10 AW14 D
B33 VCC28 VCC78 G29 G40 VCCGT11 Y6 VCCSA12 VDDQ11 AW25
B34 VCC29 VCC79 J22 H36 VCCGT12 Y7 VCCSA15 VDDQ12 AY12
B35 VCC30 VCC94 J23 H38 VCCGT13 Y8 VCCSA16 VDDQ13 AY16
B36 VCC31 VCC95 J24 H40 VCCGT14 W7 VCCSA17 VDDQ14 AY18
B37 VCC32 VCC96 J25 J36 VCCGT15 V7 VCCSA14 VDDQ15 AY23
C25 VCC33 VCC97 J26 J37 VCCGT16 AA6 VCCSA13 VDDQ16 R801 0R0402-PAD-2-GP
C26 VCC34 VCC98 J27 J38 VCCGT17 VCCSA1 AJ9 VCCPLL_OC_R 1 2
VCC35 VCC99 VCCGT18 VCCPLL_OC 1D2V_SM_S3
C27 J28 J39
C28 VCC36 VCC100 J29 J40 VCCGT19 AK11
VCC37 VCC101 VCCGT20 0D95V_CPU_VCCIO VCCIO2
C29 J30 K36 AK14
C30 VCC38 VCC102 J31 K38 VCCGT21 AK24 VCCIO3
C32 VCC39 VCC103 K16 K40 VCCGT22 AJ23 VCCIO4
C34 VCC40 VCC106 K18 L34 VCCGT23 M8 VCCIO1
C36 VCC41 VCC107 K20 L35 VCCGT24 P8 VCCIO5
D25 VCC42 VCC108 K21 L36 VCCGT25 T8 VCCIO6
D27 VCC43 VCC109 K23 L37 VCCGT26 U8 VCCIO7 C801 SC1U10V2KX-1DLGP
D29 VCC44 VCC110 K25 L38 VCCGT27 W8 VCCIO8 VCCPLL_OC_R 1 2
D31 VCC45 VCC111 K27 L39 VCCGT28 VCCIO9
D32 VCC46 VCC112 K29 L40 VCCGT29
D33 VCC47 VCC113 K31 M33 VCCGT30 20170414
D34 VCC48 VCC114 L14 M34 VCCGT31 V5 follow CPU EDS change to mount 1x 1uF 0402
VCC49 VCC117 VCCGT32 V_CPU_ST_PLL VCCST1
D35 L15 M36 V6
D36 VCC50 VCC118 L16 M38 VCCGT33 VCCST2
E24 VCC51 VCC119 L17 M40 VCCGT34 V4
E25 VCC52 VCC120 L18 N34 VCCGT35 VCCPLL
E26 VCC53 VCC121 L19 N35 VCCGT36
E27 VCC54 VCC122 L20 N36 VCCGT37
E28 VCC55 VCC123 L21 N37 VCCGT38
E29 VCC56 VCC124 L22 N38 VCCGT39
E30 VCC57 VCC125 L23 N39 VCCGT40
E32 VCC58 VCC126 L24 N40 VCCGT41
E34 VCC59 VCC127 L25 P33 VCCGT42
E36 VCC60 VCC128 L26 P34 VCCGT43 AD5 VCCSA_SENSE
VCC61 VCC129 VCCGT44 VCCSA_SENSE VCCIO_SENSE VCCSA_SENSE [47]
F23 L27 P36 AF4
VCC62 VCC130 VCCGT45 VCCIO_SENSE VSS_SA_IO_SENSE VCCIO_SENSE [48]
F24 L28 P38 AE4
F25 VCC63 VCC131 L29 P40 VCCGT46 VSS_SAIO_SENSE VSS_SA_IO_SENSE [47]
F27 VCC64 VCC132 L30 R34 VCCGT47
C C
F29 VCC65 VCC133 M13 R35 VCCGT48
F31 VCC66 VCC136 M14 R36 VCCGT49
G30 VCC67 VCC137 M16 R37 VCCGT50
G32 VCC80 VCC138 M18 R38 VCCGT51
H22 VCC81 VCC139 M20 R39 VCCGT52
H23 VCC84 VCC140 M22 R40 VCCGT53
H25 VCC85 VCC141 M24 T33 VCCGT54 SKYLAKE-1,SKL-S,LAKE-S
H27 VCC86 VCC142 M26 T34 VCCGT55
H29 VCC87 VCC143 M28 T36 VCCGT56 1D2V_SM_S3 1D2V_SM_S3
H31 VCC88 VCC144 M30 T38 VCCGT57
AJ11 VCC89 VCC145 AJ12 T40 VCCGT58
VCC7 VCC8 VCCGT59

1
AJ13 AJ14 U34 C808 C807
AJ15 VCC9 VCC10 AJ16 U35 VCCGT60
VCC11 VCC12 VCCGT61 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
AJ17 AJ18 U36

2
AJ19 VCC13 VCC14 AJ20 U37 VCCGT62
AJ21 VCC15 VCC16 U38 VCCGT63
VCC17 U39 VCCGT64
M32 AJ29 U40 VCCGT65
L31 VCC146 VCC22 AK21 V33 VCCGT66
K32 VCC134 VCC23 F35 V34 VCCGT67
J33 VCC115 VCC71 F37 V36 VCCGT68
H33 VCC104 VCC72 G35 V38 VCCGT69
G34 VCC91 VCC83 H34 V40 VCCGT70
AJ25 VCC82 VCC92 J35 W34 VCCGT71
AJ26 VCC18 VCC105 K34 W35 VCCGT72
AJ27 VCC19 VCC116 L33 W36 VCCGT73
AJ28 VCC20 VCC135 W37 VCCGT74
VCC21 W38 VCCGT75 F39 VCCGT_VCC_SEN
Y33 VCCGT76 VCCGT_SENSE F38 VCCGT_VSS_SEN VCCGT_VCC_SEN [44]
VCCGT77 VSSGT_SENSE VCCGT_VSS_SEN [44]
Y34
Y36 VCCGT78
C38 VCORE_VCC_SEN Y38 VCCGT79
VCC_SENSE VCORE_VSS_SEN VCORE_VCC_SEN [44] VCCGT80
D38
VSS_SENSE VCORE_VSS_SEN [44]

SKYLAKE-1,SKL-S,LAKE-S SKYLAKE-1,SKL-S,LAKE-S
B B

R802 49D9R2F-GP
VCORE_VCC_SEN 1 2 VCORE_VSS_SEN
(R_)

1V_PCH_SB V_CPU_ST_PLL
12V_S5 R803 0R3J-0-U-GP
1 2
(R_)
1

R804

D
47KR2J-2-GP
Q801
R805 10KR2J-3-GP AO3418L-GP
2

1 2 SLP_S4_N_SFR_G G (084.03404.0031)
1

S
1

R806 C802 C803


100KR2J-1-GP SCD1U25V2KX-1-DL-GP SCD1U16V2KX-L-GP
12V_S5 (R_) V_CPU_ST_PLL
2

2
2
1

1
R807 R808
100KR2J-1-GP Q802 4K7R2J-2-GP C804 C805
4 3 SLP_S4_N_SFR_2 (R_) SC10U25V5KX-DL-GP SCD1U16V2KX-3DLGP

2
R809 0R0402-PAD-2-GP
2

2
SLP_S4_N_SFR_1 5 2 SLP_S4_N_SFR 1 2 SLP_S4_N
SLP_S4_N [20,24,32,38,39,40,99]
A A
1

6 1
1

R810 C806
100KR2J-1-GP 2N7002KDW-1-GP SCD1U16V2KX-L-GP
(R_) (R_)
2
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(CPU Power)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 8 of 107
5 4 3 2 1
5 4 3 2 1

CPU1F 6 OF 12
AR24
Vinafix.com
CPU1K

Lake-S
11 OF 12

C37
CPU1L 12 OF 12

VSS VSS Lake-S


A11 Lake-S AK29 AR27 C5 K39 AJ24
D
A13 VSS VSS AK30 AR3 VSS VSS C8 K4 VSS VSS AJ30 D
A15 VSS VSS AK36 AR30 VSS VSS C10 K7 VSS VSS AK22
A17 VSS VSS AK37 AR31 VSS VSS D24 L13 VSS VSS AK27
A24 VSS VSS AK40 AR32 VSS VSS D26 L3 VSS VSS AR22
A7 VSS VSS AK5 AR33 VSS VSS D28 L32 VSS VSS AR23
AA3 VSS VSS AK6 AR34 VSS VSS D30 L6 VSS VSS AT15
AA33 VSS VSS AK7 AR35 VSS VSS D37 L9 VSS VSS AU39
AA8 VSS VSS AK8 AR36 VSS VSS D39 M1 VSS VSS AU40
AB39 VSS VSS AK9 AR4 VSS VSS D4 M10 VSS VSS AV39
AB5 VSS VSS AL1 AR5 VSS VSS D7 M12 VSS VSS AW38
AC3 VSS VSS AL11 AT10 VSS VSS E11 M15 VSS VSS F36
AC33 VSS VSS AL14 AT11 VSS VSS E13 M17 VSS VSS H11
AC34 VSS VSS AL2 AT12 VSS VSS E15 M19 VSS VSS H12
AC35 VSS VSS AL21 AT13 VSS VSS E17 M21 VSS VSS CPU1J 10 OF 12
AC6 VSS VSS AL24 AT14 VSS VSS E19 M23 VSS
AD1 VSS VSS AL27 AT17 VSS VSS E21 M25 VSS J8 Lake-S AC37
AD33 VSS VSS AL3 AT24 VSS VSS E23 M27 VSS J7 RSVD_TP2 RSVD4 AB35
AD36 VSS VSS AL30 AT25 VSS VSS E3 M29 VSS TP903 1 TP_CPU1_L8 L8 RSVD_TP1 RSVD1 AB37
AD37 VSS VSS AL36 AT26 VSS VSS E31 M35 VSS K8 IST_TRIG RSVD2 AB38 20170510
AD38 VSS VSS AL4 AT27 VSS VSS E33 M37 VSS RSVD_TP3 RSVD3 AJ22 Remove TP901 & TP902 & TP904
AD39 VSS VSS AL5 AT28 VSS VSS E35 M39 VSS AV1 RSVD5 D15 TP905 &TP906 & TP907
AD4 VSS VSS AM11 AT29 VSS VSS E37 M4 VSS AW2 RSVD8 RSVD12 K11
AD40 VSS VSS AM14 AT30 VSS VSS E6 M7 VSS RSVD9 RSVD21
AD6 VSS VSS AM17 AT31 VSS VSS E9 N3 VSS H8
AD7 VSS VSS AM19 AT32 VSS VSS F1 N33 VSS RSVD13
AD8 VSS VSS AM24 AT34 VSS VSS F10 N6 VSS K10
AE3 VSS VSS AM27 AT36 VSS VSS F22 N8 VSS L10 RSVD20
AE33 VSS VSS AM30 AT37 VSS VSS F26 P1 VSS RSVD24
AE36 VSS VSS AM31 AT38 VSS VSS F28 P35 VSS J17
AE5 VSS VSS AM32 AT39 VSS VSS F30 P37 VSS B39 RSVD18
AE8 VSS VSS AM33 AT40 VSS VSS F4 P39 VSS 20170519 C40 RSVD10 J15
AF1 VSS VSS AM34 AT5 VSS VSS F40 P4 VSS Remove R903, CPU1_AY3 change to test point J19 RSVD11 RSVD17 J14
AF33 VSS VSS AM35 AT6 VSS VSS F7 R3 VSS R902 0R0402-PAD-2-GP RSVD19 RSVD16
AF36 VSS VSS AM36 AT7 VSS VSS G11 R33 VSS 1 2 CPU1_G8 G8 AU9
AF37 VSS VSS AM37 AT8 VSS VSS G13 R6 VSS 1 2 CPU1_AY3 AY3 VSS_G8 RSVD7 AU10
AF40 VSS VSS AM38 AT9 VSS VSS G15 R8 VSS VSS_AY3 RSVD6
AF5 VSS VSS AM39 AU1 VSS VSS G17 T1 VSS R903 0R0402-PAD-2-GP PROC_TRIGIN_CPU D1
VSS VSS VSS VSS VSS [22] PROC_TRIGIN_CPU PROC_TRIGOUT_PCH PROC_TRIGOUT_CPU PROC_TRIGIN
C AF8 AM40 AU25 G19 T35 1 2 B3 J13 C
AG1 VSS VSS AM5 AU30 VSS VSS G22 T37 VSS [22] PROC_TRIGOUT_PCH PROC_TRIGOUT RSVD15 K13
AG2 VSS VSS AN1 AU34 VSS VSS G3 T39 VSS R901 L12 RSVD23 J11
AG3 VSS VSS AN10 AU4 VSS VSS G31 T4 VSS 20R2F-GP K12 RSVD25 RSVD14
AG33 VSS VSS AN11 AU5 VSS VSS G33 U3 VSS RSVD22
AG36 VSS VSS AN14 AU7 VSS VSS G6 U33 VSS
AG4 VSS VSS AN16 AV2 VSS VSS H1 U6 VSS
AG5 VSS VSS AN19 AV26 VSS VSS H21 V1 VSS
AG8 VSS VSS AN22 AV28 VSS VSS H24 V35 VSS SKYLAKE-1,SKL-S,LAKE-S
AH33 VSS VSS AN23 AV30 VSS VSS H26 V37 VSS
AH36 VSS VSS AN24 AV34 VSS VSS H28 V39 VSS
AH37 VSS VSS AN27 AV38 VSS VSS H30 V8 VSS
AH38 VSS VSS AN30 AV5 VSS VSS H35 W3 VSS
AH39 VSS VSS AN36 AV9 VSS VSS H37 W33 VSS
AH40 VSS VSS AN4 AW3 VSS VSS H39 W6 VSS
AH5 VSS VSS AN5 AW30 VSS VSS H4 Y35 VSS
AH8 VSS VSS AN6 AW32 VSS VSS H7 Y37 VSS
AJ1 VSS VSS AN7 AW34 VSS VSS H9 Y5 VSS
AJ31 VSS VSS AN8 AW36 VSS VSS J10 VSS
AJ32 VSS VSS AN9 AW5 VSS VSS J12 A4
AJ33 VSS VSS AP11 AW9 VSS VSS L11 B38 VSS_NCTF_A4
AJ34 VSS VSS AP14 AY27 VSS VSS J16 C2 VSS_NCTF_B38
AJ35 VSS VSS AP24 AY30 VSS VSS J18 D40 VSS_NCTF_C2
AJ36 VSS VSS AP27 AY5 VSS VSS J20 VSS_NCTF_D40
AJ4 VSS VSS AP30 AY7 VSS VSS J3
AJ5 VSS VSS AP36 AY9 VSS VSS J32 SKYLAKE-1,SKL-S,LAKE-S
AJ8 VSS VSS AP37 B24 VSS VSS J34
AK10 VSS VSS AP40 B26 VSS VSS J6
AK12 VSS VSS AP5 B28 VSS VSS K1
AK13 VSS VSS AR1 B30 VSS VSS K14
AK15 VSS VSS AR11 B6 VSS VSS K15
AK16 VSS VSS AR14 C12 VSS VSS K17
AK17 VSS VSS AR16 C14 VSS VSS K19
AK18 VSS VSS AR17 C16 VSS VSS K22 20170519
AK19 VSS VSS AR18 C18 VSS VSS K24 Remove R903, CPU1_AY3 change to test point
AK20 VSS VSS AR19 C20 VSS VSS K26
AK23 VSS VSS AR2 C22 VSS VSS K28
AK25 VSS VSS AR20 C24 VSS VSS K30
B
AK26 VSS VSS AR21 C31 VSS VSS K33 B
AK28 VSS VSS C33 VSS VSS K35
VSS C35 VSS VSS K37
VSS VSS
SKYLAKE-1,SKL-S,LAKE-S
SKYLAKE-1,SKL-S,LAKE-S

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(VSS)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 9 of 107
5 4 3 2 1
5 4 3 2 1

20170518 20170518
Follow Tahoe MT MLK A00 22uF 0603*2pcs Follow Tahoe MT MLK A00 unmount 22uF 0805*3pcs
PLACE ALL 0805 CAPS ON TOP SIDE OF CPU CAVITY 1V_CPU_CORE PLACE ALL 0603 CAPS 1V_CPU_CORE IF Have enough TOP SIDE OF CPU CAVITY, On it,
1V_CPU_CORE
20170518
Follow Tahoe MT MLK A00 22uF 0805*12pcs
ON TOP SIDE OF CPU CAVITY Or at socket EDGE

1
PC1001 PC1002 PC1004 PC1005 PC1006
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
1

1
PC1007 PC1008 PC1009 PC1010 PC1011 PC1012 (78.22610.51LDL) (78.22610.51LDL) (78.22610.51LDL)

2
SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP
(R_) (R_)
Vinafix.com
SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP
(R_)
SC22U6D3V5MX-2DLGP
2

2
D D

1V_CPU_CORE
PLACE ALL 0805 CAPS AT TOP SOCKET EDGE

1
PC1018
SC22U6D3V5MX-2DLGP

1
PC1019 PC1020 PC1021 PC1022 PC1023
SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP
(78.22610.51LDL) (78.22610.51LDL) (78.22610.51LDL) (78.22610.51LDL) (78.22610.51LDL)

2
20170518
Follow Tahoe MT MLK A00 unmount 22uF 0805*5pcs

Need EE check
Need EE check
PLACE CAPS FOR DIMM PLACE CAPS IN SOCKET EDGE TOP
1D2V_SM_S3 1D2V_SM_S3
VCCST/VCCSTG
PLACE CAPS AT TOP SOCKET EDGE
V_CPU_ST_PLL
1

1
C1025 C1026 C1027 C1028 C1029 C1030 C1031
SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC22U6D3V5MX-L3-GP SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP
(R_) (R_) (R_)
2

1
C1032 C1033
SC22U6D3V5MX-2DLGP SC1U10V2KX-1DLGP

2
C 20170414 C
follow PDG change to mount 4x 47uF 0805

CRB:1*22U
0805,1*1U 0402
PLACE CAPS ON TOP SIDE PLACE CAPS
SOCKET CAVITY 20170518
Follow Tahoe MT MLK A00 22uF 0805*7pcs + unmont 2pcs
IN SOCKET EDGE TOP
1V_CPU_GT
1

1
PC1034 PC1035 PC1036 PC1037 PC1038 PC1039 PC1040 PC1041 PC1058
SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP
(R_) (R_) (R_) (R_) (R_) (R_)
2

2
PLACE CAPS
AT SOCKET EDGE ON TOP
1

PC1042 PC1043 PC1044 PC1045


SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP SC22U6D3V5MX-2DLGP
2

B B

20170518
Follow Tahoe MT MLK A00 unmount 22uF 0805*4pcs

PLACE CAPS ON TOP SIDE PLACE CAPS AT TOP SOCKET EDGE 20170518
SOCKET CAVITY Follow Tahoe MT MLK A00 22uF 0603*4pcs PLACE CAPS ON TOP SIDE
1D05V_CPU_SA
0D95V_CPU_VCCIO SOCKET CAVITY
20170518
Follow Tahoe MT MLK A00 47uF 0805*4pcs
1

1
PC1046 PC1047 PC1048 PC1049
1

PC1050 PC1051 PC1052 PC1053 SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP


SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP SC47U6D3V5MX-1DL-GP
2

2
2

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU Power CAP
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 10 of 107
5 4 3 2 1
5 4 3 2 1

DIMM1:
SA0: 0, SA1: 0
DIMM1A
Write Address: 0xA0 205
Read Address: 0xA1 227 RFU#205 NP3
230 RFU#227 NP3 NP2
144 RFU#230 NP2 NP1
RFU#144 NP1 DIMM1C
M_A_DQ[0..63] [5]

[12,24,59] SMB_CLK_MAIN
DIMM_CA_VREF_A_L

SMB_CLK_MAIN
SMB_DATA_MAIN
146

141
285
VREFCA

SCL
Vinafix.com
DQ0
DQ1
DQ2
5
150
12
157
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
2
4
6
9
VSS
VSS
VSS
VSS
VSS
VSS
147
149
151
154
[12,24,59] SMB_DATA_MAIN SDA DQ3 M_A_DQ4 VSS VSS
139 3 11 156
D
140 SA0 DQ4 148 M_A_DQ5 13 VSS VSS 158 DIMM1D
D
238 SA1 DQ5 10 M_A_DQ6 15 VSS VSS 160 59
SA2 DQ6 M_A_DQ7 VSS VSS 1D2V_SM_S3 VDD
3D3V_S0 284 155 DIMM1B 17 162 61
VDDSPD DQ7 16 M_A_DQ8 20 VSS VSS 165 64 VDD
M_A_ACT# 62 DQ8 161 M_A_DQ9 152 M_A_DQS_DN0 22 VSS VSS 167 67 VDD
[5] M_A_ACT# M_A_ALERT# ACT# DQ9 M_A_DQ10 DQS0# M_A_DQS_DP0 M_A_DQS_DN0 [5] VSS VSS VDD
208 23 153 24 169 70
[5] M_A_ALERT# DIMM1_EVENT_N ALERT# DQ10 M_A_DQ11 DQS0 M_A_DQS_DN1 M_A_DQS_DP0 [5] VSS VSS VDD
78 168 163 26 171 73
SM_DRAMRST# EVENT# DQ11 M_A_DQ12 DQS1# M_A_DQS_DP1 M_A_DQS_DN1 [5] VSS VSS VDD
[12,20] SM_DRAMRST# 58 14 164 M_A_DQS_DP1 [5] 28 173 76
M_A_PARITY 222 RESET# DQ12 159 M_A_DQ13 DQS1 174 M_A_DQS_DN2 31 VSS VSS 176 80 VDD
[5] M_A_PARITY PAR DQ13 M_A_DQ14 DQS2# M_A_DQS_DP2 M_A_DQS_DN2 [5] VSS VSS VDD
21 175 M_A_DQS_DP2 [5] 33 178 83
49 DQ14 166 M_A_DQ15 DQS2 185 M_A_DQS_DN3 35 VSS VSS 180 85 VDD
CB0 DQ15 M_A_DQ16 DQS3# M_A_DQS_DP3 M_A_DQS_DN3 [5] VSS VSS VDD
194 27 186 37 182 88
CB1 DQ16 M_A_DQ17 DQS3 M_A_DQS_DN4 M_A_DQS_DP3 [5] VSS VSS VDD
R1101 240R2F-1-GP 56 172 244 M_A_DQS_DN4 [5] 39 184 90
1 2 DIMM1_EVENT_N 201 CB2 DQ17 34 M_A_DQ18 DQS4# 245 M_A_DQS_DP4 42 VSS VSS 187 92 VDD
1D2V_SM_S3 CB3 DQ18 M_A_DQ19 DQS4 M_A_DQS_DN5 M_A_DQS_DP4 [5] VSS VSS VDD
47 179 255 M_A_DQS_DN5 [5] 44 189 204
192 CB4 DQ19 25 M_A_DQ20 DQS5# 256 M_A_DQS_DP5 46 VSS VSS 191 206 VDD
CB5 DQ20 M_A_DQ21 DQS5 M_A_DQS_DN6 M_A_DQS_DP5 [5] VSS VSS VDD
54 170 266 48 193 209
CB6 DQ21 M_A_DQ22 DQS6# M_A_DQS_DP6 M_A_DQS_DN6 [5] VSS VSS VDD
199 32 267 M_A_DQS_DP6 [5] 50 195 212
CB7 DQ22 177 M_A_DQ23 DQS6 277 M_A_DQS_DN7 53 VSS VSS 198 215 VDD
M_A_ODT0 DQ23 M_A_DQ24 DQS7# M_A_DQS_DP7 M_A_DQS_DN7 [5] VSS VSS VDD
[5] M_A_ODT0 87 38 278 M_A_DQS_DP7 [5] 55 200 217
M_A_ODT1 91 ODT0 DQ24 183 M_A_DQ25 DQS7 196 57 VSS VSS 202 220 VDD
[5] M_A_ODT1 ODT1 DQ25 M_A_DQ26 DQS8# VSS VSS VDD
45 197 94 239 223
M_A_CKE0 60 DQ26 190 M_A_DQ27 DQS8 8 96 VSS VSS 241 226 VDD
[5] M_A_CKE0 M_A_CKE1 CKE0 DQ27 M_A_DQ28 DQS9# VSS VSS VDD
203 36 7 98 243 229
[5] M_A_CKE1 CKE1 DQ28 M_A_DQ29 DQS9 VSS VSS VDD
181 19 101 246 231
M_A_CS#0 84 DQ29 43 M_A_DQ30 DQS10# 18 103 VSS VSS 248 233 VDD
[5] M_A_CS#0 M_A_CS#1 S0# DQ30 M_A_DQ31 DQS10 VSS VSS VDD
89 188 30 105 250 236
[5] M_A_CS#1 S1# DQ31 M_A_DQ32 DQS11# VSS VSS VDD
93 97 29 107 252
237 S2#_C0 DQ32 242 M_A_DQ33 DQS11 41 109 VSS VSS 254 77
S3#_C1 DQ33 M_A_DQ34 DQS12# VSS VSS 0D675V_VTT_S0 VTT
235 104 40 112 257 221
C2 DQ34 249 M_A_DQ35 DQS12 100 114 VSS VSS 259 VTT
M_A_CLK#0 75 DQ35 95 M_A_DQ36 DQS13# 99 116 VSS VSS 261 142
[5] M_A_CLK#0 M_A_CLK0 CK0# DQ36 M_A_DQ37 DQS13 VSS VSS VPP
[5] M_A_CLK0 74 240 111 118 263 143
M_A_CLK#1 219 CK0 DQ37 102 M_A_DQ38 DQS14# 110 120 VSS VSS 265 286 VPP
[5] M_A_CLK#1 M_A_CLK1 CK1# DQ38 M_A_DQ39 DQS14 VSS VSS VPP TP_DIMM1_PIN1
[5] M_A_CLK1 218 247 122 123 268 287 1
CK1 DQ39 108 M_A_DQ40 DQS15# 121 125 VSS VSS 270 288 VPP 12V 145
2D5V_VPP_S3

1
M_A_BG0 63 DQ40 253 M_A_DQ41 DQS15 133 127 VSS VSS 272 VPP 12V
[5] M_A_BG0 M_A_BG1 BG0 DQ41 M_A_DQ42 DQS16# VSS VSS
C [5] M_A_BG1 207 115 132 129 274 4/4 R1102 C
M_A_BS0 81 BG1 DQ42 260 M_A_DQ43 DQS16 52 131 VSS VSS 276 DIMM288_DDR4 0R2J-2-GP
[5] M_A_BS0 M_A_BS1 BA0 DQ43 M_A_DQ44 DQS17# VSS VSS
[5] M_A_BS1 224 106 51 1D2V_SM_S3 134 279 (R_)
BA1 DQ44 251 M_A_DQ45 DQS17 136 VSS VSS 281
4 OF 4

2
M_A_A0 79 DQ45 113 M_A_DQ46 2/4 138 VSS VSS 283 DDR4-288P-82-GP TP_DIMM1_PIN145
[5] M_A_A0 M_A_A1 A0 DQ46 M_A_DQ47 VSS VSS
[5] M_A_A1 72 258 DIMM288_DDR4
(022.10010.0A61)
M_A_A2 216 A1 DQ47 119 M_A_DQ48 3/4
[5] M_A_A2 M_A_A3 A2 DQ48 M_A_DQ49 2 OF 4
[5] M_A_A3 71 264 DIMM288_DDR4
M_A_A4 214 A3 DQ49 126 M_A_DQ50 DDR4-288P-82-GP
[5] M_A_A4 M_A_A5 A4 DQ50 M_A_DQ51 3 OF 4
213 271 (022.10010.0A61) DDR4-288P-82-GP
[5] M_A_A5 M_A_A6 A5 DQ51 M_A_DQ52
[5] M_A_A6 69 117 (022.10010.0A61)
M_A_A7 211 A6 DQ52 262 M_A_DQ53
[5] M_A_A7 M_A_A8 A7 DQ53 M_A_DQ54
[5] M_A_A8 68 124
M_A_A9 66 A8 DQ54 269 M_A_DQ55
[5] M_A_A9 M_A_A10 A9 DQ55 M_A_DQ56
225 130
[5] M_A_A10 M_A_A11 A10 DQ56 M_A_DQ57
[5] M_A_A11 210 275
M_A_A12 65 A11 DQ57 137 M_A_DQ58
[5] M_A_A12 M_A_A13 A12 DQ58 M_A_DQ59
[5] M_A_A13 232 282
M_A_A14 228 A13 DQ59 128 M_A_DQ60
[5] M_A_A14 M_A_A15 A14_WE# DQ60 M_A_DQ61
86 273
[5] M_A_A15 M_A_A16 A15_CAS# DQ61 M_A_DQ62
[5] M_A_A16 82 135
234 A16_RAS# DQ62 280 M_A_DQ63
A17 DQ63
1/4 3D3V_S0 1D2V_SM_S3
DIMM288_DDR4 1D2V_SM_S3
1 OF 4
DDR4-288P-82-GP
(022.10010.0A61)

1
TC1101 C1109 C1110
E820U2D5VM-6-GP SCD1U16V2KX-3DLGP SC2D2U6D3V2MX-DL-GP C1101 C1102
(R_) SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

2
B DIMM VREF DQ A (To DIMM/CPU) B

2D5V_VPP_S3

1
C1103 C1104
Del for DDR4 Modify Del C82, C83 SCD1U16V2KX-L-GP SCD1U16V2KX-L-GP
(R_) (R_)

2
For DDR4 Modify

1D2V_SM_S3

DIMM VREF CA A (To DIMM)


1

1D2V_SM_S3
1

R1103
1KR2F-3-GP C1105

1
SCD1U16V2KX-3DLGP
2

R1104
2

470R2J-2-GP

R1105 0R0402-PAD-2-GP
2

DIMM_CA_VREF_A 1 2 DIMM_CA_VREF_A_L SM_DRAMRST#


[6] DIMM_CA_VREF_A
1

R1106 C1107 C1108


1KR2F-3-GP C1106 SC4D7U6D3V3KX-DLGP SCD1U16V2KX-L-GP
A SCD1U16V2KX-3DLGP (R_) A
2

20170410
2

change to 47U for Edison's and Alan's feedback


20170412
correct the capacitance to 4D7U for Alan's feedback

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR DIMM_1
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 11 of 107
5 4 3 2 1
5 4 3 2 1

DIMM2:
SA0: 0, SA1: 1 DIMM2A
205
Write Address: 0xA4 227 RFU#205 NP3
Read Address: 0xA5 230 RFU#227 NP3 NP2
144 RFU#230 NP2 NP1

Vinafix.com
RFU#144 NP1
DIMM_CA_VREF_B_L M_B_DQ0 M_B_DQ[0..63] [6]
146 5 DIMM2C
VREFCA DQ0 150 M_B_DQ1 2 147
141 DQ1 12 M_B_DQ2 4 VSS VSS 149
[11,24,59] SMB_CLK_MAIN SCL DQ2 M_B_DQ3 VSS VSS
[11,24,59] SMB_DATA_MAIN 285 157 6 151
D
139 SDA DQ3 3 M_B_DQ4 DIMM2B 9 VSS VSS 154 D
140 SA0 DQ4 148 M_B_DQ5 11 VSS VSS 156 DIMM2D
238 SA1 DQ5 10 M_B_DQ6 152 M_B_DQS_DN0 13 VSS VSS 158 59
SA2 DQ6 M_B_DQ7 DQS0# M_B_DQS_DP0 M_B_DQS_DN0 [6] VSS VSS 1D2V_SM_S3 VDD
284 155 153 15 160 61
3D3V_S0 VDDSPD DQ7 M_B_DQ8 DQS0 M_B_DQS_DN1 M_B_DQS_DP0 [6] VSS VSS VDD
16 163 M_B_DQS_DN1 [6] 17 162 64
M_B_ACT# 62 DQ8 161 M_B_DQ9 DQS1# 164 M_B_DQS_DP1 20 VSS VSS 165 67 VDD
[6] M_B_ACT# M_B_ALERT# ACT# DQ9 M_B_DQ10 DQS1 M_B_DQS_DN2 M_B_DQS_DP1 [6] VSS VSS VDD
208 23 174 22 167 70
[6] M_B_ALERT# DIMM2_EVENT_N ALERT# DQ10 M_B_DQ11 DQS2# M_B_DQS_DP2 M_B_DQS_DN2 [6] VSS VSS VDD
78 168 175 M_B_DQS_DP2 [6] 24 169 73
SM_DRAMRST# 58 EVENT# DQ11 14 M_B_DQ12 DQS2 185 M_B_DQS_DN3 26 VSS VSS 171 76 VDD
[11,20] SM_DRAMRST# M_B_PARITY RESET# DQ12 M_B_DQ13 DQS3# M_B_DQS_DP3 M_B_DQS_DN3 [6] VSS VSS VDD
[6] M_B_PARITY 222 159 186 M_B_DQS_DP3 [6] 28 173 80
PAR DQ13 21 M_B_DQ14 DQS3 244 M_B_DQS_DN4 31 VSS VSS 176 83 VDD
DQ14 M_B_DQ15 DQS4# M_B_DQS_DP4 M_B_DQS_DN4 [6] VSS VSS VDD
49 166 245 33 178 85
CB0 DQ15 M_B_DQ16 DQS4 M_B_DQS_DN5 M_B_DQS_DP4 [6] VSS VSS VDD
194 27 255 M_B_DQS_DN5 [6] 35 180 88
R1201 240R2F-1-GP 56 CB1 DQ16 172 M_B_DQ17 DQS5# 256 M_B_DQS_DP5 37 VSS VSS 182 90 VDD
CB2 DQ17 DQS5 M_B_DQS_DP5 [6] VSS VSS VDD
1D2V_SM_S3 1 2 DIMM2_EVENT_N 201 34 M_B_DQ18 266 M_B_DQS_DN6
M_B_DQS_DN6 [6] 39 184 92
47 CB3 DQ18 179 M_B_DQ19 DQS6# 267 M_B_DQS_DP6 42 VSS VSS 187 204 VDD
CB4 DQ19 M_B_DQ20 DQS6 M_B_DQS_DN7 M_B_DQS_DP6 [6] VSS VSS VDD
192 25 277 44 189 206
CB5 DQ20 M_B_DQ21 DQS7# M_B_DQS_DP7 M_B_DQS_DN7 [6] VSS VSS VDD
54 170 278 M_B_DQS_DP7 [6] 46 191 209
199 CB6 DQ21 32 M_B_DQ22 DQS7 196 48 VSS VSS 193 212 VDD
CB7 DQ22 177 M_B_DQ23 DQS8# 197 50 VSS VSS 195 215 VDD
M_B_ODT0 87 DQ23 38 M_B_DQ24 DQS8 8 53 VSS VSS 198 217 VDD
[6] M_B_ODT0 M_B_ODT1 ODT0 DQ24 M_B_DQ25 DQS9# VSS VSS VDD
91 183 7 55 200 220
[6] M_B_ODT1 ODT1 DQ25 M_B_DQ26 DQS9 VSS VSS VDD
45 19 57 202 223
M_B_CKE0 60 DQ26 190 M_B_DQ27 DQS10# 18 94 VSS VSS 239 226 VDD
[6] M_B_CKE0 M_B_CKE1 CKE0 DQ27 M_B_DQ28 DQS10 VSS VSS VDD
[6] M_B_CKE1 203 36 30 96 241 229
CKE1 DQ28 181 M_B_DQ29 DQS11# 29 98 VSS VSS 243 231 VDD
M_B_CS#0 84 DQ29 43 M_B_DQ30 DQS11 41 101 VSS VSS 246 233 VDD
[6] M_B_CS#0 M_B_CS#1 S0# DQ30 M_B_DQ31 DQS12# VSS VSS VDD
[6] M_B_CS#1 89 188 40 103 248 236
93 S1# DQ31 97 M_B_DQ32 DQS12 100 105 VSS VSS 250 VDD
237 S2#_C0 DQ32 242 M_B_DQ33 DQS13# 99 107 VSS VSS 252 77
S3#_C1 DQ33 M_B_DQ34 DQS13 VSS VSS 0D675V_VTT_S0 VTT
235 104 111 109 254 221
C2 DQ34 249 M_B_DQ35 DQS14# 110 112 VSS VSS 257 VTT
M_B_CLK#0 75 DQ35 95 M_B_DQ36 DQS14 122 114 VSS VSS 259 142
[6] M_B_CLK#0 M_B_CLK0 CK0# DQ36 M_B_DQ37 DQS15# VSS VSS VPP
74 240 121 116 261 143
[6] M_B_CLK0 M_B_CLK#1 CK0 DQ37 M_B_DQ38 DQS15 VSS VSS VPP
[6] M_B_CLK#1 219 102 133 118 263 286
M_B_CLK1 218 CK1# DQ38 247 M_B_DQ39 DQS16# 132 120 VSS VSS 265 287 VPP 1 TP_DIMM2_PIN1
[6] M_B_CLK1 CK1 DQ39 M_B_DQ40 DQS16 VSS VSS VPP 12V
108 52 123 268 288 145
DQ40 DQS17# VSS VSS 2D5V_VPP_S3 VPP 12V

1
C M_B_BG0 63 253 M_B_DQ41 51 125 270 C
[6] M_B_BG0 M_B_BG1 BG0 DQ41 M_B_DQ42 DQS17 1D2V_SM_S3 VSS VSS
207 115 127 272 4/4 R1202
[6] M_B_BG1 M_B_BS0 BG1 DQ42 M_B_DQ43 VSS VSS
[6] M_B_BS0 81 260 2/4 129 274 DIMM288_DDR4 0R2J-2-GP
M_B_BS1 224 BA0 DQ43 106 M_B_DQ44 DIMM288_DDR4 131 VSS VSS 276 (R_)
[6] M_B_BS1 BA1 DQ44 M_B_DQ45 VSS VSS 4 OF 4
251 134 279

2
M_B_A0 79 DQ45 113 M_B_DQ46 2 OF 4
136 VSS VSS 281 DDR4-288P-82-GP TP_DIMM2_PIN145
[6] M_B_A0 M_B_A1 A0 DQ46 M_B_DQ47 VSS VSS
72 258 DDR4-288P-82-GP 138 283 (022.10010.0A61)
[6] M_B_A1 M_B_A2 A1 DQ47 M_B_DQ48 VSS VSS
[6] M_B_A2 216 119 (022.10010.0A61)
M_B_A3 71 A2 DQ48 264 M_B_DQ49 3/4
[6] M_B_A3 M_B_A4 A3 DQ49 M_B_DQ50
214 126 DIMM288_DDR4
[6] M_B_A4 M_B_A5 A4 DQ50 M_B_DQ51
[6] M_B_A5 213 271
M_B_A6 69 A5 DQ51 117 M_B_DQ52 DDR4-288P-82-GP
3 OF 4
[6] M_B_A6 M_B_A7 A6 DQ52 M_B_DQ53
[6] M_B_A7 211 262 (022.10010.0A61)
M_B_A8 68 A7 DQ53 124 M_B_DQ54
[6] M_B_A8 M_B_A9 A8 DQ54 M_B_DQ55
66 269
[6] M_B_A9 M_B_A10 A9 DQ55 M_B_DQ56
[6] M_B_A10 225 130
M_B_A11 210 A10 DQ56 275 M_B_DQ57
[6] M_B_A11 M_B_A12 A11 DQ57 M_B_DQ58
[6] M_B_A12 65 137
M_B_A13 232 A12 DQ58 282 M_B_DQ59
[6] M_B_A13 M_B_A14 A13 DQ59 M_B_DQ60
228 128
[6] M_B_A14 M_B_A15 A14_WE# DQ60 M_B_DQ61
[6] M_B_A15 86 273
M_B_A16 82 A15_CAS# DQ61 135 M_B_DQ62
[6] M_B_A16 A16_RAS# DQ62 M_B_DQ63
234 280
A17 DQ63
1/4
DIMM288_DDR4

1 OF 4
DDR4-288P-82-GP
(022.10010.0A61)
1D2V_SM_S3 3D3V_S0

1
C1203 C1212 C1213
DIMM VREF DQ B (To DIMM/CPU) C1201 C1202 SC1U10V2KX-1DLGP SCD1U16V2KX-3DLGP SC2D2U6D3V2MX-DL-GP
SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

2
(R_)
B B

Del for DDR4 Modify


0D675V_VTT_S0 2D5V_VPP_S3 20170410
change to mounted for Edison's feedback

1
C1204 C1205 C1206 C1207
SC4D7U6D3V3KX-DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

2
For DDR4 Modify

1D2V_SM_S3
DIMM VREF CA B (To DIMM)
1

R1203
1KR2F-3-GP C1208
SCD1U16V2KX-3DLGP
2
2

R1204 2R2F-GP R1205 0R0402-PAD-2-GP


M_VREF_DQ_DIM1 1 2 DIMM_CA_VREF_B 1 2 DIMM_CA_VREF_B_L
[6] M_VREF_DQ_DIM1
1
1

A C1209 R1206 C1211 A


SCD022U16V2KX-3DLGP 1KR2F-3-GP C1210 SC4D7U6D3V3KX-DLGP
SCD1U16V2KX-3DLGP
2

20170410
2

DIMM_DQ_CPU_VREF_B_RC change to 47U for Edison's and Alan's feedback


20170412
1

correct the capacitance to 4D7U for Alan's feedback


R1207
24D9R2F-L-GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

Title
DDR DIMM_2
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 12 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

C C

B B

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title
Reserved
Size Document Number Rev
A Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 13 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

C C

B B

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title
Reserved
Size Document Number Rev
A Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 14 of 107
5 4 3 2 1
5 4 3 2 1

20170406
USB charger function is removed
net CHAR_EN @ pin Y47
net PCH_CHAR_CTL3 @ pin AA45 is removed

20170410

Vinafix.com PCH_PME_N BE36


SB1A
GPP_A11/PME#/SD_VDD2_PWR_EN#
1 OF 13
GPP_B13/PLTRST#
AV29 PLTRST#_PCH
R1504
1
33R2J-2-GP
2 PLTRST#_SIO
add 33R series resistor for Edison's & Alan's feedback

PLTRST#_SIO [24]
R15
D
R13 RSVD2 Y47 D
RSVD1 GPP_K16/GSXCLK Y46 3D3V_SB
GPP_K12/GSXDOUT Y48 VGA_CABLE_DET_N
GPP_K13/GSXSLOAD VGA_CABLE_DET_N [59]
W46 20170512
TP1501 1 TP_VSS_AL37 AL37 GPP_K14/GSXDIN AA45 Remove R1501
AN35 VSS GPP_K15/GSXSRESET#
TP R1502 10KR2J-3-GP
SPI_SI_PCH AU41 AL47 WAKE_M2_SSD_N VGA_CABLE_DET_N 1 2
[23,25,91,99] SPI_SI_PCH SPI_SO_PCH SPI0_MOSI GPP_E3/CPU_GP0 WAKE_M2_SSD_N [62]
BA45 AM45
[23,25,91] SPI_SO_PCH SPI_CS_PCH_N0 SPI0_MISO GPP_E7/CPU_GP1 ME_CNTL
[25] SPI_CS_PCH_N0 AY47 BF32 ME_CNTL [20]
20170512
SPI_CLK_PCH AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 Remove TP1502 R1503
8K2R2F-1-GP
[25,91] SPI_CLK_PCH SPI0_CLK GPP_B4/CPU_GP3 WAKE_M2_SSD_N
AW48 1 2
20170406 SPI0_CS1# AE44 20170512 20170418
change to single 32MB SPI ROM SPI_WP_PCH AY48 GPP_H18/SML4ALERT# AJ46 Remove TP1503 mount R57 8K2R to follow D9 Bison
remove SPI_CS_PCH_N2 [23,25] SPI_WP_PCH SPI_HOLD_PCH SPI0_IO2 GPP_H17/SML4DATA
[23,25] SPI_HOLD_PCH BA46 AE43
change SPI_CD_PCH_N1 to TPM SPI_CS_PCH_N2 AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H_15
[91] SPI_CS_PCH_N2 SPI0_CS2# GPP_H15/SML3ALERT# GPP_H_15 [23]
BE19 AD48
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H14/SML3DATA AF47
BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H13/SML3CLK AB47 GPP_H_12 1 TP1506 (R_)
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H12/SML2ALERT# AD47 3P0V_BAT_VREG SPI_CLK_PCH R1515 1 2 100KR2J-1-GP
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H11/SML2DATA AE48 R1507 1MR2J-1-GP
BD17 GPP_D22/SPI1_IO3 GPP_H10/SML2CLK BB44 PCH_INTRUDER_N 1 2
GPP_D21/SPI1_IO2 INTRUDER# PLTRST#_SIO R1516 1 (R_) 2 100KR2J-1-GP
CANON-LAKE-GP
(071.CANNO.0B0U)

20170423 SB1K 11 OF 13
Remove R1505 TP1507 1 LPSS_GSPI1_MOSI BA26 BA20
3D3V_S0 BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20
AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16
AW26 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18
TP1508 1 LPSS_GSPI0_MOSI BE30 GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
BD29 GPP_B18/GSPI0_MOSI BF14
C C
R1506 10KR2J-3-GP BF29 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
1 2 PCIE_SLOT1_PRSNT_N PCIE_SLOT1_PRSNT_N BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17
[94] PCIE_SLOT1_PRSNT_N GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
TP1504 1 UART0_TX BB24 GPP_D13/ISH_UART0_RXD/I2C2_SDA
TP1505 1 UART0_RX BE23 GPP_C9/UART0_TXD
AP24 GPP_C8/UART0_RXD
FP_CBL_DET BA24 GPP_C11/UART0_CTS#
[64] FP_CBL_DET GPP_C10/UART0_RTS#
BD21 AG45
AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL AH46
AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD AH47
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL AH48
LPC_PME_N AV21 GPP_H21/ISH_I2C1_SDA
[24] LPC_PME_N GPP_C23/UART2_CTS#
AW21
BE20 GPP_C22/UART2_RTS#
BD20 GPP_C21/UART2_TXD AV34
GPP_C20/UART2_RXD GPP_A23/ISH_GP5 AW32
BE21 GPP_A22/ISH_GP4 BA33
BF21 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 BE34
BC22 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 BD34 FORM_FAC_ID_2
GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 FORM_FAC_ID_1 FORM_FAC_ID_2 [64]
BF23 BF35
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 FORM_FAC_ID_0 FORM_FAC_ID_1 [64]
BD38
BE15 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 FORM_FAC_ID_0 [64]
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CANON-LAKE-GP
(071.CANNO.0B0U)

20170413
3D3V_SB change to on board power switch SB1M 13 OF 13
R1508 8K2R2F-1-GP remove the net FP_CBL_DET @ pin BF8 BD4 CNV_WR_CLK_DN
20170420 CNV_WR_CLKN CNV_WR_CLK_DN [63]
1 2 PCH_PME_N AW13 BE3 CNV_WR_CLK_DP
CNV_WR_CLK_DP [63]
B add the net FP_CBL_DET back for SFF GPP_G0/SD_CMD CNV_WR_CLKP B
BE9
BF8 GPP_G1/SD_D0 BB3 CNV_WR_0_DN
GPP_G2/SD_D1 CNV_WR_D0N CNV_WR_0_DP CNV_WR_0_DN [63]
R1509 10KR2J-3-GP BF9 BB4 CNV_WR_0_DP [63]
1 2 H_SKTOCC_N BG8 GPP_G3/SD_D2 CNV_WR_D0P BA3 CNV_WR_1_DN
GPP_G4/SD_D3 CNV_WR_D1N CNV_WR_1_DP CNV_WR_1_DN [63]
BE8 BA2 CNV_WR_1_DP [63]
BD8 GPP_G5/SD_CD# CNV_WR_D1P
R1510 10KR2J-3-GP 20170413 AV13 GPP_G6/SD_CLK BC5 CNV_WT_CLK_DN
GPP_G7/SD_WP CNV_WT_CLKN CNV_WT_CLK_DN [63]
1 2 FP_CBL_DET change to on board power switch BB6 CNV_WT_CLK_DP
CNV_WT_CLK_DP [63]
remove the net FP_CBL_DET @ pin BF8 H_SKTOCC_N AP3 CNV_WT_CLKP
20170420 [24] H_SKTOCC_N GPP_I11/M2_SKT2_CFG0 CNV_WT_0_DN
AP2 BE6 CNV_WT_0_DN [63]
add the net FP_CBL_DET back for SFF GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N CNV_WT_0_DP
R1511 47KR2J-2-GP AN4 BD7
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P CNV_WT_0_DP [63]
1 2 GPP_J1 AM7 BG6 CNV_WT_1_DN
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N CNV_WT_1_DP CNV_WT_1_DN [63]
BF6 CNV_WT_1_DP [63]
AV6 CNV_WT_D1P BA1 CNV_WT_RCOMP
GPP_J1 AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP
AR13 GPP_J1/CPU_VCCIO_PWR_GATE# B12 PCIE_RCOMP_N
AV7 GPP_J11/A4WP_PRESENT PCIE_RCOMPN A13 PCIE_RCOMP_P
[23] CNV_BRI_DT GPP_J10 PCIE_RCOMPP
AW3 BE5
AT10 GPP_J_2 SD_RCOMP_1P8 BE4
R9932 1 2 33R2J-2-GP CNV_BRI_DT AV4 GPP_J_3 SD_RCOMP_3P3 BD1
[63] CNV_BRI_DT_R CNV_BRI_RSP GPP_J_4_CNV_BRI_DT_UART0_RTSB GPPJ_RCOMP_1P81
R9933 1 2 22R2J-2-GP AY2 BE1
[63] CNV_BRI_RSP_R CNV_RGI_DT GPP_J5/CNV_BRI_RSP/UART0_RXD GPPJ_RCOMP_1P82 SD_RCOMP
R9934 1 2 33R2J-2-GP BA4 BE2 R1512 150R2F-1-GP
[63] CNV_RGI_DT_R CNV_RGI_RSP GPP_J6/CNV_RGI_DT/UART0_TXD GPPJ_RCOMP_1P83 CNV_WT_RCOMP
[63] CNV_RGI_RSP_R R9935 1 2 22R2J-2-GP AV3 1 2
AW2 GPP_J7/CNV_RGI_RSP/UART0_CTS# Y35
AU9 GPP_J8/CNV_MFUART2_RXD RSVD2 Y36
GPP_J9/CNV_MFUART2_TXD RSVD3 R1513 100R2F-L1-GP-U
[23] CNV_RGI_DT BC1_TP 1 PCIE_RCOMP_N
BC1 TP1509 1 2 PCIE_RCOMP_P
RSVD1 AL35
TP
R1514 200R2F-L-GP
CANON-LAKE-GP SD_RCOMP 1 2
(071.CANNO.0B0U)

R9937 20KR2F-L-GP
A 1D8V_SB 1 2 CNV_RGI_RSP A

R9936 20KR2F-L-GP
1 2 CNV_BRI_RSP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(SPI/UART/I2C )
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 15 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

SB1B 2 OF 13
DMI_TX_CPU_N3 K34 J3 USB_PCH_PN1
[3] DMI_TX_CPU_N3 DMI_TX_CPU_P3 DMI0_RXN USB2N_1 USB_PCH_PP1 USB_PCH_PN1 [38]
J35 J2 Front USB3.0
[3] DMI_TX_CPU_P3 DMI_RX_CPU_N3 DMI0_RXP USB2P_1 USB_PCH_PN2 USB_PCH_PP1 [38]
C33 N13
[3] DMI_RX_CPU_N3 DMI_RX_CPU_P3 B33 DMI0_TXN USB2N_2 N15 USB_PCH_PP2 USB_PCH_PN2 [38] Front USB3.0
[3] DMI_RX_CPU_P3 DMI_TX_CPU_N2 DMI0_TXP USB2P_2 USB_PCH_PP2 [38]
G33 K4 20170516
[3] DMI_TX_CPU_N2 DMI_TX_CPU_P2 F34 DMI1_RXN USB2N_3 K3 Remove USB Port3 20170406
[3] DMI_TX_CPU_P2 DMI_RX_CPU_N2 DMI1_RXP USB2P_3 change net name from USB_OC7_R_N to GPIO_PCI_RESET
C32 M10
[3] DMI_RX_CPU_N2 DMI_RX_CPU_P2 B32 DMI1_TXN USB2N_4 L9 to control PLTRST_N of device and slot
[3] DMI_RX_CPU_P2 DMI_TX_CPU_N1 K32 DMI1_TXP USB2P_4 M1 USB_PCH_PN5
[3] DMI_TX_CPU_N1 DMI_TX_CPU_P1 DMI2_RXN USB2N_5 USB_PCH_PP5 USB_PCH_PN5 [32] 3D3V_S0
J32 L2 Rear USB2.0 w/ RJ-45
[3] DMI_TX_CPU_P1 DMI_RX_CPU_N1 C31 DMI2_RXP USB2P_5 K7 USB_PCH_PN6 USB_PCH_PP5 [32]
R1601 10KR2J-3-GP
[3] DMI_RX_CPU_N1 DMI_RX_CPU_P1 DMI2_TXN USB2N_6 USB_PCH_PP6 USB_PCH_PN6 [32] GPIO_PCI_RESET_N
B31 K6 Rear USB2.0 w/ RJ-45 1 2
[3] DMI_RX_CPU_P1 DMI_TX_CPU_N0 DMI2_TXP USB2P_6 USB_PCH_PN7 USB_PCH_PP6 [32]
G30 L4
[3] DMI_TX_CPU_N0 DMI_TX_CPU_P0 F30 DMI3_RXN USB2N_7 L3 USB_PCH_PP7 USB_PCH_PN7 [39] Rear USB2.0
[3] DMI_TX_CPU_P0 DMI_RX_CPU_N0 DMI3_RXP USB2P_7 USB_PCH_PN8 USB_PCH_PP7 [39]
C29 G4
[3] DMI_RX_CPU_N0 DMI_RX_CPU_P0 B29 DMI3_TXN USB2N_8 G5 USB_PCH_PP8 USB_PCH_PN8 [33] Card Reader
[3] DMI_RX_CPU_P0 DMI3_TXP USB2P_8 USB_PCH_PN9 USB_PCH_PP8 [33]
A25 M6
DMI7_TXP USB2N_9 USB_PCH_PP9 USB_PCH_PN9 [39]
B25 N8 Rear USB2.0
P24 DMI7_TXN USB2P_9 H3 USB_PCH_PP9 [39]
R24 DMI7_RXP USB2N_10 H2
C26 DMI7_RXN USB2P_10 R10
B26 DMI6_TXP USB2N_11 P9
F26 DMI6_TXN USB2P_11 G1 3D3V_SB
G26 DMI6_RXP USB2N_12 G2
B27 DMI6_RXN USB2P_12 N3
C C
C27 DMI5_TXP USB2N_13 N2
L26 DMI5_TXN USB2P_13 E5 USB_PCH_PN14 R1604 10KR2J-3-GP
DMI5_RXP USB2N_14 USB_PCH_PP14 USB_PCH_PN14 [63] USB_OC3_R_N
M26 F6 WLAN 20170515 1 2
D29 DMI5_RXN USB2P_14 USB_PCH_PP14 [63] Change to USB port 14 for WLAN BT function
E28 DMI4_TXP AH36 USB_OC0_R_N
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1_R_N USB_OC0_R_N [19,38]
R1605 10KR2J-3-GP
DMI4_RXP GPP_E10/USB2_OC1# USB_OC2_R_N USB_OC1_R_N [19,39] USB_OC2_R_N
M29 AJ44 1 2
DMI4_RXN GPP_E11/USB2_OC2# AL41 USB_OC3_R_N
G17 GPP_E12/USB2_OC3# AV47 USB_OC4_R_N USB_OC3_R_N [32]
F16 PCIE1_RXN/USB31_7_RXNGPP_F15/USB2_OC4# AR35 USB_OC5_R_N R1606 10KR2J-3-GP
A17 PCIE1_RXP/USB31_7_RXPGPP_F16/USB2_OC5# AR37 USB_OC6_R_N USB_OC5_R_N [19] 20170418 USB_OC6_R_N 1 2
B17 PCIE1_TXN/USB31_7_TXNGPP_F17/USB2_OC6# AV43 GPIO_PCI_RESET_N GPIO_PCI_RESET change net name to GPIO_PCI_RESET_N
R21 PCIE1_TXP/USB31_7_TXPGPP_F18/USB2_OC7#
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP R1607 10KR2J-3-GP
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE USB_OC4_R_N 1 2
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD7
PCIE3_TXN/USB31_9_TXN GPD7 GPD7 [23]
C19
N18 PCIE3_TXP/USB31_9_TXP G45
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46 R1609 113R2F-GP
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41 USB2_COMP 1 2
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
PCIE_RX_PCH_N5 F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
[31] PCIE_RX_PCH_N5 PCIE_RX_PCH_P5 G20 PCIE5_RXN PCIE23_TXP G49 20170421 R1610 10KR2J-3-GP
[31] PCIE_RX_PCH_P5 PCIE_TX_PCH_N5 PCIE5_RXP PCIE23_TXN Remove PCIE Signal USB2_VBUSSENSE
LAN B21 W44 1 2
[31] PCIE_TX_PCH_N5 PCIE_TX_PCH_P5 A22 PCIE5_TXN PCIE23_RXP W43
[31] PCIE_TX_PCH_P5 K21 PCIE5_TXP PCIE23_RXN H48
J21 PCIE6_RXN PCIE22_TXP H47
D21 PCIE6_RXP PCIE22_TXN U41 USB2_ID R1611 1 2 1KR2J-1-GP
C21 PCIE6_TXN PCIE22_RXP U40
PCIE_TX_PCH_P7 B23 PCIE6_TXP PCIE22_RXN F46
20170426 [94] PCIE_TX_PCH_P7 PCIE_TX_PCH_N7 C23 PCIE7_TXP PCIE21_TXP G47 20170698
Change to PCIE*1 Slot to port7 [94] PCIE_TX_PCH_N7 PCIE_RX_PCH_P7 PCIE7_TXN PCIE21_TXN R1611 Change to pull down 10kohm
PCIEx1 slot J24 R44
[94] PCIE_RX_PCH_P7 PCIE_RX_PCH_N7 L24 PCIE7_RXP PCIE21_RXP T43
[94] PCIE_RX_PCH_N7 PCIE_RX_PCH_N8 F24 PCIE7_RXN PCIE21_RXN
B [63] PCIE_RX_PCH_N8 PCIE_RX_PCH_P8 PCIE8_RXN B
G24
20170421 [63] PCIE_RX_PCH_P8 PCIE_TX_PCH_N8 B24 PCIE8_RXP
Remove PCIE8 PCIE Signal for PCI bridge IC WLAN [63] PCIE_TX_PCH_N8 PCIE_TX_PCH_P8 C24 PCIE8_TXN
20170426 [63] PCIE_TX_PCH_P8 PCIE8_TXP
Change to WLAN to port8 CANON-LAKE-GP
(071.CANNO.0B0U)

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(DMI/PCI-E/USB)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 16 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

V_CPU_ST_PLL
R1703 1KR2J-1-GP
THERMTRIP#_CPU 1 2

20170418
20170413 PW_CLEAR change from GPP_K9 to GPP_K10 to follow D9 Bison SB1C 3 OF 13
change to on board power switch PCH_RST_GPIO change from GPP_K10 to GPP_F23 to follow D9 Bison AR2 G36 20170406
remove the net CHASSIS_ID_0 @ pin L47 AT5 CL_CLK PCIE9_RXN F36 20170423 SATA LED add back to MB
20170420 R1701 AU4 CL_DATA PCIE9_RXP C34 Remove PCIEx1 slot port from PCIE9 TP_GPP_E8 change to PCH_SATA_LED_N 3D3V_S0
add the net CHASSIS_ID_0 back for SFF CL_RST# PCIE9_TXN
0R0402-PAD-2-GP D34 R1704 10KR2J-3-GP
DP_HPD_CPU 1 2 VGA1_DETECT P48 PCIE9_TXP PCH_SATA_LED_N 1 2
[19,59] DP_HPD_CPU GPP_K8
V47
PW_CLEAR V48 GPP_K9 K37
3D3V_SB [20] PW_CLEAR GPP_K10 PCIE10_RXN
W47 J37
R1712 10KR2J-3-GP GPP_K11 PCIE10_RXP C35 20170427
1 2 CHASSIS_ID_0 L47 PCIE10_TXN B35 Will add SATA2 Siganl Change to ODD Function
[64] CHASSIS_ID_0 L46 GPP_K0 PCIE10_TXP
NGFF_WIFI_PWR_CRL U48 GPP_K1 F44 SATA_RX_PCH_N2 R1706 10KR2J-3-GP
[63] NGFF_WIFI_PWR_CRL GPP_K3 GPP_K2 PCIE15_RXN/SATA2_RXN SATA_RX_PCH_P2 SATA_RX_PCH_N2 [60] VGA1_DETECT
U47 E45 1 2
[63] GPP_K3 GPP_K3 PCIE15_RXP/SATA2_RXP SATA_TX_PCH_N2 SATA_RX_PCH_P2 [60]
R1702 N48 B40 ODD
GPP_K5 GPP_K4 PCIE_15_SATA_2_TXN SATA_TX_PCH_P2 SATA_TX_PCH_N2 [60]
0R0402-PAD-2-GP N47 C40
HDMI_DET_CPU 1 2 HDMI1_DETECT P47 GPP_K5 PCIE15_TXP/SATA2_TXP SATA_TX_PCH_P2 [60]
[19,56] HDMI_DET_CPU GPP_K6 SATA_RX_PCH_N3
R46 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40 SATA_RX_PCH_P3 SATA_RX_PCH_N3 [60]
3D3V_SB PCIE16_RXP/SATA3_RXP SATA_TX_PCH_N3 SATA_RX_PCH_P3 [60]
C36 B41 HDD2
PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN SATA_TX_PCH_P3 SATA_TX_PCH_N3 [60]
B36 C41
F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP SATA_TX_PCH_P3 [60] 3D3V_SB
R1709 10KR2J-3-GP
1 2 G38 PCIE11_RXP/SATA0A_RXP K43 20170423 20170609
C C
PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 Will add SATA3 Siganl for SSD Function Follow CRB will R1705 change to 3D3V_SB
AR42 PCIE17_RXP/SATA4_RXP A42 20170427 R1705 10KR2J-3-GP
[63] WLAN_PEDET GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN Will add SATA3 Siganl Change to HDD2 Function SSD_PEDET
AR48 B42 1 2
AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP 20170421
AU46 GPP_F13/SATA_SDATAOUT0 P41 change to PCIE21, 22 to support Optane
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
SATA_TX_PCH_N1 C39 PCIE18_RXP/SATA5_RXP C42
20170427 [62] SATA_TX_PCH_N1 SATA_TX_PCH_P1 D39 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN D42
Change to SSD to SATA port1 SSD [62] SATA_TX_PCH_P1 SATA_RX_PCH_N1 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
[62] SATA_RX_PCH_N1 SATA_RX_PCH_P1 PCIE14_RXN/SATA1B_RXN PCH_SATA_LED_N
C47 AK48 PCH_SATA_LED_N [64]
[62] SATA_RX_PCH_P1 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# AH41 3D3V_S0
SATA_TX_PCH_N0 B38 GPP_E0/SATAXPCIE0/SATAGP0 AJ43 R1714 10KR2J-3-GP
[60] SATA_TX_PCH_N0 SATA_TX_PCH_P0 C38 PCIE13_TXN/SATA0B_TXN GPP_E1/SATAXPCIE1/SATAGP1 AK47 GPP_K5 1 2
HDD1 [60] SATA_TX_PCH_P0 SATA_RX_PCH_N0 C45 PCIE13_TXP/SATA0B_TXP GPP_E2/SATAXPCIE2/SATAGP2 AN47 (R_)
[60] SATA_RX_PCH_N0 SATA_RX_PCH_P0 PCIE13_RXN/SATA0B_RXN GPP_F0/SATAXPCIE3/SATAGP_3 SSD_PEDET
C46 AM46
[60] SATA_RX_PCH_P0 PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 AM43 SSD_PEDET [62]
R1713 10KR2J-3-GP
E37 GPP_F2/SATAXPCIE5/SATAGP5 AM47 1 2
D38 PCIE12_TXP/SATA1A_TXP GPP_F3/SATAXPCIE6/SATAGP6 AM48 (R_)
J41 PCIE12_TXN/SATA1A_TXN GPP_F4/SATAXPCIE7/SATAGP7
H42 PCIE12_RXP/SATA_1A_RXP AU48
B44 PCIE12_RXN/SATA1A_RXN GPP_F21/EDP_BKLTCTL AV46
A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 (R_)
R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN R1708
R35 PCIE20_RXP/SATA7_RXP AD3 THERMTRIP#_PCH R1710 1 2 619R2F-L1-GP THERMTRIP#_CPU 1KR2J-1-GP
PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI THERMTRIP#_CPU [4]
20170421 D43 AF2 1 2
change to PCIE23, 24 to support Optane C44 PCIE19_TXP/SATA6_TXP PECI AF3 PM_SYNC_PCH R1711 1 2 30R2J-1-GP PM_SYNC_CPU
N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5 PLTRST_CPU_N PM_SYNC_CPU [4]
PCIE19_RXP/SATA6_RXP PLTRST_CPU# PM_DOWN_PCH PLTRST_CPU_N [4,99]
M44 AE2
PCIE19_RXN/SATA6_RXN PM_DOWN PM_DOWN_PCH [4]
CANON-LAKE-GP
(071.CANNO.0B0U)

B B

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(PCI-E/SATA)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 17 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com R1801 10KR2J-3-GP


3D3V_S0

PEG_CLKREQ1_PCH# 1 2
D D
SB1G 7 OF 13
BE33
GPP_A16/CLKOUT_48 Y3 R1803 10KR2J-3-GP
PCH_CPU_NSSC_CLK_DP D7 CLKOUT_ITPXDP# Y4 PEG_CLKREQ2_PCH# 1 2
[4] PCH_CPU_NSSC_CLK_DP PCH_CPU_NSSC_CLK_DN CLKOUT_CPUNSSC_P CLKOUT_ITPXDP_P
[4] PCH_CPU_NSSC_CLK_DN C6
CLKOUT_CPUNSSC# B6 PCH_CPU_PCIBCLK_DN
PCH_CPU_BCLK_DP B8 CLKOUT_CPUPCIBCLK# A6 PCH_CPU_PCIBCLK_DP PCH_CPU_PCIBCLK_DN [4]
[4] PCH_CPU_BCLK_DP R1805 10KR2J-3-GP
PCH_CPU_BCLK_DN CLKOUT_CPUBCLK_PCLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_DP [4] PEG_CLKREQ3_PCH#
[4] PCH_CPU_BCLK_DN C8 1 2
CLKOUT_CPUBCLK# AJ6
3D3V_S0 XTAL_24M_PCH_OUT U9 CLKOUT_PCIE_N0 AJ7
R1806 10KR2J-3-GP XTAL_24M_PCH_IN U10 XTAL_OUT CLKOUT_PCIE_P0 R1807 10KR2J-3-GP
1 2 PCIE_SLOT2_PRSNT_N XTAL_IN AH9 PEG_CLK1_PCH# PEG_CLKREQ8_PCH# 1 2
XCLK_RBIAS CLKOUT_PCIE_N1 PEG_CLK1_PCH PEG_CLK1_PCH# [63]
R1802 1 2 60D4R2F-GP T3 AH10 WLAN
XCLK_BIASREF CLKOUT_PCIE_P1 PEG_CLK1_PCH [63]
PCH_RTCX1 BA49 AE14 PEG_CLK2_PCH#
PCH_RTCX2 RTCX1 CLKOUT_PCIE_N2 PEG_CLK2_PCH PEG_CLK2_PCH# [31]
20170406 BA48 AE15 LAN 20170414
PCI bridge IC has no CLKREQ# RTCX2 CLKOUT_PCIE_P2 PEG_CLK2_PCH [31] duplicate net and pull up
add a PD resistor BF31 AE6
20170518 PEG_CLKREQ1_PCH# BE31 GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_N3 AE7 20170423 R1809 10KR2J-3-GP
Remove R1808 for PEG_CLKREQ10_PCH# [63] PEG_CLKREQ1_PCH# PEG_CLKREQ2_PCH# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_P3 Remove CLKOUT_PCIE3 Signal for SSD PEG_CLKREQ9_PCH#
[31] PEG_CLKREQ2_PCH# AR32 1 2
PEG_CLKREQ3_PCH# BB30 GPP_B7/SRCCLKREQ2# AC2
PCIE_SLOT2_PRSNT_N BA30 GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_N4 AC3
[93] PCIE_SLOT2_PRSNT_N GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_P4
AN29 20170518
20170518 AE47 GPP_B10/SRCCLKREQ5# AB2 Remove R1810 for PEG_CLKREQ10_PCH#
remove the net L_BAR_CTRL AC48 GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_N5 AB3
PEG_CLKREQ8_PCH# AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_P5
[93] PEG_CLKREQ8_PCH# PEG_CLKREQ9_PCH# GPP_H2/SRCCLKREQ8#
AF48 W4
[94] PEG_CLKREQ9_PCH# GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_N6
AC41 W3
20170518 AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_P6
Remove PEG_CLKREQ10_PCH# Signal for PCI Slot AE39 GPP_H5/SRCCLKREQ11# W7 20170423
AB48 GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_N7 W6 Remove R1811 for PCIE Slot
20170423 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_P7
Remove PEG_CLKREQ11_PCH# Signal for PCIE Slot AC43 GPP_H8/SRCCLKREQ14# AC14 PEG_CLK8_PCH#
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_N8 AC15 PEG_CLK8_PCH PEG_CLK8_PCH# [93] PCIEx16
CLKOUT_PCIE_P8 PEG_CLK8_PCH [93]
V2
V3 CLKOUT_PCIE_N15 U2 PEG_CLK9_PCH#
CLKOUT_PCIE_P15 CLKOUT_PCIE_N9 U3 PEG_CLK9_PCH PEG_CLK9_PCH# [94] PCIEx1
CLKOUT_PCIE_P9 PEG_CLK9_PCH [94]
C T2 C
T1 CLKOUT_PCIE_N14 AC9
CLKOUT_PCIE_P14 CLKOUT_PCIE_N10 AC11 20170421
AA1 CLKOUT_PCIE_P10 Remove PEG_CLK10 Signal for PCI bridge IC
Y2 CLKOUT_PCIE_N13 AE9
CLKOUT_PCIE_P13 CLKOUT_PCIE_N11 AE11 20170423
AC7 CLKOUT_PCIE_P11 Remove PEG_CLK11 Signal for PCIE Slot
AC6 CLKOUT_PCIE_N12 R6 TP_CLKIN_XTAL R1816 1 2 0R0402-PAD-2-GP PULSAR_38D4M_REFCLK
CLKOUT_PCIE_P12 CLKIN_XTAL PULSAR_38D4M_REFCLK [63]
CANON-LAKE-GP 20170504
add 38.4Mhz refclk from wifi card
(071.CANNO.0B0U) 20170607
Remove R1817 & R1815
R1816 change to unmount

CLOCK BUFF

R1818 1 2 0R0402-PAD-2-GP SUSCLK_SIO


SUSCLK_SIO [24]
[20] SUSCLK SUSCLK

R1822 1 2 0R0402-PAD-2-GP SUSCLK_WIFI


SUSCLK_WIFI [63]

B B

20170508
add to follow D9
20170627
Remove Clock Buff circuit

5/12 P/N is 082.30006.0531


20170607
change to common part follow d9 NOTE:The 200kohm Damping Resistor
PCH_RTCX1
XTAL_24M_PCH_IN

R1814 1 2 PCH_RTCX2 follow CRB R1812 1 2 200KR2F-L-GP XTAL_24M_PCH_OUT


10MR3J-L1-GP
X1801

4 1

X1802
1 2
A 3 2 A
1

XTAL-32D768KHZ-88-GP
C1803 C1804 C1802 C1801
SC15P50V2JN-DL-GP SC15P50V2JN-DL-GP SC15P50V2JN-DL-GP SC15P50V2JN-DL-GP
2

XTAL-24MHZ-182-GP
9/5 CL change to 15P for vendor Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

follow PDG Title


9/5 CL change to 15P for vendor
Frequecy: 32.768KHz PCH_(CLOCK/CL)
ESR: 50kohm follow PDG
Frequecy: 24MHz Size Document Number Rev
CL: 12pF
Series Resistance :< 30ohm MAX C Gambits MLK SFF A00
CL: 12pF Date: Friday, February 02, 2018 Sheet 18 of 107
5 4 3 2 1
5 4 3 2 1

3D3V_SB

R1917 10KR2J-3-GP
PIRQA_N 1 2
20170609
ADD R1917 & R1918 for TPM PIRQA_N singal

Vinafix.com 20170418
PCH_RST_GPIO change from GPP_K10 to GPP_F23
change net name to PCIVAUX_CTRL
to follow D9 Bison
WLAN_USB_DET
20170418
R1901
1
8K2R2F-1-GP
2

change from 2K2R to 8K2R to follow D9 Bison


SB1E 5 OF 13 R1902 10KR2J-3-GP
D HDMI_CLK_CPU GPP_A7 D
AL13 1 2
HDMI_DET_CPU AT6 GPP_I5/DDPB_CTRLCLK AR8 HDMI_DATA_CPU HDMI_CLK_CPU [56] 20170418
[17,56] HDMI_DET_CPU GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I6/DDPB_CTRLDATA DDPC_CTRL_CLK HDMI_DATA_CPU [23,56] mount R102 10KR to follow D9 Bison
AN10 AN13
AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I7/DDPC_CTRLCLK AL10 DDPC_CTRL_DATA
DP_HPD_CPU GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I8/DDPC_CTRLDATA DDPD_CTRL_CLK DDPC_CTRL_DATA [23]
[17,59] DP_HPD_CPU AL15 AL9
GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I9/DDPD_CTRLCLK AR3 DDPD_CTRL_DATA 20170609
GPP_I10/DDPD_CTRLDATA AN40 PCIVAUX_CTRL DDPD_CTRL_DATA [23] Remove R1903 and PEG_SLOT_PWR_EN
GPP_F23/DDPF_CTRLDATA AT49 GPIO_PEG_RESET_N
GPP_F22/DDPF_CTRLCLK
AP41 PCH_PS_ON_N
AN6 GPP_F14/EXT_PWR_GATE#/PS_ON# 20170418
GPP_I4/EDP_HPD/DISP_MISC4 M45 GPIO_LAN_RESET_N GPIO_LAN_RESET change from GPP_F23 to GPP_K23
GPP_K23/IMGCLKOUT1 L48 change net name to GPIO_LAN_RESET_N PIRQA_N R1918 1 (R_) 2 10KR2J-3-GP
GPP_K22/IMGCLKOUT0 T45 PIRQA_N GPIO_PEG_RESET change net name to GPIO_PEG_RESET_N
GPP_K21 PIRQA_N [91] PCIVAUX_CTRL
T46 20170609 R1905 1 (R_) 2 10KR2J-3-GP
GPP_K20 AJ47 ADD R1917 & R1918 for TPM PIRQA_N singal PCH_PS_ON_N R1919 1 (R_) 2 10KR2J-3-GP
GPP_H23/TIME_SYNC0 20170615
CANON-LAKE-GP ADD R1919 foe PCH_PS_ON_N
3D3V_S0
(071.CANNO.0B0U)
R1906 2K2R2J-2-GP
DDPC_CTRL_CLK 1 2
(R_)

R1907 2K2R2J-2-GP
DDPD_CTRL_CLK 1 2
(R_)

R1908 2K2R2J-2-GP
HDMI_CLK_CPU 1 2

20170509
Remove R1909

R1910 10KR2J-3-GP
LPC_SERIRQ_PCH 1 2
C C

R1911 10KR2J-3-GP
GPIO_PEG_RESET_N 1 2
SB1F 6 OF 13
USB30_TX_PCH_N1 F9 BB39 LPC_AD_PCH_P0 20170406
[38] USB30_TX_PCH_N1 USB30_TX_PCH_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD_PCH_P1 LPC_AD_PCH_P0 [24,68] add to control PLTRST_N of device and slot
F7 AW37 R1912 10KR2J-3-GP
[38] USB30_TX_PCH_P1 USB30_RX_PCH_N1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD_PCH_P2 LPC_AD_PCH_P1 [24,68] GPIO_LAN_RESET_N
[38] USB30_RX_PCH_N1 D11 AV37 1 2
USB30_RX_PCH_P1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD_PCH_P3 LPC_AD_PCH_P2 [24,68]
C11 BA38
[38] USB30_RX_PCH_P1 USB30_TX_PCH_N2 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD_PCH_P3 [24,68]
C3
[38] USB30_TX_PCH_N2 USB30_TX_PCH_P2 USB31_2_TXN
[38] USB30_TX_PCH_P2 D4 R1913 33R2J-2-GP
USB30_RX_PCH_N2 B9 USB31_2_TXP BE38 LPC_FRAME#_PCH_R LPC_FRAME#_PCH_R 1 2 LPC_FRAME#_PCH
[38] USB30_RX_PCH_N2 USB30_RX_PCH_P2 USB31_2_RXN GPP_A5/LFRAME#/ESPI_CS0# LPC_SERIRQ_PCH LPC_FRAME#_PCH [24,68]
[38] USB30_RX_PCH_P2 C9 AW35 LPC_SERIRQ_PCH [24,68]
USB31_2_RXP GPP_A6/SERIRQ/ESPI_CS1# BA36 GPP_A7
C17 GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KBRST_N R1914 22R2J-2-GP
USB31_6_TXN GPP_A0/RCIN#/ESPI_ALERT1# KBRST_N [24]
C16 BF38 1 2 LPC_CLK_14M_EC
G14 USB31_6_TXP GPP_A14/SUS_STAT#/ESPI_RESET# LPC_CLK_14M_EC [24]
F14 USB31_6_RXN BB36 LPC_CLK_PCH_P0
C15 USB31_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK BB34 LPC_CLK_PCH_P1 R1915 22R2J-2-GP
B15 USB31_5_TXN GPP_A10/CLKOUT_LPC1 LPC_CLK_PCH_P0 1 2 LPC_CLK_14M_DEBUG
J13 USB31_5_TXP T48 LPC_CLK_14M_DEBUG [68]
K13 USB31_5_RXN GPP_K19/SMI# T47
USB31_5_RXP GPP_K18/NMI# R1916 22R2J-2-GP
G12 LPC_CLK_PCH_P1 1 2 LPC_CLK_33M_EC
F11 USB31_3_TXP AH40 LPC_CLK_33M_EC [24]
C10 USB31_3_TXN GPP_E6/SATA_DEVSLP2 AH35 DEVSLP_N
USB31_3_RXP GPP_E5/SATA_DEVSLP1 DEVSLP_N [62]
B10 AL48
USB31_3_RXN GPP_E4/SATA_DEVSLP0 AP47
C14 GPP_F9/SATA_DEVSLP7 AN37 PCH_HEATSINK_DET
B14 USB31_4_TXP GPP_F8/SATA_DEVSLP6 AN46 3D3V_SB
J15 USB31_4_TXN GPP_F7/SATA_DEVSLP5 AR47
K16 USB31_4_RXP GPP_F6/SATA_DEVSLP4 AP48 WLAN_USB_DET
USB31_4_RXN GPP_F5/SATA_DEVSLP3 WLAN_USB_DET [63]
RN1901
CANON-LAKE-GP USB_OC5_R_N 1 8
[16] USB_OC5_R_N PCH_HEATSINK_DET
(071.CANNO.0B0U) 2 7
USB_OC1_R_N 3 6
[16,39] USB_OC1_R_N USB_OC0_R_N
[16,38] USB_OC0_R_N 4 5
B B

SRN10KJ-6-GP

20170417-2
add PCH heatsink hook and detect
PCH_HEATSINK_DET

HS1901 HS1902
1 1
2 2

FOX-CON2-3-GP FOX-CON2-3-GP
(R_) (R_)

HEAT SINK DETECT

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(USB/ESPI)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 19 of 107
5 4 3 2 1
5 4 3 2 1

20170410
add net GPP_A8 for Edison's feedback
SB1D 4 OF 13 3D3V_S0
HDA_BITCLK_PCH BD11 BF36 SIO_PECI_REQ_N R2001 10KR2J-3-GP
HDA_SDIN0_PCH HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# GPP_A8 SIO_PECI_REQ_N [24] GPP_A8
BE11 AV32 1 2
[27] HDA_SDIN0_PCH HDA_SDOUT_PCH HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
BF12 20170410
HDA_SYNC_PCH BG13 HDA_SDO/I2S0_TXD BF41 add net GPP_A8 for Edison's feedback
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC R2002 10KR2J-3-GP
HDA_RST#_PCH BE10 BD42 SLP_WLAN_N SIO_PECI_REQ_N 1 2
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# SLP_WLAN_N [63]
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 SM_DRAMRST#
SM_DRAMRST# [11,12]

Vinafix.com
I2S1_SFRM BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 UART_BT_WAKE_N R2003 1KR2J-1-GP
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# UART_BT_WAKE_N [63] PCH_SYSPWROK
BF33 1 2
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29 R2004 (R_)
AUD_AZACPU_SDO_R AM2 GPP_B0/GSPI0_CS1# R47 0R2J-2-GP 20170609
AUD_AZACPU_SDI_R AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29 SUS_PWR_ACK 1 (R_) 2 SUS_WARNB R2005 change to 1kohm follow CRB Design
D [7] AUD_AZACPU_SDI_R AUD_AZACPU_SCLK_R AM3 HDACPU_SDI GPP_B11/I2S_MCLK AU3 PCH_SYSPWROK 3D3V_SB
D
PCH_SYSPWROK [24,99]
1

HDACPU_SCLK SYS_PWROK 20170613 R2007 10KR2J-3-GP


R2054 AV18 BB47 PCH_WAKE_N R2004 Change to unmount UART_BT_WAKE_N 1 2
GPP_D8/I2S2_SCLK WAKE# PCH_SLP_A_N PCH_WAKE_N [31,62,63,93,94]
100KR2J-1-GP AW18 BE40
PCM_OUT_PCH GPP_D7/I2S2_RXD GPD6/SLP_A# TP_SLP_LAN_N PCH_SLP_A_N [24,99]
(R_) BA17 BF40 1 TP2001
PCM_SYNC_PCH BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 SLP_S0_N R2009 499R2F-2-GP
SLP_S0_N [91]
2

BF15 GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# BF42 SLP_S3_N 20170411 SML0CLK_PCH 1 2


GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# SLP_S4_N SLP_S3_N [24,40,42,50,99] remove LAN power control
BD16 BE42 SLP_S4_N [8,24,32,38,39,40,99]
AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42 SLP_S5_N 1 TP2003
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# R2010 499R2F-2-GP
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK SML0DATA_PCH 1 2
GPD8/SUSCLK BATLOW_N SUSCLK [18]
BF44
GPD0/BATLOW# BE35 SUS_PWR_ACK
PCH_RTCRST_PULLUP BE47 GPP_A15/SUSACK# BC37 SUS_WARNB SUS_PWR_ACK [38]
R2012 1KR2J-1-GP
PCH_SRTCRSTB_PULLUP BD46 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUS_WARNB [24] SMLICLK_PCH 1 2
SRTCRST#
PCH_PWROK AY42 BG44 LANWAKE_R_N
[40] PCH_PWROK RSMRST_SIO_N PCH_PWROK GPD2/LAN_WAKE#
[24,63,99] RSMRST_SIO_N BA47 BG42 ACPRESENT R2013 1KR2J-1-GP
RSMRST# GPD1/ACPRESENT BD39 SLP_SUSB SMLIDATA_PCH 1 2
PCH_DPWROK SLP_SUS# PWRBTN_N SLP_SUSB [24,42,51]
AW41 BE46 PWRBTN_N [24,64,99]
[26] PCH_DPWROK SMBALERT_N BE25 DSW_PWROK GPD3/PWRBTN# AU2 FP_RST_N R2005 2K2R2J-2-GP
[23] SMBALERT_N SMB_CLK_RESUME GPP_C2/SMBALERT# SYS_RESET# FP_RST_N [99] FP_RST_N
BE26 AW29 SPKR R2006 0R0402-PAD-2-GP 1 2
[24,93,94] SMB_CLK_RESUME SMB_DATA_RESUME GPP_C0/SMBCLK GPP_B14/SPKR H_PWRGD_R SPKR [23,27]
[24,93,94] SMB_DATA_RESUME BF26 AE3 1 2 H_PWRGD H_PWRGD [4,99]
SML0ALERT# BF24 GPP_C1/SMBDATA CPUPWRGD
[23] SML0ALERT# SML0CLK_PCH GPP_C5/SML0ALERT# ITP_PMODE
BF25 AL3 20170411 3D3V_S5
SML0DATA_PCH BE24 GPP_C3/SML0CLK ITP_PMODE AH4 H_TCK ITP_PMODE [99] remove WLAN power control
TMIN_SHIFT_PCH GPP_C4/SML0DATA PCH_JTAGX PCH_JTAG_TMS H_TCK [4] 20170421
BD33 AJ4
[23] TMIN_SHIFT_PCH SMLICLK_PCH GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS [4] add WALN power control for BIOS's request
BF27 AH3 R2044
(R_) 10KR2J-3-GP
[24] SMLICLK_PCH SMLIDATA_PCH BE27 GPP_C6/SML1CLK PCH_JTAG_TDO AH2 PCH_JTAG_TDI PCH_JTAG_TDO [4] SLP_WLAN_N 1 2
[24] SMLIDATA_PCH GPP_C7/SML1DATA PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI [4]
AJ3
PCH_JTAG_TCK R2014 1KR2J-1-GP

1
20170410 CANON-LAKE-GP Place Near PCH within 1.1 inch PCH_WAKE_N 1 2
change net name form TMIN_SHIFT to TMIN_SHIEF_PCH for Edison's feedback R2011 DB2001 0R3J-0-U-GP
(071.CANNO.0B0U)
51R2F-2-GP PCH_PWROK 1 2
(R_) (R_) R2015 10KR2J-3-GP
ACPRESENT 1 2

2
For DB1 Debug Hole
C C
RN2001
BATLOW_N 1 4
LANWAKE_R_N 2 3
R2017 33R2J-2-GP
HDA_BITCLK_CODEC 1 2 HDA_BITCLK_PCH SRN10KJ-5-GP
[27] HDA_BITCLK_CODEC

[27] HDA_RST#_CODEC
HDA_RST#_CODEC
R2019
1
33R2J-2-GP
2 HDA_RST#_PCH
CRB
20170607

R2020 33R2J-2-GP
SLP_S0_N de-glitch circuit V_CPU_ST_PLL
R2021/R2024/R2026/R2028 change Power rail
V_CPU_ST_PLL
HDA_SDOUT_CODEC 1 2 HDA_SDOUT_PCH R2021 1K5R2F-2-GP
[27] HDA_SDOUT_CODEC H_TCK 1 2
20170411 (R_)
R2022 33R2J-2-GP reserve CEC control
HDA_SYNC_CODEC 1 2 HDA_SYNC_PCH 20170517 R2024 100R2F-L1-GP-U
[27] HDA_SYNC_CODEC Remove U2001 U2002 U2003 PCH_JTAG_TDO 1 2

R2025 30R2J-1-GP
AUD_AZACPU_SDO 1 2 AUD_AZACPU_SDO_R SLP_S0_N DB2002 1 2 0R3J-0-U-GP SLP_S0_PLT_N 1 TP2002 R2026 51R2F-2-GP
[7] AUD_AZACPU_SDO PCH_JTAG_TDI 1 2
(R_)
R2027 30R2J-1-GP
AUD_AZACPU_SCLK 1 2 AUD_AZACPU_SCLK_R R2028 51R2F-2-GP
[7] AUD_AZACPU_SCLK PCH_JTAG_TMS 1 2

R2032 33R2J-2-GP For ITH/DCI debug


PCM_OUT 1 2 PCM_OUT_PCH
[63] PCM_OUT

R2033 33R2J-2-GP
PCM_SYNC 1 2 PCM_SYNC_PCH
[63] PCM_SYNC

20170607
Remove R2030
B B

(R_)
HDA_BITCLK_PCH R2052 1 2 100KR2J-1-GP

HDA_RST#_PCH R2053 1 (R_) 2 100KR2J-1-GP


ME ENABLE/DISABLE PASSWORD CLEAR CLEAR CMOS SLP_WLAN_N R2048 1 (R_) 2 100KR2J-1-GP
With Jumper ME Disable With Jumper Normal Mode With Jumper Clear CMOS PCH_SLP_A_N R2047 1 (R_) 2 100KR2J-1-GP
Without Jumper Normal Mode Without Jumper Clear Password Without Jumper Normal Mode SLP_S3_N R2046 1 (R_) 2 100KR2J-1-GP
3D3V_SB SLP_S4_N
R2034 0R0402-PAD-2-GP R2035 4K7R2J-2-GP R2045 1 (R_) 2 100KR2J-1-GP
1 2 ME_CNTL_2 PCH_RTCRST_DOWN 1 2
SLP_SUSB R2055 1 (R_) 2 100KR2J-1-GP
2

4
6

R2036 0R0402-PAD-2-GP
JMP1 1 2 PCH_RTCRST_N
PCH_RTCRST_N [99]
E

R2037 1KR2J-1-GP PIN-CONN6A-S3-GP


ME_CNTL 1 2 ME_CNTL_1 B LMBT3906LT1G-1-GP
[15] ME_CNTL
Q2001
1

3
5
C

R2038 1KR2J-1-GP R2039 0R0402-PAD-2-GP R2040 30K1R2F-L-GP


HDA_SDOUT_PCH 1 2 AUD_LINK_SDO_C 1 2 AUD_LINK_SDO_R1 PCH_RTCRST_PULLUP 1 2
3P0V_BAT_VREG

3D3V_SB
C2006 1 2 SC1U10V2KX-1DLGP
1

R2042 30K1R2F-L-GP
A R2041 1 2 PCH_SRTCRSTB_PULLUP A
3P0V_BAT_VREG
10KR2J-3-GP

1
1

R2043
2

PW_CLEAR C2007 4K7R2J-2-GP


[17] PW_CLEAR
SC1U10V2KX-1DLGP (R_)
2

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(GPIO/SMBUS/IHDA/JTAG)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 20 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
SB1H 8 OF 13 C2101
D D
AA22 AW9 SCD1U16V2KX-3DLGP
1V_PCH_SB VCCPRIM_1P051 VCCPRIM_3P32 3D3V_SB
AA23
AB20 VCCPRIM_1P052 BF47 DCPRTC 1 2
AB22 VCCPRIM_1P053 DCPRTC1 BG47
AB23 VCCPRIM_1P054 DCPRTC2
AB27 VCCPRIM_1P055 V23
VCCPRIM_1P056 VCCPRIM_3P35 3D3V_SB
AB28 AN44
VCCPRIM_1P057 VCCSPI 3D3V_SB
AB30
AD20 VCCPRIM_1P058 BC49
VCCPRIM_1P059 VCCRTC1 3P0V_BAT_VREG
AD23 BD49
AD27 VCCPRIM_1P0510 VCCRTC2
AD28 VCCPRIM_1P0511 AN21
VCCPRIM_1P0512 VCCPGPPG_3P3 3D3V_SB
AD30 AY8
AF23 VCCPRIM_1P0513 VCCPRIM_3P33 BB7
AF27 VCCPRIM_1P0516 VCCPRIM_3P34
AF30 VCCPRIM_1P0517 AC35
VCCPRIM_1P0518 VCCPGPPHK1 3D3V_SB
U26 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 1D8V_SB 3D3V_SB
VCCPRIM_1P0524 VCCPGPPEF1 3D3V_SB
V25 AE36
V27 VCCPRIM_1P0525 VCCPGPPEF2
V28 VCCPRIM_1P0526 AN24 1D8V_SB_CNVI 0R0603-PAD-2-GP-U 1 2 R2101
V30 VCCPRIM_1P0527 VCCPGPPD AN26
VCCPRIM_1P0528 VCCPGPPBC1 3D3V_SB
V31 AP26 0R3J-0-U-GP 1 2 R2102 (R_)
VCCPRIM_1P0529 VCCPGPPBC2

1V_PCH_SB AD31 AN32 3D3V_SB


AE17 VCCPRIM_1P0514 VCCPGPPA
VCCPRIM_1P0515 AT44
VCCPRIM_3P31 3D3V_SB
1V_PCH_SB W22 BE48 3D3V_S5
W23 VCCDUSB_1P051 VCCDSW_3P31 BE49
VCCDUSB_1P052 VCCDSW_3P32
BG45 BB14
1V_VCCDSW VCCDSW_1P051 VCCHDA 3D3V_SB
BG46 AG19
VCCDSW_1P052 VCCPRIM_1P83 1D8V_SB
1V_PCH_SB W31 AG20
VCCPRIM_MPHY_1P05 VCCPRIM_1P84 AN15
D1 VCCPRIM_1P85 AR15
E1 VCCPRIM_1P0521 VCCPRIM_1P86 BB11
1

C2127 1 C2128 1V_VCCAMPHYPLL


C49 VCCPRIM_1P0522 VCCPRIM_1P87
SC22U6D3V3MX-1-DL-GP SC1U10V2KX-1DLGP D49 VCCAMPHYPLL_1P051 AF19
C C
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P81 AF20
2

VCCAMPHYPLL_1P053 VCCPRIM_1P82
P2 AG31
1V_VCCA_XTAL VCCA_XTAL_1P051 VCCPRIM_1P0520 1V_PCH_SB
P3 AF31
W19 VCCA_XTAL_1P052 VCCPRIM_1P0519 AK22
1V_PCH_SB VCCA_SRC_1P051 VCCPRIM_1P241 1D24V_PCH
W20 AK23 20170412
VCCA_SRC_1P052 VCCPRIM_1P242 rename 1D24V_SB to 1D24V_PCH
C1 AJ22
VCCAPLL_1P054 VCCDPHY_1P241 1D24V_PCH
VCCA_PRIM_3p3 C2 AJ23
V19 VCCAPLL_1P055 VCCDPHY_1P242 BG5
Follow CRB , VCCA_BCLK_1P05 VCCDPHY_1P243
Mark B1 K47 TP_VCCPHY_SENSE 1 TP2101
3D3V_SB B2 VCCAPLL_1P051 VCCMPHY_SENSE K46 TP_VSSPHY_SENSE 1 TP2102
B3 VCCAPLL_1P052 VSSMPHY_SENSE
VCCAPLL_1P053
CANON-LAKE-GP
(071.CANNO.0B0U)
1

C2126
SC10U6D3V3MX-DL-GP
2

20170412
rename 1D24V_SB to 1D24V_PCH

3P0V_BAT_VREG 3D3V_SB
3P0V_BAT_VREG 3D3V_SB 3D3V_S5 1D8V_SB 1D24V_PCH
Current:0.000416A

1
C2108 C2109
C2102 C2103 C2104 C2105 C2106 C2107 SC4D7U6D3V3KX-DLGP SC4D7U6D3V3KX-DLGP
1V_PCH_SB 1V_VCCAMPHYPLL 2 SCD1U16V2KX-3DLGP SC1U10V2KX-1DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP

2
B B
L2101 1 2 HCB1608KF-601T10-GP
(68.00230.041)
1

C2111 C2112
C2110 SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP
SC1U10V2KX-1DLGP 1V_PCH_SB
2

1
1V_PCH_SB 1V_VCCA_XTAL C2113 C2114 C2115 C2116 C2117
SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
2

2
L2102 1 2 HCB1608KF-601T10-GP
(68.00230.041)
1

C2118 C2119
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP
2

1
C2120 C2121 C2122 C2123 C2124 C2129
SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC22U6D3V3MX-1-DL-GP
1V_VCCDSW
2

2
1

C2125
SC1U10V2KX-1DLGP
2

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(POWER1)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 21 of 107
5 4 3 2 1
5 4 3 2 1

Vinafix.com
D D

SB1J 10 OF 13
Y14
RSVD7 Y15
RSVD8 U37
RSVD6 U35
RSVD5
N32
RSVD3 R32
SB1I 9 OF 13 SB1L 12 OF 13 RSVD4
A2 AL12 BG3 M24 AH15
A28 VSS_1 VSS_73 AL17 BG33 VSS_145 VSS_196 M32 RSVD2 AH14 9/4 Remove TP2201 & TP2202 for(TP_PCH_AH15 &TP_PCH_AH14)
A3 VSS_2 VSS_74 AL21 BG37 VSS_146 VSS_197 M34 RSVD1
A33 VSS_3 VSS_75 AL24 BG4 VSS_147 VSS_198 M49
A37 VSS_4 VSS_76 AL26 BG48 VSS_148 VSS_199 M5
A4 VSS_5 VSS_77 AL29 C12 VSS_149 VSS_200 N12 AL2 PCH_XDP_PREQ_R_N
VSS_6 VSS_78 VSS_150 VSS_201 PREQ# PCH_XDP_PRDY_R_N PCH_XDP_PREQ_R_N [99]
A45 AL33 C25 N16 AM5
VSS_7 VSS_79 VSS_151 VSS_202 PRDY# H_TRST_N_R PCH_XDP_PRDY_R_N [99]
A46 AL38 C30 N34 AM4 H_TRST_N_R [4]
A47 VSS_8 VSS_80 AM1 C4 VSS_152 VSS_203 N35 CPU_TRST# AK3 PROC_TRIGIN_PCH R2201 1 2 30D1R2F-L-GP PROC_TRIGIN_CPU
A48 VSS_9 VSS_81 AM18 C48 VSS_153 VSS_204 N37 TRIGGER_OUT AK2 PROC_TRIGOUT_PCH PROC_TRIGIN_CPU [9]
VSS_10 VSS_82 VSS_154 VSS_205 TRIGGER_IN PROC_TRIGOUT_PCH [9]
A5 AM32 C5 N38
A8 VSS_11 VSS_83 AM49 D12 VSS_155 VSS_206 P26 CANON-LAKE-GP
AA19 VSS_12 VSS_84 AN12 D16 VSS_156 VSS_207 P29 Place close CPU <200mil
VSS_13 VSS_85 VSS_157 VSS_208 (071.CANNO.0B0U)
AA20 AN16 D17 P4
AA25 VSS_14 VSS_86 AN34 D30 VSS_158 VSS_209 P46
AA27 VSS_15 VSS_87 AN38 D33 VSS_159 VSS_210 R12
AA28 VSS_16 VSS_88 AP4 D8 VSS_160 VSS_211 R16
AA30 VSS_17 VSS_89 AP46 E10 VSS_161 VSS_212 R26
AA31 VSS_18 VSS_90 AR12 E13 VSS_162 VSS_213 R29
AA49 VSS_19 VSS_91 AR16 E15 VSS_163 VSS_214 R3
AA5 VSS_20 VSS_92 AR34 E17 VSS_164 VSS_215 R34
C C
AB19 VSS_21 VSS_93 AR38 E19 VSS_165 VSS_216 R38
AB25 VSS_22 VSS_94 AT1 E22 VSS_166 VSS_217 R4
AB31 VSS_23 VSS_95 AT16 E24 VSS_167 VSS_218 T17
AC12 VSS_24 VSS_96 AT18 E26 VSS_168 VSS_219 T18
AC17 VSS_25 VSS_97 AT21 E31 VSS_169 VSS_220 T32
AC33 VSS_26 VSS_98 AT24 E33 VSS_170 VSS_221 T4
AC38 VSS_27 VSS_99 AT26 E35 VSS_171 VSS_222 T49
AC4 VSS_28 VSS_100 AT29 E40 VSS_172 VSS_223 T5
AC46 VSS_29 VSS_101 AT32 E42 VSS_173 VSS_224 T7
AD1 VSS_30 VSS_102 AT34 E8 VSS_174 VSS_225 U12
AD19 VSS_31 VSS_103 AT45 F41 VSS_175 VSS_226 U15
AD2 VSS_32 VSS_104 AV11 F43 VSS_176 VSS_227 U17
AD22 VSS_33 VSS_105 AV39 F47 VSS_177 VSS_228 U21
AD25 VSS_34 VSS_106 AW10 G44 VSS_178 VSS_229 U24
AD49 VSS_35 VSS_107 AW4 G6 VSS_179 VSS_230 U33
AE12 VSS_36 VSS_108 AW40 H8 VSS_180 VSS_231 U38
AE33 VSS_37 VSS_109 AW46 J10 VSS_181 VSS_232 V20
AE38 VSS_38 VSS_110 B47 J26 VSS_182 VSS_233 V22
AE4 VSS_39 VSS_111 B48 J29 VSS_183 VSS_234 V4
AE46 VSS_40 VSS_112 B49 J4 VSS_184 VSS_235 V46
AF22 VSS_41 VSS_113 BA12 J40 VSS_185 VSS_236 W25
AF25 VSS_42 VSS_114 BA14 J46 VSS_186 VSS_237 W27
AF28 VSS_43 VSS_115 BA44 J47 VSS_187 VSS_238 W28
AG1 VSS_44 VSS_116 BA5 J48 VSS_188 VSS_239 W30
AG22 VSS_45 VSS_117 BA6 J9 VSS_189 VSS_240 Y10
AG23 VSS_46 VSS_118 BB41 K11 VSS_190 VSS_241 Y12
AG25 VSS_47 VSS_119 BB43 K39 VSS_191 VSS_242 Y17
AG27 VSS_48 VSS_120 BB9 M16 VSS_192 VSS_243 Y33
AG28 VSS_49 VSS_121 BC10 M18 VSS_193 VSS_244 Y38
AG30 VSS_50 VSS_122 BC13 M21 VSS_194 VSS_245 Y9
AG49 VSS_51 VSS_123 BC15 VSS_195 VSS_246
AH12 VSS_52 VSS_124 BC19 CANON-LAKE-GP
AH17 VSS_53 VSS_125 BC24
VSS_54 VSS_126 (071.CANNO.0B0U)
AH33 BC26
AH38 VSS_55 VSS_127 BC31
AJ19 VSS_56 VSS_128 BC35
AJ20 VSS_57 VSS_129 BC40
B
AJ25 VSS_58 VSS_130 BC45 B
AJ27 VSS_59 VSS_131 BC8
AJ28 VSS_60 VSS_132 BD43
AJ30 VSS_61 VSS_133 BE44
AJ31 VSS_62 VSS_134 BF1
AK19 VSS_63 VSS_135 BF2
AK20 VSS_64 VSS_136 BF3
AK25 VSS_65 VSS_137 BF48
AK27 VSS_66 VSS_138 BF49
AK28 VSS_67 VSS_139 BG17
AK30 VSS_68 VSS_140 BG2
AK31 VSS_69 VSS_141 BG22
AK4 VSS_70 VSS_142 BG25
AK46 VSS_71 VSS_143 BG28
VSS_72 VSS_144
CANON-LAKE-GP
(071.CANNO.0B0U)

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(VSS)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 22 of 107
5 4 3 2 1
5 4 3 2 1

GPP_B14 / SPKR Top Swap Rising edge of The signal has a weak internal Pull-down. GPP_H15 / Reserved Rising edge of External pull-up is required. Recommend 100K if pulled GPP_F23 Display Rising edge of This signal has a weak internal pull-down.
Override PCH_PWROK 0 = Disable “Top Swap” mode. (Default) SML3ALERT# RSMRST# up to 3.3V or 75K if pulled up to 1.8V. Port F PCH_PWROK 0 = Port F is not detected. (Default)
1 = Enable “Top Swap” mode. This inverts an address This strap should sample HIGH. There should NOT be Detected 1 = Port F is detected.
on access to SPI and firmware hub, so the any on-board device driving it to opposite direction
processor believes it fetches the alternate boot during strap sampling.
block instead of the original boot-block. PCH will
invert A16 (default) for cycles going to the upper PCIVAUX power control
two 64-KB blocks in the FWH or the appropriate
Swap Block size soft strap .
Vinafix.com
address lines (A16, A17, or A18) as selected in Top
[15] GPP_H_15
GPP_H_15
R2301
1
4K7R2J-2-GP
2
3D3V_SB
GPP_J4 /
CNV_BRI_DT /
XTAL
Frequency
Rising edge of
RSMRST#
This signal has a weak internal pull-down.
0 = 38.4/19.2MHz XTAL frequency selected. (Default)
R2302 4K7R2J-2-GP UART0_RTS# Select 1 = 24MHz XTAL frequency selected.
D D
SPKR 1 2
[20,27] SPKR 3D3V_S0
(R_)
GPP_B23 / Reserved Rising edge of This signal has an internal Pull-down. External pull-up is R2303 10KR2J-3-GP
R2304 20KR2J-L2-GP SML1ALERT# / RSMRST# required. CNV_BRI_DT 1 2
PCHHOT# This strap should sample HIGH. There should NOT be [15] CNV_BRI_DT 1D8V_SB
1 2
(R_) any on-board device driving it to opposite direction
during strap sampling.
R2305 10KR2J-3-GP
20170504 1 2
20170410 Will R2303 change to mount (R_)
change net name form TMIN_SHIFT to TMIN_SHIEF_PCH for Edison's feedback Follow PCH EDS 0.7
GPP_B18 / No Reboot Rising edge of The signal has a weak internal Pull-down. add reserved series resistor to solate the net from SIO for Edison's feedback
GSPI0_MOSI PCH_PWROK 0 = Disable “No Reboot” mode. (Default) R2306 0R2J-2-GP
1 = Enable “No Reboot” mode (PCH will disable the 1 2 TMIN_SHIFT
TCO Timer system reboot feature). This function is TMIN_SHIFT [24]
(R_) GPP_J6 / Modem Rising edge of An external pull-up or pull-down is required.
useful when running ITP/XDP. CNV_RGI_DT / Reference RSMRST# 0 = Integrated CNVI enable (Default)
R2307 4K7R2J-2-GP UART0_TXD Clock 1 = Integrated CNVI disable
TMIN_SHIFT_PCH 1 2 Source
[20] TMIN_SHIFT_PCH 3D3V_SB Select

20170515 R2309 20KR2J-L2-GP


Remove R2308 &R2311 ,default is internal pull down 1 2 R2310 20KR2J-L2-GP
add TP at PCH side (R_) CNV_RGI_DT 1 2
[15] CNV_RGI_DT 1D8V_SB

R2312 10KR2J-3-GP
20170613 1 2
SPI0_IO2 Reserved Rising edge of External pull-up is required. Recommend 100K if pulled R2310 Change to mount
RSMRST# up to 3.3V or 75K if pulled up to 1.8V. R2312 Change to unmount (R_)
GPP_C2 / TLS Rising edge of This signal has a weak internal Pull-down. This strap should sample HIGH. There should NOT be
SMBALERT# Confidentiality RSMRST# 0 = Disable Intel ME Crypto Transport Layer Security any on-board device driving it to opposite direction
(TLS) cipher suite (no confidentiality). (Default) during strap sampling.
1 = Enable Intel ME Crypto Transport Layer Security GPP_J9 1.8V Rising edge of The signal has a weak internal pull-down
(TLS) cipher suite (with confidentiality). Must be VCCPSPI RSMRST# 0 = VCCPSPI is connected to 3.3V rail
pulled up to support Intel AMT with TLS. 1 = VCCPSPI is connected to 1.8V rail
R2313 20KR2J-L2-GP
SPI_WP_PCH 1 2
[15,25] SPI_WP_PCH 3D3V_SPI
R2314 10KR2J-3-GP 20170613
C SMBALERT_N 1 2 R2313 change to muount C
[20] SMBALERT_N 3D3V_SB

20170613 SPI0_IO3 Reserved Rising edge of External pull-up is required. Recommend 100K if pulled
Remove R2316,because CPU default Pull down RSMRST# up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction GPD7 Reserved Rising edge of External pull-up is required. Recommend 100K.
during strap sampling. DSW_PWROK This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling
GPP_B22 / Boot BIOS Rising edge of This Signal has a weak internal Pull-down. R2317 20KR2J-L2-GP
GSPI1_MOSI Strap Bit PCH_PWROK This field determines the destination of accesses to the SPI_HOLD_PCH 1 2
BBS BIOS memory range. Also controllable using Boot BIOS [15,25] SPI_HOLD_PCH 3D3V_SPI
Destination bit (Bus0, Device31, Function0, offset DCh, 20170613 GPD7 R2318 1 2 1KR2J-1-GP
bit 6). R2317 change to muount [16] GPD7 3D3V_S5
Bit 6 Boot BIOS Destination 20170609
0 SPI (Default) update R2318 pull high 1kohm follow CRB
1 LPC HDA_SDO / Flash Rising edge of This signal has a weak internal Pull-down.
I2S0_TXD Descriptor PCH_PWROK 0 = Enable security measures defined in the Flash
Security Descriptor. (Default)
Override 1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
Pull-up in manufacturing/debug environments
ONLY.
20170515
Remove R2319 &R2320 ,default is internal pull down
add TP at PCH side
ME DISABLE JUMPER

GPP_H12 / eSPI Flash Rising edge of This signal has a weak internal pull-down.
GPP_C5 / eSPI or LPC Rising edge of This signal has a weak internal Pull-down. SML2ALERT# Sharing RSMRST# 0 = Master Attached Flash Sharing (MAFS) enabled
SML0ALERT# RSMRST# 0 = LPC is selected (for EC). (Default) Mode (Default)
1 = eSPI is selected (for EC). 1 = Slave Attached Flash Sharing (SAFS) enabled.

R2323 20KR2J-L2-GP 20170512


SML0ALERT# 1 2 Remove R2322
B [20] SML0ALERT# GPP_H_12 B
add TP at PCH side follow D9

20170613
Remove R2321
GPP_I6 / Display Rising edge of This signal has a weak internal Pull-down.
DDPB_CTRLDATA Port B PCH_PWROK 0 = Port B is not detected. (Default)
Detected 1 = Port B is detected.

SPI0_MOSI Reserved Rising edge of External pull-up is required. Recommend 100K if pulled
RSMRST# up to 3.3V or 75K if pulled up to 1.8V. R2324 2K2R2J-2-GP
This strap should sample HIGH. There should NOT be HDMI_DATA_CPU 1 2
any on-board device driving it to opposite direction [19,56] HDMI_DATA_CPU 3D3V_S0
during strap sampling.

R2325 1KR2J-1-GP
SPI_SI_PCH 1 2 GPP_I8 / Display Rising edge of This signal has a weak internal Pull-down.
[15,25,91,99] SPI_SI_PCH 3D3V_SPI DDPC_CTRLDATA Port C PCH_PWROK 0 = Port C is not detected. (Default)
(R_)
Detected 1 = Port C is detected.
20170609 R2326 4K7R2J-2-GP
R2325 change to unmounted follow CRB 1 2
(R_) R2327 2K2R2J-2-GP
DDPC_CTRL_DATA 1 2
[19] DDPC_CTRL_DATA 3D3V_S0
R2328 4K7R2J-2-GP (R_)
SPI_SO_PCH 1 2
[15,25,91] SPI_SO_PCH
(R_)

GPP_I10 / Display Rising edge of This signal has a weak internal pull-down.
DDPD_CTRLDATA Port D PCH_PWROK 0 = Port D is not detected. (Default)
Detected 1 = Port D is detected.

R2329 2K2R2J-2-GP
DDPD_CTRL_DATA 1 2
[19] DDPD_CTRL_DATA 3D3V_S0
(R_)
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_(Strap Pin)
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 23 of 107
5 4 3 2 1
5 4 3 2 1

20170406
FAN [26] CPU_FAN_TACH_SIO Layout Note: place 2200PF near SIO, rename for new PSU design
20170418 Circuit to Support pre-Post Diagnostic 20170406
rename the net PLTRST_PCI_N to PLTRST_BUF_PCI_N
[26] CPU_FAN_CTRL_SIO others near PCH location Layout Note: place 2200PF near SIO, rename for D9 PSU design rename the net PLTRST_LAN_N to PLTRST_BUF_LAN_N
others near CPU core MOS location 20170419
3D3V_S0
[26] SYS_FAN_TACH_SIO SYS_THERMDA+ rename for new PSU and D9 PSU design
[26] SYS_FAN_CTRL_SIO 3D3V_S5 3D3V_S0 0D95V_CPU_VCCIO R2401 22R2J-2-GP
CPU_THERMDA+ 12V_CPU PCIRST1# 1 2 PLTRST_BUF_PCI_N
PLTRST_BUF_PCI_N [40]

1
1

1
R2405 R2406 100KR2J-1-GP

1
R2403 R2404 30KR2F-GP 1 2
20170518 R2402 30KR2F-GP 9K1R2F-1-GP Q2402 (R_) PCIEx16, PCIEx1, PCI bridge
add for SSD 8K2R2F-1-GP 1 6 MB_REG_PG

2
E
1

1
C2402 Q2401 R2407 22R2J-2-GP

2
1

1
SC2200P50V2KX-2DLGP Q2403 B C2403(R_) Q2409 B C2427(R_) C2404 1 6 MB_REG_PG_1 2 5 SP_TXD_N_1 PCIRST2# 1 2 PLTRST_BUF_LAN_N
CLOCK PLTRST_BUF_LAN_N [40]

2
LMBT3904LT1G-GP SC100P50V2JN-3DLGP LMBT3904LT1G-GP SC100P50V2JN-3DLGP SC2200P50V2KX-2DLGP Q2404 B C2401(R_)

2
LMBT3904LT1G-GP PWR2_PRSN_1 2 5 PWR2_PRSN_2 SP_TXD_N 3 4
[19] LPC_CLK_14M_EC SC100P50V2JN-3DLGP 5V_S0

2
C
E

1
20170410 R2410 100KR2J-1-GP
[19] LPC_CLK_33M_EC

1
change to common part 20170410 PWR2_PRSNT 3 4 R2409 MMDT3904-2-GP 1 2
[18] SUSCLK_SIO

Vinafix.com
change to common part R2408 6K8R2F-2-GP (R_) LAN, WALN, SSD, LPC, TPM
SYS_THERMDA- 680R2F-GP MMDT3904-2-GP
CPU_THERMDA-

2
LPC

2
D D
[19,68] LPC_AD_PCH_P0
[19,68] LPC_AD_PCH_P1
[19,68] LPC_AD_PCH_P2
[19,68] LPC_AD_PCH_P3 VBAT2 3D3V_SB
C2405 20170421 3D3V_S0
SC1U10V2KX-1DLGP change to 10KR2F to follow vendor's feedback 3D3V_S0 1V_PCH_SB
[19,68] LPC_FRAME#_PCH

1
3D3V_S0

1
3D3V_S0 R2411

1
1 2 R2415 10KR2F-2-GP
Divide to 0.55V

1
R2414 2KR2F-3-GP

1
3D3V_S0 R2413 9K1R2F-1-GP Q2406

2
3D3V_SB R2412 10KR2F-2-GP 1 6 MB_REG_PG VIN_DET

2
30KR2F-GP Q2405

1
3D3V_S5 C2408 VR_READY 1 6 MB_REG_PG MB_REG_PG_3 2 5 MB_REG_PG_2

2
1

1
C2406 SCD1U16V2KX-3DLGP C2407 R2416

2
SCD1U16V2KX-3DLGP 3D3V_S5 MEM_REG_PG_2 2 5 MEM_REG_PG_1 MB_REG_PG 3 4 SCD01U50V2KX-1DLGP 2KR2F-3-GP
3D3V_S0

1
1 2

2
V5_ALW_MON MEM_REG_PG 3 4 R2423 MMDT3904-2-GP R2424
1D2V_SM_S3

2
1
7K15R2F-L-GP 33KR2F-GP
MMDT3904-2-GP R2417

104
120
9K1R2F-1-GP

15

22
32
55
60
65
77

21

45

27

2
4
U2401

VBAT
V3_DUAL
V3_DUAL
V3_DUAL
V3_DUAL
V3_DUAL
V3_DUAL
V3_DUAL
V3_DUAL

HV3_DUAL

V3_S5
V5_ALW_MON

VCC

2
20170509
change from SUSCLK to SUSCLK_SIO to follow D9
SMBUS SUSCLK_SIO 19
CLK32 SDAT_1/GP120
78 SMB_DATA_RESUME
LPC_CLK_14M_EC 7 79 SMB_DATA_MAIN 20170613
[11,12,59] SMB_CLK_MAIN LPC_AD_PCH_P0 CLOCKI SDAT/GP121 SMB_CLK_RESUME remove R2418
8 80 5V_S5
[11,12,59] SMB_DATA_MAIN LPC_AD_PCH_P1 9 LAD0 SCLK_1/GP122 81 SMB_CLK_MAIN
[20,93,94] SMB_DATA_RESUME LPC_AD_PCH_P2 10 LAD1 SCLK/GP123
[20,93,94] SMB_CLK_RESUME LPC_AD_PCH_P3 LAD2
LPC I/F 11 R2478 10KR2J-3-GP

LPC Interface

Miscellaneous
LPC_FRAME#_PCH 12 LAD3 1 2
[20] SMLICLK_PCH PLTRST#_SIO LFRAME# 3D3V_SB
14 (R_) R2419 10KR2J-3-GP
[20] SMLIDATA_PCH [15] PLTRST#_SIO LPC_CLK_33M_EC LRESET# SUS_ACK_EN_N
16 1 2
LPC_SERIRQ_PCH 127 PCICLK 87 U2405
LPC_PME_N 75 SER_IRQ GP105 5 1 20170613 3D3V_SB
OTHERS [15] LPC_PME_N PCH_SLP_A_N 126 GP041/IO_PME#
SLP_M#/GP071/IO_SMI# GP107
89
3D3V_SB VCC IN_B H_SKTOCC_CPU [4] R2419 Change to mount R2421 10KR2J-3-GP
20170406 20170613 13 2 PWR2_PRSN_2 LPC_PME_N 1 2
[4,44] PROCHOT#_CPU_R remove net SIO_SMBCLK1 Remove R2420 GP117 PCIAUX_GATE IN_A
92
[19] KBRST_N remove net SIO_SMBDAT1 GP125 93 4 3
20170421 SIO_SMBCLK1 70 GP126 94 SUS_ACK_EN_N [15] H_SKTOCC_N OUT_Y GND R2425 10KR2J-3-GP
[19,68] LPC_SERIRQ_PCH add back to follow vendor's feedback SIO_SMBDAT1 GP036/SMB_CLK1 SUS_ACK_EN#/GP127 SUS_ACK_EN_N [38] SIO_SMBCLK1
72 95 TC7SZ32FU-2-GP 20170406 1 2

SMB
SMLIDATA_PCH R2422 1 2 0R0402-PAD-2-GP SIO_SMBDAT2 25 GP040/SMB_DAT1 BACKFEED_CUT#/GP116 remove net SIO_SMBCLK1
SMLICLK_PCH SMBDAT2/GP010 (R_)
R2426 1 2 0R0402-PAD-2-GP SIO_SMBCLK2 26 20170508 remove net SIO_SMBDAT1
SMBCLK2/GP011 96 SP_DCD_N add TXD, RXT @ LPC connector for BIOS debug 20170421 R2427 10KR2J-3-GP
GPIO [20,99] PCH_SLP_A_N
V_CPU_ST_PLL DCD1#/GP043
DSR1#/GP044
97 SP_DSR_N add back to follow vendor's feedback
SIO_SMBDAT1 1 2
SIO_PECI_REQ_N 20 98 SP_RXD_N
[20] SIO_PECI_REQ_N H_CPURST#/GP005/PECI_REQUEST# RXD1/GP045 SP_RTS_N SP_RXD_N [68]

Serial Port 1
29 99 R9924 1 2 0R2J-2-GP
PECI_CPU R2428 1 2 43D2R2F-GP PECI_EC 30 PECI_VREF RTS1#/GP046 100 SP_TXD_SIO R2431 4K7R2J-2-GP
PECI/LVSMB_CLK1 5V_PRSNT/GP047/TXD1 SP_TXD_SIO [68]
1

C2411 R2430 1 2 10KR2J-3-GP PECI_READY 31 101 SP_CTS_N TMIN_SHIFT 1 2

PECI
C
V_CPU_ST_PLL PECI_READY/LVSMB_DAT1 CTS1#/GP050 SP_DTR_N C
SC4D7U6D3V3KX-DLGP 102 R2477 10KR2J-3-GP
DTR1#/GP051 103 SP_RI_N SUS_WARNB (R_) 1 2
2

20170410 PCIRST1# 51 RI1#/GP052 20170613


Power Manager change to 4D7U for Edison's feedback
When 3P3V_SB ready, PCI_RST_1#/GP026 ADD R2477 for SUS_WARNB signal
PCIRST2# 52 R2432 10KR2J-3-GP
RSMRST asserted SIO_PS_ON_N 53 PCI_RST_2#/GP027 SP_TXD_SIO R2429 1 2 160R2F-GP SP_TXD_N PCIAUX_GATE 1 2
PCH_PWROK_EC [43] SIO_PS_ON_N EC_PWRGD_3V PS_ON#/GP030
[26] PCH_SIO_DPWROK R2433 1 2 33R2J-2-GP 57 106
RSMRST_SIO_N R2434 1 2 0R0402-PAD-2-GP RSMRST_SIO_N_1 58 PWR_GOOD_3V/GP033 GP054
67 RSMRST# PWR2_PRSNT

Glue Logic
R2435 108 RN2404
1 2 PWRGD_PS 123 LATCHED_BF_CUT/GP035 PWR2_PRSNT/GP056 109 MB_REG_PG SMB_CLK_RESUME 1 4
3D3V_S0 PWRGD_PS MB_REG_PG/GP057
CEC

Diagnostic
10KR2J-3-GP SMB_DATA_RESUME 2 3
111 MEM_REG_PG
[20,63,99] RSMRST_SIO_N MEM_REG_PG/GP061 SRN1KJ-7-GP
SLP_S3_N 121 PCH_SYSPWROK 20170411
reserve CEC control
D

[20,24,99] PCH_SYSPWROK [20,40,42,50,99] SLP_S3_N SLP_S4_N 69 SLP_S3# 20170615


DPWROK pull up when
[8,20,32,38,39,40,99] SLP_S4_N SLP_S4# Remove CEC control for PCH_SYSPWROK
122 113 KCLK
Q2407
V3_Dual pull out to 50% PCH_SIO_DPWROK 28 SLP_S5#/GP066 KCLK 114 KDAT
2N7002K-2-GP DPWROK/GP013 KDAT 115 MCLK
[23] TMIN_SHIFT SUS_WARNB SUS_WARNB_R MCLK PCH_PWROK_EC PCH_SYSPWROK
R2438 1 2 0R0402-PAD-2-GP 68 116 MDAT R2439 1 2 0R0402-PAD-2-GP

Deep Sleep Logic


SLP_SUSB SUS_WARN#/GP004 MDAT KBRST_N PCH_SYSPWROK [20,24,99]
71 118
[40] VR_READY SLP_SUS# GP063/KBDRST#
C2412 2 1 SC1U10V2KX-1DLGP 74 119 A20GATE
[20] SUS_WARNB SUS3V_ON#/GP076 GP064/A20M
56

Keyboard/
(R_)
G

1
73 SUS3V_FON#/GP032

Mouse
[20,42,51] SLP_SUSB SUS5V_ON#/GP075

1
C2413 R2442
VCTRL_VCC_EN 37 CPU_FAN_TACH_SIO SC100P50V2JN-3DLGP 20KR2J-L2-GP
[42,43] PSPWRGD TACH1/GP017 38 SYS_FAN_TACH_SIO

2
TACH2/GP020 39 SYS_FAN2_TACH_SIO 3D3V_SB
[42] VCTRL_VCC_EN

2
TACH3/GP021 RN2403
MDAT 1 8

Miscellaneous
47 CPU_FAN_CTRL_SIO MCLK 2 7
GP022/PWM1 48 SYS_FAN_CTRL_SIO KDAT 3 6
GP023/PWM2 49 KCLK 4 5
THERM_THRESH/GP024/PWM3 2 SIO_GREEN
GP000/PWM4 SRN8K2J-4-GP 3D3V_S0

HWM Interface
46 VIN_DET
SIO_YELLOW 23 V_IN RN2401
SIO_GREEN 24 YELLOW#/GP006 41 CPU_THERMDA+ SP_RTS_N 1 8
R2446 1 2 330KR2F-L-GP TMIN_SHIFT 33 GREEN#/GP007 REMOTE1+ 42 CPU_THERMDA- SP_RXD_N 2 7
PWRBTN_N 34 TMIN_SHIFT/GP014 REMOTE1- 43 SYS_THERMDA+ R2458 SP_DSR_N 3 6
R2448 1 2 10KR2J-3-GP FP_CBL_DET_PD 50 PWRBTN#/GP015 REMOTE2A+/REMOTE2B- 44 SYS_THERMDA- 75R2J-1-GP SP_DCD_N 4 5
PECI [4] PECI_CPU
R2449 1 2 10KR2J-3-GP PC_SPKR_DET_PD 54 FP_CBL_DET#/GP025
PC_SPKR_DET/GP031
REMOTE2A-/REMOTE2B+
76 36 PROCHOT#_EC 1 2 PROCHOT#_CPU_R SRN8K2J-4-GP
R2450 1 2 1KR2J-1-GP TRST_N 124 GP042 PROCHOT_IN#/PROCHOT_OUT#/GP016
R2452 1 2 10KR2J-3-GP SIO_SPKR 125 TRST# RN2402
3D3V_SB SPEAKER/DIAG_EN#/GP070 SP_RI_N
(R_) 1 8
LED
1

SP_DTR_N

NC#105
NC#107
NC#110
NC#112
2 7
NC#61
NC#62
NC#63
NC#64
NC#84
NC#85
NC#91

HVSS

AVSS
SP_CTS_N

CAP1
NC#5
NC#6

R2453 3 6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
[64] SIO_YELLOW 4 5
PU : Disable Pre-Post Diagnostic 10KR2J-3-GP
[64] SIO_GREEN
PD : Enable Pre-Post Diagnostic SCH5553-NU-GP SRN8K2J-4-GP
2

5
6
61
62
63
64
84
85
91
105
107
110
112

128

1
3
17
35
59
66
82
83
86
88
90
117

40

18
(071.05553.000E)
B B

Power Botton/Reset CAP_1

[20,64,99] PWRBTN_N
1

C2414
SC4D7U6D3V3KX-DLGP
2

KBMS
3D3V_S0
RN2405
SMB_CLK_MAIN 1 4
SMB_DATA_MAIN 2 3

SRN1KJ-7-GP

SCH5555(S) SCH5553(T)
R2462 10KR2J-3-GP
Pin 3 GP001 VSS SYS_FAN2_TACH_SIO 1 2

Pin 5 GP002 NC
R2476 10KR2J-3-GP
Pin 6 GP003 NC 20170421 SYS_FAN_TACH_SIO 1 2
remove SYS FAN
Pin 61 GP111 NC
R2463 10KR2J-3-GP
KBRST_N 1 2
Pin 62 GP112 NC
Pin 63 GP113 NC
12V_S5 12V_S5 5V_S5 R2464 10KR2J-3-GP
Pin 64 GP114 NC A20GATE 1 2
1

Pin 82 DDC_DAT_5V VSS 3D3V_S5


GP100 R2466 R2467 R2468
Place 10uF cap on V_3P3_A path R2465 30KR2F-GP
DDC_DAT_2P5V 20KR2F-L-GP 100KR2J-1-GP 16KR2F-GP PWR2_PRSNT 1 2
Pin 83 VSS
GP101
1

1
Pin 84 DDC_CLK_5V NC
2

GP102 Q2408 C2415 C2416 C2417 C2418 C2419 C2420 C2421 C2422 C2423 C2424 R2469 30KR2F-GP
Pin 85 DDC_CLK_2P5V NC 1 6 V5_ALW_MON_1 (R_) MB_REG_PG 1 2
2

2
GP103
Pin 86 GP104 VSS V5_ALW_MON_2 2 5 SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP SC10U6D3V3MX-DL-GP
1

R2470 30KR2F-GP
1

MEM_REG_PG
SCD1U16V2KX-3DLGP

Pin 88 GP106 VSS 3 4 R2472 C2426 1 2


1

6K8R2F-2-GP SCD01U50V2KX-1DLGP
1

Pin 91 PCIAUX_CTRL# NC C2425 R2471 MMDT3904-2-GP


2

GP124 1K65R2F-GP V5_ALW_MON R2473 30KR2F-GP


2

PCIAUX_GATE SP_TXD_N 1 2
Pin 92 GP125 Place these 0.1uF de-coupling caps on pin 22, 32, 45, 55, 60, 65, 77, 104,and 120
2

GP125
2

A A
Pin 105 GP053 NC
R2474 47KR2J-2-GP
GP055 RSMRST_SIO_N 1 2
Pin 107 NC The divider must give a voltage above 1.37V while V_5P0_A in the system is valid.
If V_5P0_A begins to fall unexpectedly, the V5_ALW_MON voltage must be below 1.11V
Pin 110 GP060 NC before V_3P3_A or SB3V become invalid to PCH R2475 100KR2J-1-GP
PCH_SIO_DPWROK 1 2
Pin 112 GP062 NC

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
SMSC 5555/5553
Size Document Number Rev
D Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 24 of 107
5 4 3 2 1
5 4 3 2 1

20170406
change to single 32MB SPI ROM

Vinafix.com 3D3V_SPI 3D3V_SPI


3D3V_SPI

1
20170419

1
D add for Edison's feedback D
R2502

1
R2501 C2501 20170419 1KR2J-1-GP
1KR2J-1-GP
(R_)
SPI ROM SC1U10V2KX-1DLGP add for Edison's feedback (R_)

2
U2501 R2507

2
SPI_CS_PCH_N0 33R2J-2-GP
[15] SPI_CS_PCH_N0 SPI_HOLD_PCH
RN2501 1 8 1 2
SPI_SO_PCH SPI_SO_ROM1 CS# VCC SPI_HOLD_ROM1 SPI_HOLD_PCH [15,23]
1 4 2 7
[15,23,91] SPI_SO_PCH SPI_WP_PCH 2 3 SPI_WP_ROM1 3 SO/SIO1 SIO3 6 SPI_CLK_ROM1 1 4 SPI_CLK_PCH
[15,23] SPI_WP_PCH SIO2 SCLK SPI_SI_ROM1 SPI_SI_PCH SPI_CLK_PCH [15,91]
4 5 2 3
GND SI/SIO0 SPI_SI_PCH [15,23,91,99]
SRN33J-5-GP-U RN2502
MX25L25673GM2I-08G-GP SRN33J-5-GP-U
(R_)

SSKT1
1 8
2 7
3
4
6
5
V3P3A_V1P8A_PCH_SPI
SKT-91960-0084L-GP
(R_62.10089.001) 3D3V_SB R2503 1 2 0R0603-PAD-2-GP-U 3D3V_SPI

SPI Socket
U2502
7 2
8 CS# VCC 1
9 SO/SIO1 SIO3 16
10 SIO2 SCLK 15
GND SI/SIO0
4
NC#4 5
NC#5 6
C C
NC#6 11
3 NC#11 12
20170515 RESET# NC#12 13
add 16 pin SPI ROM colay NC#13 14
NC#14

MX25L25673GMI-10G-GP

SSKT2
SPI_CLK_ROM1 16 1

SPI_SI_ROM1 15 2
14 3
13 4
12 5
11 6
10 7 SPI_CS_PCH_N0
9 8 SPI_SO_ROM1

SKT-SPI16P-7-GP
(X_)

B B

R2504 2 1 1K5R2F-2-GP 3D3V_S5


VCCRTC
R2505 1 2 45K3R2F-L-GP
TP2501 TP2502
VBAT1_R
1

R2506 1 2 1KR2J-1-GP VBAT1_L


VBAT1
A
1

1
+

BAT2501 BT2501 D2501 D2502 20170417-2


BATTERY CR2032 BAT-20-00950-1A01-A-GP-U RB551V30-GP BAT54C-12-GP change back to common part
(23.21012.001)
2

3P0V_BAT_VREG
3

VBAT2

20170512
change battery holder for Dell's request
20170522
change to 022.70007.0101 for EMN issue
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Flash&RTC
Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 25 of 107
5 4 3 2 1
12V_S0

CPU FAN CONTROL

1
R2601
4K7R2J-2-GP

2
3D3V_S0 20170410
change to common part
Reverse V : 20 V

Vinafix.com Forward V : 0.47V at 0.5A


Forward Curr. : 500mA
CPU_FAN_TACH_1 R2602 1 2 20KR2J-L2-GP CPU_FAN_TACH_SIO
CPU_FAN_TACH_SIO [24]

K
1

1
Source : 83.R5003.T8F
D2601 12V_S0 FANC1
R2603 RB551V30-GP 1 R2604
2K2R2J-2-GP 8K2R2F-1-GP
2

2
A
3 NP1
CPU_FAN_CTRL_SIO R2605 1 2 100R2F-L1-GP-U CPU_FAN_CTRL_CONN 4
[24] CPU_FAN_CTRL_SIO
BAOT-CON4-S5-GP
PWM:21-28KHz (021.60293.0104)

SYS FAN CONTROL 12V_S0

1
20170421
remove SYS FAN
20170606 R2615
Customer suggestion add SYS FAN 3D3V_S0 20170410 4K7R2J-2-GP
change to common part (R_)

2
Reverse V : 20 V
Forward V : 0.47V at 0.5A SYS_FAN_TACH_1 R2618 1 2 20KR2J-L2-GP SYS_FAN_TACH_SIO
Forward Curr. : 500mA (R_) SYS_FAN_TACH_SIO [24]

K
1

1
Source : 83.R5003.T8F
D2602 12V_S0 FANS1 R2617
R2616 RB551V30-GP 1 8K2R2F-1-GP
2K2R2J-2-GP (R_) (R_)
(R_) 2

2
A
3 NP1
SYS_FAN_CTRL_SIO R2614 1 2 100R2F-L1-GP-U SYS_FAN_CTRL_CONN 4
[24] SYS_FAN_CTRL_SIO
(R_)
PWM:21-28KHz FOX-CON4-S19-GP
(R_)

Thermal sensor G709


20170413
change thermal shut down solution

U2601 3D3V_S5

TH_SET 1 5
2 SET VCC 3D3V_S5
1

3 GND 4 R2612 1 2 0R2J-2-GP


R2611 OUT# HYST

1
9K53R2F-GP
(R_) G709T1UF-GP R2613
10K5R2F-GP 3D3V_S5
(R_)
2

(R_) U2602
[24] PCH_SIO_DPWROK 1 5 20170622

2
A VCC Add R2619 for PCH_DPWROK
TS_CRIT# 2
B
3 4
GND Y PCH_DPWROK [20]
SNLVC1G08DCKRG4-GP
(R_) R2619 100KR2J-1-GP
Modify circuit for thermal shutdown issue 1 2

(R_)

HS2601 HS2602 HS2603 HS2604 HS2605


FW part
GEN330R190-8-F-C-GP GEN315R158-8-F-C-S-GP-U GEN315R158-8-F-C-S-GP-U GEN330R190-8-F-C-GP GEN315R158-8-F-C-S-GP-U HS2606
GEN315R158-8-F-C-S-GP-U
FW P/N Location
3

BIOS1
3

4 4 4 4
1 1 6 3 1 1 4
1 BIOS FW P/N
U2502
5 8 5 8 7 2 5 8 5 8 (353.09Z02.0001)
5 8 LAN1

U3101
6

LAN FW P/N for Eagle SFF


6

(353.09Z01.0001)

LAN2
PCB2601
MAIN PCB M2601 M2602 M2603 LBL2601 LBL2602
348.09Z01.001B LABEL LABEL LAN FW P/N for Gambit MLK SFF
U3101
(40.3EQ13.011) (45.3E702.001) (GAM_353.06H01.B001)

Mylar CARD1 GASKET LAN ID : LAN ID :


F80F4105EB9A F80F4105EB9A
(340.08501.0001) (334.03A02.0001) (347.03801.0001)

20170523
H2601 change footpoint to ZZ.00PAD.DV1
Wistron Corporation
M2605 M2604 M2606 M2607 M2608 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
H2604 change footpoint to ZZ.AFEN8.190 Taipei Hsien 221, Taiwan, R.O.C.
Remove H2607 & H2608
Title

washer washer washer washer Spacer Thermal&FAN


(340.03A0A.0001) (340.03A0A.0001) (340.03A0A.0001) (340.03A0A.0001) (342.06701.0001) Size Document Number Rev
C Gambits MLK SFF A00
Date: Friday, February 02, 2018 Sheet 26 of 107
AGND
HP_OUT_R
HP_OUT_R [29]
HP_OUT_L
HP_OUT_L [29]

1
C2701
SC2D2U10V3KX-1DLGP-U AUD_LINE1_L
AUD_LINE1_L [30]

2
AUD_LINE1_R
AUD_LINE1_R [30]

1
C2702
SC2D2U10V3KX-1DLGP-U AUD_VREF

CPVEE
AGND

CBN
2

1
C2703
SC10U25V5KX-DL-GP 5V_AUD_S5

Vinafix.com AGND

CBP

2
D2701 3D3V_AUD_S0
1 2

1
AGND C2704 C2705
AZ5125-01H-R7G-GP SCD1U16V2KX-3DLGP SC10U25V5KX-DL-GP

36

35

34

33

32

31

30

29

28

27

26

25
1

1
5V_AUD_S5 (083.PJSD5.00A0) C2706 C2707 U2701

2
L2701 SC10U6D3V3MX-DL-GP SCD1U16V2KX-3DLGP

AVSS2

HP1-OUT-L_PORT-H-L

CENTER_PORT-G-L

LINE1-L_PORT-C-L

AVSS1
CBN

HP1-OUT-R_PORT-H-R

LFE_PORT-G-R

LINE1-R_PORT-C-R

VREF
CBP

CPVEE
1 2
5V_S5

2
MHC1608S800QBP-GP
1

20170419 C2710 AGND


remove Audio CEC circuit 37 24 SC10U25V5KX-DL-GP
HPVDD