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IC 77serviceman

IC 77serviceman

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Azhar Walet
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930 visualizzazioni70 pagine

IC 77serviceman

IC 77serviceman

Caricato da

Azhar Walet
Copyright
© © All Rights Reserved
Per noi i diritti sui contenuti sono una cosa seria. Se sospetti che questo contenuto sia tuo, rivendicalo qui.
Formati disponibili
Scarica in formato PDF o leggi online su Scribd
fe) fore) SERVICE A ON HF TRANSCEIVER IC-77 Icom Inc. INTRODUCTION This service manual describes the latest service infor- mation for the I-77 HF TRANSCEIVER at the time of publication. VERSION NO. VERSION SYMBOL #01 Philippines #02 Other To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 16 V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver DO NOT apply an RF signal of more than 20 dBm (100 mW) to thé antenna connector. This could damage the transceiver's front end. ORDERING PARTS REPAIR NOTES Be sure to include the following four points when ordering replacement parts: 10-digit order numbers Component part number and name Equipment model name and unit name Quantity required o> 1120000970 IC MS4562P IC-77 MAINUNIT Spieces 8810000230 Screw PHM3x6 IC77 Chassis 10 pieces Addresses are provided on the inside back cover for your convenience. 1, Make sure a problem is internal before disassembling the transceiver. 2. DO NOT open the transceiver until the transceiver is disconnected from its power source. 3. DO NOT force any of the variable components. Turn them slowly and smoothly. 4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments. 5. DO NOT keep power ON for a long time when the transceiver is defective. 6. DO NOT transmit power into a signal generator or a sweep generator 7. ALWAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment. 8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver. TABLE OF CONTENTS SECTION SECTION SECTION SECTION ‘SECTION SECTION SECTION SECTION SECTION SECTION 1 SPECIFICATIONS 2 DISASSEMBLY INSTRUCTIONS 3 INSIDE VIEWS. CIRCUIT DESCRIPTION RECEIVER CIRCUITS TRANSMITTER CIRCUITS. PLL CIRCUITS Loaic ciRCUITS . REGULATOR CIRCUITS. Beaeae ADJUSTMENT PROCEDURES PREPARATION BEFORE SERVICING. PLL ADJUSTMENT. RECEIVER ADJUSTMENT. ‘TRANSMITTER ADJUSTMENT gacoe 6 PARTS LIST. 7 MECHANICAL PARTS FRONT, CABINET PARTS AND ACCESSORIES CHASSIS PARTS BOARD LAYOUTS MAIN UNIT FRONT, VR AND JACK UNITS. PLL UNIT PA UNIT FILTER UNIT 9 BLOCK DIAGRAM 10 VOLTAGE DIAGRAMS. 10-1 MAIN, PA AND FILTER UNITS 10-2 PLLAND FRONT UNITS. 5-1tod 5-1 5-2 5-2 5-6 6-1t014 7-1to4 Tt 7-3 10-1to2 10-1 10-2 ECTION 1 SPECIFICATIONS GENERAL * Frequency coverage ‘Transmit 1.6050-1.9999 MHz 3.5000-3.9999 MHz 5,0000-7.9999 MHz 9.0000-28,0000 MHz 28.0000-30.0000 MHz (Except Philippines version) Receive 0.5000-30,0000 MHz + Mode Philippines version ‘888 (USB) Other versions Normal setting SSB (USB) Optional settings SSB (LSB), AM, CW ‘+ Number of channels 50 ‘= Antenna impedance 50.9 (nominal) ‘+ Usable temperature range 10°C to +60°C (+14°F to +140" F) ‘= Power supply requirement 13.8 V DC +1% (negative ground) ‘Current drain (at 13.8 V) Transmit Max. 208 Receive Squeiched 138 Max. audio output 2.1 A ‘= Frequency stability Philippines version Less than +20 Hz from 15 min. after power ON at O°C to +50°C Other versions Less than +200 Hz from 1 min. to 60 min. after power ON. Less than £30 Hz/hr. affer 1 hr. at +25°C Less than +350 Hz with temperature fluctuations of 0°C to +50°C * Dimensions 240 (W)%95 (H) «299 (0) mm 9.4 (W)x3.7 (H)X9.4 (0) in (Projections not included) * Weight : 8.9 kg (8.6 Ib) TRANSMITTER ++ Output power $88, CW 5-100 W AM 25 W (continuously adjustable) ‘+ Modulation system USB, LSB Balanced modulation AM Low power modulation * Spurious emissions Less than ~46 dB. ‘= Carrier suppression ‘More than 40 48 ‘* Unwanted sideband suppression: More than 50 8 ‘* Microphone impedance : 6009 RECEIVER ‘Sensitivity (Preamp ON) + USB, LSB, CW (12 dB SINAD) 1.6050-30.0000 MHz Less than 0.5 HV AM (10 dB SIN) 0.5000-1.6049 MHz Less than 12.6 wV 1,6050-30.0000 MHz Less than 2.0 pV ‘= Squelch sensitivity (Preamp OFF) : SSB, CW 5.6 BV Selectivity USB, LSB, CW More than 2.1 kHz/—6 dB Less than 4.0 kHz/—60 dB aM More than 6.0 KHz/—6 dB Less than 20.0 kHz/—40 dB ‘Spurious and image rejection ratio: More than 70 dB * Audio output power More than 2.6 W with an 8 Q load RIT variable range #12 kHz Al stated specifications are subject to change without notice or obligation. SECTION 2 DISASSEMBLY INSTR ire) NTS) 1. Remove 12 screws from the top and bottom covers, 2. Remove 11 screws from the PA unit cover. Fig. 1 [POWER] switch ‘bin, trom PA unit, W23 To remove the front panel: Unplug 8 connectors as shown in Fig. 4 and 5. 2. Remove 4 screws as shown in Fig. 3. 10 | 3. Unplug lead cable trom [POWER] switch Earth torminal, from MAIN unit, E12" 4, Remove 1 screw from J10 as shown in Fig. 3 Remove flat cables. © Pull out the connector tab. —- Re th @Remove the flat cable ot} leo __J3 (16pin) from FRONT unit, 43 $9 (16-pin) from FRONT unit, Jt 410 (16-pin) from FRONT unit, J2 S11 (ain) from FRONT unit, P2 J15 (4-pin) from JACK unit, Pt J16 (pin) trom Speaker (SP1), Pt J12 (16-pin) from VR unit, P2 J7 in) from FRONT unit, PS 24 SECTION 3 INSIDE VIEWS ¢ PLL, PA AND FILTER UNITS PA unit FILTER unit Predrive amplifier (Qt: 28C1971) . 7 Tx/Rx switching relay Dive amplitisr (RL13: DS-M-0C 12 V) (Q2, Q3; 2803133) Final amplifier SWR detector circuit (Q4, Q5: 2862904) Bias voltage controler Tx low-pass filters (Q6: 25D1406 ¥) Reference crystal &X1: CR-337 32,000 MHz #02 ( CR338 #01 } The photo shows GR-337 114 divider (\C2; TOT4ACT4F) VCO circuit PLL unit 1/2 divider (IC4: TC74AC390F) DDS circuit PLL IC : (106: SC-1246) (IC3: CXD1225M-1) 5 V regulator (C1: TA7805F) ¢ MAIN UNIT Ceramic filter (F12: CFW45SHT) 7 AF power amplifier J (106: pPC1241H) fe-—— —5 V DC-DC converter circuit Rx preamplifier: (Q22, Q23: 28K2171) Rx 3rd mixer (C10: pPC1037H) Tx 2nd mixer (Q2, Q3: 3SK126) ‘Space for CW-N 3rd IF filter (FL-52A or FL-53A option) Rx 1st mixer (Q26, Q27: 25K2171) USB - LSB + CW 3rd IF filter F13: FL-65) 1st IF filter ‘ ) (FIV: FL-197) 8 V regulator Rx 2nd/Tx 1st mixer (C17: NUM7808A) (D124: ND433G) ECTION 4 CIRCUIT DESCRIPTION 4-1 RECEIVER CIRCUITS 4-1-4 RF SWITCHING CIRCUIT (FILTER AND MAIN UNITS) ‘The RF switching circuit leads receive signals to bandpass fiers from the antenna connector while receiving. While transmitting, this circuit leads the signals from the RF power amplifier to the antenna connector. This circuit includes a 20 dB RF attenuator circuit to prevent distortion from very strong signals, RF signals from the antenna connector pass through the transmivreceive switching relay (RL13) and low-pass fiter (L14, C14-C16), and are then applied to the MAIN unit via 2 (MAIN unit: 2). ‘The signals from the FILTER unit are either bypassed or are attenuated at the 20 dB attenuator (R99, RL). There are no non-linear components from the antenna connector to the attenuator in this circuit construction. Therefore the attenuator effectively prevents distortion caused by strong signals, The signals are then applied to AF fiters. 4-1-2. RF BANDPASS FILTER CIRCUIT (MAIN UNIT) RF bandpass filters pass only the desired band signals and suppress any undesired band signals. ‘The RF circuit has 7 RF bandpass fiers (BPF) for signals above 1.6 MHz and 1 low-pass fiter (LPF) for signals below 1.6 MHz, The signals pass through the low-pass or one of the bandpass filters depending on their frequencies. (1)0.5-1.6 MHz These signals pass through a low-pass iter (L28, L29, C84-C86) to suppress unwanted frequencies. The fitered signals are bypassed a preamplifier by a BPF control signal (G0) and preamp switch (Q21), and are then applied to the 1st mixer circuit (026, G27), (2)1.8-2.0 MHz These signals pass through a bandpass filter (L35-L39, C92-C99) to suppress unwanted frequencies. The fitered signals are then applied to the preamplifier circuit. (3)2.0-30.0 MHz These signals pass through a high-pass fier (L33, L94, C89, C90, C359, C367) to suppress strong signals below 1.6 MHz, such as from broadcasting stations. The filtered signals are applied to one of 6 bandpass fiters depending on thelr frequencies and are then applied to the preamplifier circuit USED RF FILTER Te ECE eran pan Feat | ome || °° [Sout | oon los-1.6MH2| 60 | Das |[earwiz | Ba | Dasa 16-2MHz| BT | 038 [11-15 MHz] BS | Dasp 2-4MHz | 62 | Data |[15-20MHz| BS | Daga amnz | 63 | Datb |[22-s0MHz| 67 | Davo 4-1-3 PREAMPLIFIER CIRCUIT (MAIN UNIT) The preamplifier circuit uses two 2SK2171s to obtain 10 dB of gain over a wideband frequency range. When the preamplifier is turned ON, the signals above 1.6 MHz are applied to the preamplifier circuit. Q22 and Q23 are connected in parallel to easily match the impedance to 509. Q24 and Q25 switch the signals from a bandpass fier, either to be bypassed, or to be applied to the preamplifier, depending on the [PREAMP] switch condi- tion. ‘Amplified or bypassed signals are applied to the 1st mixer circuit (026, 227). 4-1-4 1ST MIXER CIRCUIT (MAIN UNIT) The 1st mixer circuit mixes the receive signals with the tst LO signal to convert the receive signal frequencies to a 64.455 MHz 1st IF. ‘The signals from the preamplifier circuit, or signals which bypass the preamplifier, pass through a low-pass fiter. This low-pass filter suppresses signals above 30 MHz to elimi nate direct receiving of signals at 64.455 MHz and image interference at 190-160 MHz. The signals are then applied to the 1st mixer (226, 027). ‘The 1st LO signal (64.9595-94.4565 MHz) enters the MAIN Unit from the PLL unit via P1 (PLL unit: J4). The LO signal is amplifed at QS and then applied to the 1st mixer. ‘The 1st mixer (226, Q27) uses two 2SK21718 to produce high level mixing with a high intercept point. EXACT 1ST IF FREQUENCY ‘MODE FREQUENCY (MHz) USB 64.4565 1sB 64.4535 cw 64.4541 ‘AM, CW.N 64.4550 4-1-5 1ST IF CIRCUIT (MAIN UNIT) The 1st IF circut fiters and amplifies the 1st IF signals. The 4st IF signals from the 1st mixer circuit are applied to MCF (Monolithic Crystal Filter; FI1) to suppress. out-of-band signals, The passband width of Ft is +7.5 kHz/—6 dB. ‘The fitered signals are applied to the 1st IF amplifier (228), AGC voltage Is supplied to the 2nd gate of 028. 4-1-6 2ND MIXER CIRCUIT (MAIN UNIT) ‘The 2nd mixer circuit mixes the amplified 1st IF signals and 2nd LO signal (64,00 MHz) to convert the 1st IF to a 2nd IF. ‘The amplified 1st IF signals trom Q28 are converted to 455 kHz 2nd IF signals at the 2nd mixer (D124). D124 is a DBM (Double Balanced Mixer). The 2nd LO level is approx. 0 dBm. ‘The 2nd IF signals are applied to Fiz to suppress undesired signals such as the 2nd LO signal, and are then applied to the noise blanker gate (010, D11). EXACT 2ND IF FREQUENCY MODE FREQUENCY (kHz) USB 4565 tsB) 4535, cw. 4544 AM, CWN 455.0) -7 NOISE BLANKER CIRCUIT (MAIN UNIT) The noise blanker circuit detects pulse type noise, and turns OFF the signal line when noise appears, ‘The 2nd IF signals from FI2 are applied to the noise blanker gate (010, 011), A portion of the signals from Fi2 are amplified at the noise amplifiers (Q10, Q12, Q13), then dotacted at the noise detector (015). The detected signal from the noise detector is applied to the noise banker switch (238). A portion of the detected signals from the nolse detector is applied to the noise AGC circuit (Q11, Q37, C211, R59, 214) to control the bias voltage of the noise amplifier (Q10, a12), ‘The threshold level of the noise blanker switch (Q39) is set at 0.9 V. When the detected voltage exceeds the threshold level, Q40 outputs a blanking signal to close the noise blanker gate (010, D11), depending on the pulse noise period ‘When the operating frequency is changed, the "DNB" signal line becomes "LOW," turning Q40 ON through 072. In this case, the noise blanker gate prevents PLL click noise. 4-1-8 2ND IF CIRCUIT (MAIN UNIT) ‘The 2nd IF circuit amplifes and fiters the 2nd IF signals. The signals passed through the noise gate (D10, D11) are amplified at Q9. AGC voltage is supplied to the 2nd gate of a8, When SSB or CW mode is selected, the amplified signals pass through FI3 (FL-65). When an optional CW narrow fiter Is installed and CW-N mode is selected, the signals pass through the CW narrow filter. When AM mode is selected, the signals bypass the 2nd IF fiter. ‘The fiters are selected with mode selecting signals (SSB-CW, AM, CW-N) and the "T8V" vottage line. The fered signal is amplified at Q44-Q46 to obtain a detectable level. AGC voltage is supplied to the 2nd gate ot Q46. A thermistor (R228), connected to the gate of Q45, Improves the temperature characteristics of the receiver gain. R230 adjusts the receiver gain. Output signals from O45 are applied to the SSB/CW detector. Output signals from 44 are shared between the [AM detector and AGC detector. 4-1-9 BFO CIRCUIT (PLL UNIT) BFO (Beat Frequency Oscillator) frequency is used at the 'SSB/CW detector and the balanced modulator. The IC-77 uses a PLL circuit for the BFO circuit. ‘The oscillated signal at the VCO (15, 45.33-45.85 MHz) is butfer-ampliied at Q16 and applied to the divider (IC). The signal is divided by 2 at IC4 and is applied toa PLL IC (ca). The signal is divided at the programmable divider section in IC3 and is then phase detected at the phase comparator section with a 5 kHz relerence frequency. The phase detected signal is output from pin 7 and is then converted to a DC voltage (lock voltage) by the active loop fiter (213, Q14), The lock voltage is applied to the varactor diode (03) in the VCO circu to change the capacitance of the diode and control the oscilation frequency. ‘The oscillating signal is then butfer-amplified at Q16, divided by 100 at IC4, fitered by the low-pass fiter (L14, L15, C51-C55), and finally applied to the product detector (MAIN unit IC10) for receive demodulation, BFO FREQUENCY IN EACH MODE FREQUENCY (kHz) oe RECEIVE TRANSMIT use, 2565 1s. 4535 ow. 4533 aaa Cw 456.2 455.0 ‘AM NO OUTPUT 455.0 4-1-10 SSB/CW DEMODULATOR CIRCUITS (MAIN UNIT) In SSB or CW mode, the 2nd IF signal trom the IF amplifier (Q45) is mixed with the BFO signal trom the PLL unit at the product detector (IC10) to demodulate the 2nd IF signal into an AF signal. The detected signal (AF) from IC10 (pin 3) is applied to the AF input mode selector switch (IC5). 4-1-11 AM DEMODULATOR CIRCUITS (MAIN UNIT) In AM mode, the 2nd IF signal from the buffer amplifier (Q44) passes through C198 and is detected at D71. The detected signal (AF) is then applied to the AF input mode selector switch (ICS). 4-1-12 AF INPUT MODE SELECTOR SWITCH (MAIN UNIT) ‘Tne AF signal from one of the detector circuits is applied to the AF input mode selector switch (IC5). ICS consists of 4 analog switches which are selected with a mode signal and the squelch control signal. The AF signal is output from IC5 (pins 1, 4) and then applied to the AF amplifier circut. 4-1-13 AGC CIRCUIT (MAIN UNIT) The AGC (Automatic Gain Control) circuit reduces IF amplifier gain to keep the audio output at a constant level. ‘The receiver gain is determined by the voltage on the AGC line (Q33, collector). The voltage Is usualy set by Dé4 and the resistance ratio of A171, R172, R174 and R176. ‘The 2nd IF signal from the butter amplifier (Q4) is detected at the AGC detector (D65) and is then applied to the DC amplfier (233), _— 5 V is applied to the Q33 emitter to activate the AGC line with minus voltage. When receiving strong signals, the detected voltage in- ‘creases and the voltage of the AGC line decreases via the DC amplifier (033). As the AGC line is used for the bias voltage of the IF amplifiers (Q9, 028, 046), IF amplifier gain is decreased. When the strong signal disappears, the AGC line voltage is released by C175 and R170 in CW mode to obtain a fast AGC release time. In SSB or AM mode, C174 and R169 {are connected in parallel to obtain a slow AGC release time. 4-1-14 S-METER CIRCUIT (MAIN UNIT) The [Link] circuit indicates the relative received signal strength while receiving by utilizing the AGC voltage which changes depending on the received signal strength. The AGC bias voltage (time constant line) is applied to a differential amplifier (IC9 pin 6) where the difference be- ‘ween the bias and reference voltages is detected. ‘The resulting S-meter signal Is applied to the A/D converter section in the CPU (FRONT unit IC1 pin 98) and the S/RF Indicator displays the relative signal strength. The refer- ence voltage is adjusted with R175. 4-1-15 SQUELCH CIRCUIT (MAIN UNIT) The squelch circuit mutes audio output when the S-metor signal is lower than the [SQL] control setting level ‘The S-meter signal from IC9b (pin 7) is applied to the ‘comparator (IC8a pin 2) through D63 to be compared with the threshold level set by the [SQL] control. When the S-meter signal is lower than the threshold level, the comparator becomes “HIGH” and Q32 tums ON to deactivate the AF input mode selector switch (IC5 pins 5, 13). This cuts the AF signal OFF. This signal is then applied to Q31, turning OFF the [RX] indicator, and is also applied to the [MIC] connector (pin 4) and [ACC(1)] connec- tor (pin 6). AF CIRCUIT Demodulator ‘cone [AF input mode selector swich cs _f fl ee ee AE ee cemegell lia 3 AF preampliier: fier ameter mal 4 Bs detector ed er 2 8 CW site tone Als 1- al mA | “9 4-1-16 AF AMPLIFIER CIRCUIT (MAIN UNIT) ‘The AF amplifier amplifes the AF input signal to a suitable driving level for the speaker. ‘The AF signal from the AF input mode selector switch is applied to the AF preamplifiers (34, Q35). The CW side tone signal is applied to 034. ‘The amplified signal is applied to the [AF] control (RY on the [AF unit) and then to the 2.3 kHz cut-off active low-pass fiter (036). The AF signal output from 36 is power-ampliied at [C6 to drive the speaker. 4-2 TRANSMITTER CIRCUITS 4-2-1 MICROPHONE AMPLIFIER CIRCUIT (FRONT AND MAIN UNITS) The microphone amplifier circuit amplifies the microphone input signals and outputs the amplified signal to the bal- anced modulator. ‘Aucio signals from the [MIC] connector are adjusted at the {MIC} control (FRONT unit R61) and amplified at IC18¢ and (C1 (MAIN unit). External modulation input trom the [ACC(1)] socket (pin 4) is also applied to 1C18¢ via R341 (MAIN unit). The microphone bias voltage is supplied from the € Vine via R62 and R63 (FRONT unt). In AM mode, the maximum level of the IC18 output is limited by the ALC circuit (IC184, 057, D91). The maximum modulation level is set by R300 (MAIN unit). 4-2-2 BALANCED MODULATOR (MAIN UNIT) ‘The balanced modulator converts the AF signal from the microphone amplifier to a 455 kHz IF signal with a BFO signal. ‘Output signals from the microphone amplifier and the CW keying signal are applied to the balanced modulator (IC11 pin 5), The BFO signal from the PLL unit is applied to IC11 (pin 7) as a carrier signal IC11 is a double balanced mixer IC and outputs a double side band (DSB) signal with ~ 40 dB carrier suppression. F251 and R253 adjust the balanced level of IC11 for maximum carrier suppression. In CW mode, the CW keying signal upsets the balance to create a cartier signal. In AM mode, Q75 and R407 upset the balance to create an AM cartier signal -2-3 CW KEYING CIRCUIT (MAIN UNIT) ‘The CW keyer is connected to Q68. When the CW key is closed, 8 V is output from 68 and this voltage controls break-in operation, the side tone signal and the transmit signal The 8 V from Q68 is applied via D106, D101 and D102 to the balanced modulator (IC11) to unbalance the IC11 input bias voltage and create a carrer signal. R331 determines the transmit delay timing, (1) BREAKIN The IC-77 Is automatically set to transmit by CW keying. ‘The 8 V from Q68 is applied to the base of Q66 via Q67. When the key Is closed, Q66 grounds the SEND line for transmitting. ‘The transmit release delay time is determined by C290, R35 and R336, (2) SIDE TONE When the CW key Is closed, the side tone circuit (464) coscilates and sends the signal to the AF circuit. Normally, D100 Is ON, and C285 is connected to the Q64 collector so that no oscillation occurs. When the CW key is closed, the 8 V from Q68 via D101 give D100 reverse bias to disconnect C285 from G64. ‘64 then oscillates with 800 Hz as a side tone signal. R328 prevents side tone click noise. (3) KEYING Keying is controlled at 2 points in the IC-77. The balanced mixer (IC11) stops the carrier output by recovering the balance of the input bias voltage. Q7, located at the 2nd IF mixer (D124) input, cuts the signal line, €287, R330 and A331 determine the voltage wave form to IC11 (pin 6) to produce the keying wave form. 4-2-4 IF AMPLIFIER (MAIN UNIT) ‘The SSB/CW 455 kHz IF signal passes through FI3 (FL-65) to suppress unwanted sideband signals, then the signal is applied to a transmit IF amplifier (Q8). The optional CW narrow fier is not used in transmitting The amplified signal from Q8 Is mixed with the 2nd LO signal and converted to a 64.455 MHz IF signal at D124. D124 is used in receiving and transmitting. The AM signal bypasses FI3, is amplified at QB and is then applied to D124. ‘The 64.455 MHz IF signal is fitered at FI1, amplified at the IF amplifier (Q4) and is then converted to the displayed frequency at the balanced mixer (Q2, Q3) with the 1st LO signal. The gates of the IF amplifers (24, Q8) are controlled by ALC bias voltage from the ALC circuit. A thermistor (R41), connected to the gate of Q8, improves the temperature characteristics of the transmitter gain. A36 adjusts the total transmitter gain. 4-2-5 RF CIRCUIT (MAIN AND PA UNITS) ‘The RF power signal level is detected at D8 (FILTER unit) and applied to the MAIN unit as the “FOR” voltage. The displayed frequency signal converted at the balanced mixer (MAIN unit Q2, Q3) is applied to the bandpass fiter_ The “FOR voltage from the FILTER unit is applied to IC1S> (L3-L5, C3-C7, C9, C10) where unwanted LO signal (pin 6) in the MAIN unit. The *POC" voltage, set by the [AF emission is reduced. ‘The fitered signal is amplified at Q1, PWR} control (FRONT unit R60), is applied to IC1b (pin 5) and is then applied to the PA unit via the attenuator. as the reference voltage. ‘The signals trom the MAIN unit are amplified at the predriva When the “FOR' voltage exceeds the “POC voltage, ALC amplifier (Q1), drive amplifier (Q2, Q3) and power amplifier _bias voltage from IC15b (pin 7) controls the IF ampliers (@4, 25) in the PA unit to obtain a stable 100 W of RF (Qs, Q8). This adjusts the output power to the determined output power. level by the [RF PWR] control until the “FOR” and "POC" voltages are equalized. The predrive amplifier is a class A amplifier with a Voc of 13.8 V. The drive amplifier is a class AB push-pull amplifier In AM mode, Q48 turns ON and C256 is connected to the With a Vec of 13.8 V. Dt controls bias voltage to the drive "FOR" voltage line to obtain an averaging ALC operation. ampitfr. Q47 tums ON and the "POC" voltage is shifted for 40 W AM output power (maximum) through R274. ‘The impedance of the signal from the drive amplifier is converted at L2, then the signal is applied to the power An external ALC input from the [ACC(1)] or [ACC(2)] socket amplifier (Q4, Q5), The power amplifier is a class AB or the {ALC} jack Is applied to the butter amplifier (Q50). push-pull amplifier and amplifies the input signal to 100 W. ‘External ALC operation is identical to that of the internal 2 and D3 control bias voltage to the power amplifier. The ALC. signal from the power amplifier is applied to one of the low-pass fiters in the FILTER unit. 4-2-8 APC CIRCUIT (MAIN UNIT) 4-2-6 LOW-PASS FILTER CIRCUIT The APC (Automatic Power Control) circuit protects the (FILTER UNIT) power amplifiers on the PA unit from high SWR and excessive current. The low-pass fiter circuit consists of 6 Chebyschev low- pass fiters to suppress the higher harmonic components. A reflected wave signal appears and increases on the ‘The signal trom the power amplifer (Q4, QS) is applied to antenna connector when the antenna is mismatched. D9 of ‘one of the low-pass filters (depending on its frequency). the SWR detector crcutt(L13, D8, D9) in the FILTER unit The fier switching voltage from the MAIN unit (J4) is detects the signal and applies it to 1C14a in the MAIN unit applied to the FILTER unit via P1 as the “REF” signal The fitered signal passes through the SWR detector circuit When the "REF" signal lovel increases, IC14a decreases (L13) and is then applied to the antenna connector. the IALC line voltage via F264 to activate the ALC. For the IC APC, the power transistor current is obtained by 4-2-7 ALC CIRCUIT (MAIN UNIT) detecting the voltages CICH” and “ICL") which appear at both terminals of a 0.012 Q resistor (PA unit R25). The The ALC (Automatic Level Control) circuit controls the gain detected voltage Is applied to the differential amplifier of IF amplifiers in order for the IC-77 to output a constant —_(IC15a pins 2, 9). When the current of the final transistors RF power set by the [RF PWR] control even when the Is more than 22 A, IC1Sa controls the ALC line Via D86 to supplied voltage shits, ete. prevent excessive current flow. ALC CIRCUIT ou, Alc votage awe ‘ooeane se -sv REF votage _A boo ~ av ‘Ecemal ALC 45 During tuning of an antenna with an optional AT-130, the “PODN" signal tums Q51 ON. As a result, the "POC" voltage is shifted for approx. 10 W output power. 4-29 TEMPERATURE PROTECTION CIRCUIT (MAIN UNIT) A cooling fan (CHASSIS unit MF1) is activated while trans- rmitting or if the temperature of Q4 exceeds the preset value. While transmitting, PATS voltage is provided to MF1 via 29, Thermistor R29 on the PA unit detects the temper- ature of Q4, If the Q4 temperature is more than 50°C (122 ‘F), R29 becomes very low Impedance and keeps Q73 and Q74 (MAIN unit) ON to rotate the cooling fan at high speed = even when the transcelver condition has changed from transmit to receive. 4-210 RF METER CIRCUIT (MAIN UNIT) ‘The “FOR” voltage from the FILTER unit is applied to the AF meter amplifier (IC14b pin 5). The amplified voltage is output from IC14b (pin 7) and then applied to the A/D converter section of the CPU (IC1 pin 99) in the FRONT Unit, R268 adjusts the meter sensitivity and R273 and C254 are used for RF meter peak power hold. FREQUENCY CONSTRUCTION 4-3 PLL CIRCUITS 4-3-1 GENERAL DESCRIPTION ‘The PLL unit contains 2 PLL circuits for generating a tst LO signal (64.9595-94.4565 MHz variable) and a BFO fre- quency (453.3-456.5 kHz). The 1st LO PLL employs a 1 loop DDS PLL whose reference oscillator is also used as the 2nd LO signal (64.00 MHz fixed). The DDS (Direct Digital Synthesizer) circuit performs signal sampling, gener- ation of digital sine wave and digital phase detection 4-3-2 1ST LO CIRCUIT (PLL UNIT) The PLL contains 4 VCO circuits for all HF band coverage Within 10 Hz steps (100 Hz step by programming and 10 Hz by an RIT). One of four VCO oscilation signals is butfer- amplified at Q26 and ts then amplified at Q29, Q32 and (Q30. The resulting signal is applied to the DDS IC (C6). The DDS IC outputs pulsetype signals. The signals are applied to the active loop fer (IC5) to be converted to a DC voltage (lock voltage), The lock voltage Is applied to the varactor diodes (04-07) in the VCO circuits to change the capacitance of these diodes and control the oscillation frequency. The VCO Circuits are switched by the VCO switching signal ("'VCO1"— "VCO4") from the DDS IC. The VCO oscillating signal is then butter-amplfied at the buffer amplifier (Q26), ampitied at Q27 and Q28, and finally applied to the MAIN unit as a tst LO signal. ToAF ret aw unit PLL unit 4530. as05 mH 4-3-3 REFERENCE OSCILLATOR CIRCUIT (PLL UNIT) The reference oscillator circuit consists of Q9 and Xt. A 32.00 MHz reference frequency is oscillated to produce a 2nd LO signal, DDS reference frequency and BFO PLL reference frequency, The reference frequency is applied to the DDS IC (IC pins 40, 41). The reference frequency is amplified at Q11 and is then divided by 4 at IC2, The 8.00 MHz frequency is divided by 1600 at the BFO PLL IC (IC3) to obtain the 5 kHz PLL reference frequency. The 32,00 MHz reference frequency Is multiplied by 2 at Q10 to obtain the 2nd LO signal. The resulting 64.00 MHz 4-4-3 CPU (LOGIC UNIT) ‘The CPU (IC1) contains an 8-bit CMOS CPU, a 32k-byte ROM, a tk-byte RAM and an LCD driver. A 9.8304 MHz clock is used for rapid operation. The CPU controls the ‘operating frequency, mode, function display, etc. The memory channel information is stored in the CPU using a lithium backup battery which has a normal life of more than 5 years. ‘The cloning function allows the IC-77 to transfer pro- ‘grammed memory contents to another IC-77. The Icom CIV network system allows the IC-77 to be remotely controlled by a personal computer using an RS-232C jO port. signal is fitered at the bandpass filter and is then applied to INPUT PORT ALLOCATIONS the MAIN unt via P1|as the 2nd LO signal Pa PORT NAME| i IN DESCRIPTION itv 1 Input po forthe detection of rt poston, 4-4 LOGIC CIRCUITS eee ‘Aves, Avec |2,69 | Input reference votagos for 4-4-1 BAND SELECTION DATA internal A/D converters. (MAIN AND PLL UNITS) osct, 7,8 | WO ports for the CPU clock osc2 osclation To solect the correct bandpass fiter and iow-pass fiter, the CPU outputs the following band selection data from the /O RES 9 Input port for the reset signal. der (MAIN unit C3) depending on th Ce ead at etal civck 84 Input port for busy signal of the sath CLV bus line. This port becomes HIGH" The VCO selection data is output tom the DDS IC inthe pseeratic ae PLL unit. The band voltage is produced at R966-R76 and R978 (MAIN unt), cM @5 | inputpor for the CLV data BAND SELECTION DATA BAKUP | 88 | Detects he power vottage. ae a Wen the signal is “LOW,” the PU Is backed up. (MHz) BPF voitace| LPF | VOO oe z oss | 2 | yy | a KAO-KRS | 90-89 _ | Input ports for tum signals of eter the key matrix 2.0-3.99999 B2 61V w weod KEY 94 Input port for ae antenna tuner (AT-120), This Sete cay e port becomes "LOW" while an 3.0-10.00909. textemal antenna tuner Is 11.0-14,99999 BS 44V a oe tuning. 15.0-21.99999 86 32V 5 | vco3 TRC 95 Input port for transmitireceive 22.0-80.00000 | 87 | 22v | ts | vcos switching signal. This port becomes HIGH" while transmiting, SQLS [96 | input por forthe squelch 4-4-2 RIT CONTROL (FRONT UNIT) signal. This port becomes LOW" when squelch Is open ‘The [RIT] contro! shits the “RIT vottage in order to shit Suv 98 | tnput por forte detection of the receive frequency. The voltage is applied to the AD the received signal strength, converter section of the CPU (IC1 pin 1). The CPU shifts over Pov 99 | inputpor forthe detection of the Nedata forthe DDS IC. oa micy [100 | input por for the detection of [UP//[DN] switch access. ‘+ OUTPUT PORTS PORT NAME| Juin DESCRIPTION NUMBER STAR 14 ‘Outputs a control signal for the external antenna tuner (AT-130). Detects the Connection of the external antenna tuner. CONO- | 15-17 _ | Output control signals for the Gon2 DDS IC. RES 18 ‘Outputs a reset signal forthe DDS IC. ck 19 ‘Outputs a clock signal for the DDS IC, PLL IC and output expanders, PLE 20 ‘Outputs an enable signal for the PLL data, DATA 21 ‘Outputs serial data to the DDS IC, PLLIC or output expander. DSTB 22 ‘Outputs a strobe signal for the DDS IC. PSTB 23 ‘Outputs a strobe signal for the BFO PLL BSTB 2 (Ouiputs a strobe signal for the output expander (|C3) which outputs band signals. MSTB 5 ‘Outputs a strobe signal for the ‘output expander (\C8) which ‘outputs mode selection signals. KSTB 26 ‘Outputs a strobe signal for the ‘output expander (\C6) which ‘outputs key matrix strobe sig- nals, comi— | 35-32 | Output LED common signals. coms SEGI- | 36-73 _| Output LCD segment signals. SEG38 POON |77 ‘Outputs a control signal for setting the tuning output power of the AT-190. BEEP 78 ‘Outputs a 1 KHz or 500 Hz beep tone, PREV 79 ‘Outputs a control signal for the preamplifier cicut. ATV 0 ‘Outputs a control signal for the AF attenuator circu. NBV at ‘Outputs a control signal for the noise bianker circu. SEN 2 ‘Outputs a control signal for tuning transmission. civo 7 ‘Output por for the CI-V data. 4-4-4 KEY MATRIX (FRONT UNIT) ) em fro, pacuet | cionng ones (Poor (Pea Progam arn A mooe | omtom Sen (Pav wer (scam we wen ey mover woex ese ss (aay T 4-5 REGULATOR CIRCUITS Ether +8 V, +5 V or —5 V DC Is supplied from a corresponding regulator circuit. +8 V, +5 Vand - 5 VDC are regulated at the following circuits using 13.8 V DC. (1) +5 V REGULATOR (FRONT UNIT) +5 V DC Is provided by a three-termi (C4), (2) +8 VREGULATOR (MAIN UNIT) +8 V DC is provided by a three-terminal voltage regulator (c17). I voltage regulator (3) 5 V REGULATOR (MAIN UNIT) IC16 generates a negative pulse-type voltage by converting the DC input to AC voltages (approx. 6.7 kHz) as a mult-vibrator. The voltage Is rectified at D80 and D8t, regulated by a Zener diode (D82) and C249, and is then applied to the MAIN and PLL units. SECTION 5 ADJUSTMENT PROCEDURES 5-1 PREPARATION BEFORE SERVICING WREQUIRED TEST EQUIPMENT EQUIPMENT GRADE AND RANGE EQUIPMENT (GRADE AND RANGE DC power supply | Output voltage» 188 VDE ‘AC mllivotimeter | Measuring range > 10 mV-10V Current capacity: 30 or more ‘DC voltmeter Input impedance: 60 KA/D0 or better RF power meter | Measuring range = 10-200 W — Ilcoeinerant Gapsblag=A'and 30h (terminated type) | Frequency range: 1.8-30 MHz — ——— peoance 500 “Audio generator | Frequenoy range: 900-8000 WHE, SWR Less than 12:1 Output level 4-500 mv Frequency counter | Frequency range > 01-100 MHz “Attenuator Power attenuation: 60 oF 60 dB Frequency accuracy | £1 ppm or better Capacity 150 W oF more Sensitity 100 mv orbetter__[ Spectrum analyzer | Frequency range: Atleast 90 MHz AF voltmeter Frequency range: 0.1-100 MHz Spectrum bandwicth : +100 kHz oF more Measuring range: 001-10 Fit deviation meter | Frequency range: Atleast 20 MHz Digital multimeter | Input impedance = 10 MQ/DC or better Measuring range: Oto £10 KHz ‘Standard signal | Frequency range: 01-100 MHz Modulation analyzer | Frequency range: Atleast 30 MHE generator (5G) | Output level 0.1 w=? mv Measuring range: 0-100% (127 to —17 d8m) | Eaemal speaker | Impedance 8a Distortion meter | Frequency range: 1 KHz£10% Max. input power: 5 W Measuring range: 1-100% Oscioscope Frequency range: DO-20 MHz Measuring range: 0.01-10V (GW: Clockwise CCW: Counterclockwise CONNECTION FM deviation ‘Attenuator meter 50 or 60 dB ‘Modulation analyzer ‘Standard signal snerator RF power meter 200 Wi50. to [KEY] CAUTION: DO NOT connect the signal generator while transmitting. to[00 138) tothe fant] to (EXT SPI connector DC power supply 13.8 VI30 A. ac rmillvoltmetat sonte J} “Microphone connector, (Front pan view) Pint ‘Mic INPUT Pin 7 GND (Microphone: ‘ground) tormig, 5-2 PLL ADJUSTMENT MEASUREMENT ‘ADJUSTMENT aowsrment | — ADJUSTMENT CONDITIONS vawue unt | LocaTion unit ] aowusr Terenence | 1 |-Dipmyed vonenan verano wre | PLL |ommoctte [Preseocoweres | ru | cre Freauency | |Siose tsa Vemenoycouner | srown beer “mate Pt woh «501 ois oer Receiving ‘ 2 ecoo00 we mi 3 Cannes ne | Maxim eve ea vote oP 1 | Ateraduorent remove th eo or P1 and voug PI Groru | 1 |Dapaye roqunoy 40000 mre] PLL [oomea ne aga [19¥00 me | oe tox Sve ise mute Voctace | | Rectvng Ceatoscpe to 10 ocx | 1 | oily renenar 70090 nz | PLL [Gomer tne aptar [oovoo mu | oe vottnce |" |SMoce ise radio eer soatooope to sr 2 | ebiplye rear: 148860 MH ove on 3 | eDiaye requny:21 8880 Hz cove oe 4 | -Diayd reqeny:30 0000 wre sovoe cae 5 | eDiiayea reqvncy Wow wan n7 VOU very S00 wn 000 Me, 1500 Mean 220000 MH 5-3 RECEIVER ADJUSTMENT MEASUREMENT “non aowstuent | AnwustMeNT conorTions vawe uw | Locanion uw | aowsr TOTAL GAN] 1 | imiyedvesooy. 121000 Mrz | Rear comeot the AC | Manimum aude out | WAN [Ads size se pone |mtvotret' tothe | ee owes Sinttewen RF (eer oey ce wih tur, SINelowten “OEE trea tre, ta, “Ione ap} owtch OFF tar 0 5 Conoat ho S86 the ANT] comes rst Treavenoy: 141010 MH tore” koqe(et0r am) Modulation’ OFF recor 2 | +See 956 as cows orarieve | wan | was0 {ete 0m (47 dBm) siterrce wore ‘This output level of the standard signal generator (SSG) is indicated as SSG's open circult. © PLL UNIT L4 Reterence frequency: adjustment R187 Lock voltage ‘check point P1 Reference trequency- C86 ‘check point C16 Reterence frequency C78 | Lock voltage resetting c71 | adjustment €[Link] lock voltage: C84 adjustment L10 FO tock voltage check point © MAIN UNIT 182 80 | Total gain R230 | adiustment 181 75: Total gain adjustment [te L78- 6-3 RECEIVER ADJUSTMENT (CONTINUED) ‘ADJUSTMENT ADJUSTMENT CONDITIONS. (MEASUREMENT ‘ADJUSTMENT POINT unt LocaTion VALUE unit | aouust smeten | 1 * Displayed frequency: 14.1000 MHz Mode use) + [RIT switch OFF NB] switen OFF {PRE AMP] switch : OFF ‘Connect the SSG to the [ANT] Connector and set as: Frequency : 14.1000 MHz Level: 25 uV*(—79 dBm) Modulation: OFF + Receiving Function splay Sindicator 5 dots just appear. MAN | R175 NOISE 1 BLANKER, * Displayed frequency: 14.1000 MHz = Mode use, [NB] switeh OFF ‘(PRE AMP] switch: ON + Rlceiving ‘Connect the $86 to the [ANT] ‘connector and set as: Frequency : 14.1000 MHz Level 232 yV* (87 dm) Modulation: OFF ‘= Apply the following signal to the 'S8G's output. [NB] switen oN *Set the SSG as: Level: 10 V*(—87 dBm) Modulation: OFF + Apply the same signal as shown above. MAIN Connect the oscilloscope to Fes. ‘Adjust for maximum wavetorm on the ‘oscilloscope. MAIN | 129, L24 ‘The noise must be blanked, Verity 1st LOTRAP] 1 * Displayed frequency: 14.1000 MHz “= Moge usB) ‘[PRE AMP] switch : OFF “Connect the SSG to Pt (MAIN unit and set as: Frequency : 64.4550 MHz Level: 82 wV*(=87 dBm) Modulation: OFF “= Racaiving Rear panel Connect the AC milvottmeter to the [EXT SP} jack with an 8 0 load, ‘Adjust for minimum speaker output man | 367 air 1 ‘Displayed frequency: 14.1000 MHz = Mode use ‘Connect the $86 to the [ANT] ‘connector and set as: Level: 50 uV=(~73 dBm) Modulation: OFF RIT] control: Conter *[RIT] switen ON and OFF Receiving Front panel Speaker Same tone pitch on both concttons, :# This output level of the standard signal generator ($86) is indicated as SSG's open citcut. MAIN AND VR UNITS Gd 423. } Noise banker €387 1st Lo trap. L24 } adjustment adjustment me RGB. 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TRANSISTOR OTG114EU T107 re18 | sr10000200 | 1c Bane ‘076 | 1590003090 |. TRANSISTOR 2804219-B (TERSA) rer | s1e0000«70 | 1¢ NIMTEDBA .a77 | s590000680 | § TRANSISTOR OTCII4EU T107 1618 | r110002680 | 5-16 NaMao02M-71 01 | s7e0000480 | s. viove aoe2 (1) a1 | 1530003180 | s. TRANSISTOR 28048730-70 2 | s780000480 | 5. DIODE Mase (Tx) a2 | ss00000600 | s. FET ‘38K126-0 (TESSA) 2 | s7e0000480 | s. DIODE Magee (1X) a3 | 1580000600 | 5 FET ‘38K126.0 (TESSR) 4 | r790000480 | s. 100€ Mase (TX) a4 | 1580000860 | 5 FET [Link] (TEBSL) 10s | s780000460 | 5. DIODE MAB62 (7%) 05 | 1590008180 |S TRANSISTOR 25048730-7D 6 | s160000060 | 5: DIODE DAN202U T107 (06 | 1500000680 |S TRANSISTOR DTCIM4EU T107 7 | s160000060 | s: 1008 DAN202U TiO? a7 | 1500000880 | 5 TRANSISTOR DTCIT4EU 7107 1 | +160000060 | s. DIODE DANz02U T1O7 ‘ce | 1580000560 | s. FET ‘[Link] (TEBSL) oo DaNanzu 1107 28 | 1580000800 | 5. FET ‘38K126-0 (TEOSA) 10 Maa62 (1%) a0 | 1580000580 | 5. FET ‘[Link] (TESSL) oi MaB62 (7) 11 | 1510000510 |S TRANSISTOR 2541876 T107 ors HOMBBASALTA 212 | 1520000560 | s. FET 25K882-GR (TESSL) bir DAP20QU T107 (233 | 1880000560 | s. FET ‘[Link] (TESSL) Dis DANz02U T107 14 | 1500001390 |S TRANSISTOR OTAII4EU T107 19 DAP202U T107 1s | 1500001390 | 5. TRANSISTOR OTAII4EU 7107 20 DAN202U T1O7 216 | 1590000880 |S: TRANSISTOR OTCI14EU T107 bat DAN202U T107 17 | 1520000200 | 5. TRANSISTOR 258708-T2 DK 22 DAP202U T107 218 | 1800000880 | 5. TRANSISTOR OTCIT4EU T107 23 DAN202U 1107 ‘a21 | 1590000880 |S: TRANSISTOR OTCI14EU T107 ee DaP202U T107 (azz | 1560000720 | 5. FET 2skai7-470 025 DAN202U T1O7_ fa23_| 1580000720 | 5. Fer 25K2171-47D 25 DAN202U T1O7_ 224 | 1860001330 |S. TRANSISTOR DTAIIAEU T107 ost DAN202U T1O7 (225 | 1530002060 |. TRANSISTOR 28Ca061 T107 R 03 DAN2020 T107 226 _| 1500000720 | s. FET 25K2171-41D 33 MABé2 (7) 27 | 1560000720 | 5. FET 25K2171-47D 035 wasez (09 {223 | 1580000600 | s: FeT 38K1250 (TEBSA) 36 wMaB62 (7) 220 | 1560000680 |. TRANSISTOR DTCII4EU Ti07 p38 | 1780000880 | S. DIODE A862 (7 290 | 1800001330 |S TRANSISTOR DTATIAEU T107 41 | 1780000880 | s: DIODE MAB62 (7) ‘a31 | 1500000600 | 5. TRANSISTOR OTCI14EU T107 bez | s7e0000880 | 5. DIODE MaB62 (7 ‘asz | 1590000680 | 5. TRANSISTOR DTCIN4EU T107 145 | 1760000480 | 5. DIODE Mage (1%) ‘a33 | 1590002060 | 5. TRANSISTOR 2sC408t T1O7 R 14s | 1780000880 | 5. DIODE Mas62 (7) ‘a4 | 1530002060 | 5. TRANSISTOR 2504081 T1O7 R as | 1780000880 |S. DIODE ase2 (7) ‘035 | 1590002060 | 5. TRANSISTOR 28C#081 T107 R 1050 | 1780000480 | s. DIODE MA@62 (7) a6 | 1520007050 | 5 TRANSISTOR 2504081 T1O7 R bss | s7e0000880 | 5. DIODE MaB62 (7%) (037 | 1590002060 | 5. TRANSISTOR 2504081 T1O7 A 1055 | 1700000480 | 5. DIODE Magee (7) ‘a3e | 1590000880 |S TRANSISTOR OTCIMEU T107 sr | s7e0000«80 | 5. DIODE MAaB62 (7) ‘a36 | 1530002060 | 5. TRANSISTOR 2504081 T1O7 FR se | 1160000080 | s. DIODE DANz02U T107 ‘Q40 | 1500001390 |S. TRANSISTOR DTATI4EU T107 p61 | 1160000080 | 5: DIODE ‘DANzZ02U T107 a1 | 1500000880 |S TRANSISTOR DTCI4EU T107 162 | 1180000080 | 5: o100€ DANz02U T107 044 | 1520002000 |S. TRANSISTOR 2504091 T107 A 16a | 1160000080 | 5. 10D aP202U TiO? ‘04s | 1360000880 | s: FET [Link] (TESSL) 164 | 1160000060 | 5. o100€ DaNz02U T107 246 | 1500000000 | s. FET 38K126-0 (TERSA) 16s | 1790000600 | 5. DIODE HSMBRAGATR [Link] mount

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