Digital Integrated Circuits Application Note AN6374.1 Se Applications of the COS/MOS CD4059A Programmable ide-by-N Counter: Digital Frequency Synthesis for_ “FM Tuners and CB Transceivers by 8. Niomiec and H. Pujol ‘This Note deseribes an FM digital tuner and a citizens band (CB) transceiver digital tuner that were constructed and tested to Aemonstrate the Trequency. synthesis capa- bility of the Harris COS/MOS CD4059A programmable divide-by-N counter. The Treclanical technique normally used in fie- hess consists of varying a capa- ‘itor, of t Focal ing.the tecelver 10. any desired frequency. The ‘igital approach deseribed inthis Note allows the desired. treque ven to be siected Paiwonson aboard: % si croty ale wins Bekebdoop, BLiy cei the ‘number Focal ogeillator of the receiver ts adjusted snd Jocked to the proper frequency, thus proper station section, Alternate "of station election that demon- strate the flexibility of the system are also described. FEATURES OF THE CD40590 ‘The funetional diagram of the CD4059A Ta The CDAIS9A is fivide-by.N doven counter that ean be pro- rammed (e divide an input frequency by ny integer N from 3 (0 15,999, Fig.2. The fulput signal fsa pulse one-clock-pulse wide that occurs at a rate equal to the input fre quency divided by N. This single output has ATL drive capability, The down counter is preset by means of 16 jam inputs. The mode often decade and the conte 4 fre externally selectable by ‘h vodesselect input The three Inputs Ka, Kb, and Ke determine the modu Tus (divide-by number) of the counting sections in accordance with the we O- LE we — Ha iy. 1 = Functional book diagram of CD4O59A.“ie vale Nf determined a follow N=IMODE"] 1000. Decade 6 Preset + 100% Decade 4 o Prost + YOX Decade 2 rest + 1% Decode 2 Preset | Daca 1 Prost 2 THODE= Fist counting section sider (10, 8,8, 4 02) ‘Tocateuate preset valet (or any 1 coon, vide the N count by the Mod “Tne resultent is the corresponng pert wets ofthe Sth though 2nd decnse with te ernie elog ent tte tt cae al N a rset Value ate PUTS (B01 eeeeeeeee A. 4. oe Ke Ko Ke Ta “Sew we non? sia na 6 io rod corto 1o1o 'oor O19 9 N= BOOX + 100XGHIOXDHTKG N0479 By 1912382, Mode = 1617 +6 8 [ase Move sevect-9 PROGRAMA JAM INPUTS. é z 4 Ka Kb Ke Toe Be w WHOM Ne He sa S16 Ho oot Ct 1 eo oa Tovniy W=B(1000% 1 # 100X584 10X48 1x 7106 w= 12382 ) N= 8479, Mode » 10 ooa7 9 rofea70 Move seLect «10, PROGRAM JAM INPUTS. —i i, — + ear Ke Kb Ke Tape Bw w noo vz sa Ie Hs H6 110 root retro goto ooo 4% To Verity N= 10 (9000 x 0+ 100% +10%42 17149 Nee Fig.2 — How topreset the COAOSIA 10. dosed N. truth table shown in Table 1, Every time 2. mode only one flipflops needed in the ist (Tastes!) counting “section goes first counting section, "Therefore the last fone cyele it reduces by | the num- counting section has three flip-flops that ean ber that has been preset Gammed) into the be preset toa maxinnim count of seven with tree decades of the intermediate counting a place value of thousands, Uf divide-by-10 is fection and into the fast counting section, desired for the first section, set Ka = 1. ‘hich consists of ‘Miplops that are noi Tnputs 11, 42,33, heeded for operating the first counting used 40 preset the fest Coun ection, For'example, in the divide-by- section; there is no last counting section‘orwanexrewoeo Juooe eetscr]| —Funsr counrins tasrcounrina | couwren |counren moos | nwt ‘seoTION ‘seoH1ON frawat /rance ene ten tain} | ee 2 {ape rT 7 5 [ison a fofa we 3 2 fis.ae s Jato sass 1 oe 3 | vo e [ole noea Jor fo fu 2 {sooo waa oom] 1 | o | | 3] eave! ‘wr | xf ojo we we - ‘The intermediate counting section consists ‘of three cascaded BCD decade (divide-by~ 10) counters prescttable by means of ja inputs 15 through 316. ‘The mode select inputs synthesizer channel separations of 10, 12.8, 30,25, 0r 50 parts, Inaddition, these inputs Sel the maximum value of N at 9999 (when the first counting section divides by 5 or 10) ‘or 15,999 (when the fist counting section divides by 8,4, oF 2). ‘The three decades, of the intermediate counting section can be preset to a binary 1S instead of binary 9, while their place values are still 1, 10, 100, multiplied by the umber of the dividesby:N mode, For ex: ample, nthe divide-by8 modo, tie mumber from which counting down begins can be preset 10: ‘31d decade: 1500 ‘nd decade: 150 Ist decade: 15 Last counting section 1000 2665 x 8 = 21,320 ‘The first counting seetion can be preset to 7 ‘Therefore, 21,327 4s the maximum possible count inthe divide by-B mode, The highest count of the ‘various modes ix shown in the column en. tilled Extended Counter Range, Max., of Table I, Control inputs Kb and Ke ean be used 10 nitate and Tock the counter in the master reset state. In this condition the Nip-lops ihe counter aro preset in accordance with thejaminputs,. and the counter remains in that state as Jong as Kb and Ke both rem "The counter begins t0 ct from the preset state when a count ‘other than the master preset mode i alected. Whenever the master preset mode ts used, rol signals Kb = 0 ‘applied for at least 3 full clock pul ‘nthe latch input will cause the counter out- put to remain high until the latch Input re- {urns to 0, If the latch input is 0 the output Ise will remain high for on lock-nput signal. ‘After the master preset mode inputs have ‘been changed to one of the divide-by modes, the next positive-poing clock transition ch ger an intemal flip-flop s0-that the count own begins at the second positive-going clock transition, Thus, after an MP mode, there is always one exits count before the fultput goes high. See Fig. 3 for tolal coun of 3 (divide-by-8 mode), F cycle of Fig.9~ CO4089A waveforms ‘As illustrated in the sample appl {his device Is very useful In comt Gigital frequency synthesis (VIE, ‘AM, cle.) whore programmable’ divile-by- N counters ate an Integral part of the syn. thesizer phaselocked-Joop subsystem, Note that the CD40S9A can also be wsed to per form the synthesizer fixed divide-by-R eount- Ing function. ations, DIGITAL FM TUNER ‘The digital control for an FM/PM stereo tuner shown in block diagram form in Fig. 4 ‘was designed using the CD40S9A and other COS/MOS standard parts, A detailed system Fopie/block’ diagram of the circuit is shown imPig. 5, The system is composed of eight rajor subsystems: Keyboard for Station Selection UpyDown Counter and Memory Keyboard Load Control Station Scan Control Prescaler(K) ble Divide-by.N Counter Hz Offset Fag Compatator(R) and Retroee 1d-Crystal Display DrivereS Fig. ~ Block diagrom ofthe FM/PM stereo terpo Keyboard and Station Selection "The Keyboard consists of 16 pushbucton SPST switches and 4 SPDT toggle switches. ‘The 0 through 9 switches are wired to fo Bidiode matrix thst, generates. a four lt BCD cquivatent ofthe key number depress, i Tevel i generated on ed shit i (ais Keyboard switchs ate discussed below with the functions they contro. ‘Station Selection Techniques ‘A number of tuning options are avail abe, “The system te placed inthe fist channel location, 88.1 MHz, by depressing the Reset button, ‘This action enables all Four upfdown counters simultaneously, and unher RR, through the A inputs of the CHADIAN, feeds Hugh the system ot the tuner om R&T MZ, The display also shows 88,1 at this tine, ‘The following, options can then be initiated: Direct Station Selection ~ Direct station selection is accomplished by means of the ‘mshbuttons, 0-9 (mos! significant frequency digi est) he channel trea hnumber will appear on the displ tuner VCO will Tock on that cha ‘Sean — When the SCAN buttonisde- prested, the tuner is set (0 th eM Channel (88.1) tieough the s that in effect when the Reset butt pushed, at Input also Reeds the suto-scan fogie circuits, and the fer begins to step forward through the ig ~ Syetem atogram. (Pare)channels until station is focated. At this ew station detect signal Is received in “clock-control Topic clreults the scanning aes, and. the frequency of the channel is shown on the liquid-crystal display. ‘To eoume scanning, the staton-bypass button fon the Keyboard 1s depressed.» Depressing the Sea-Up button also causes resumption ‘Of the seanning. operation, The stepping Setion proceeds in the forward direct {il another station is, located. upper limit af the FM. band is reached (1079) the direction of tuning is reversed find stepping down the band begins. ‘The Scan-Up or Sean-Down buttons override Scanning in process and redirect the tu Step in the direction indicated. It may be desirable to design a system without the Sean, Reset, and Station-Bypass buttons; they are Included here mainly to emvonsirate system flexibility Memory Storage — Any channel located uring the sean operation or selected by means of the Keyboard canbe stored in the memory. The four SPDT switches on the keyboord allow Tour channels to be stored for future pushbutton selection. (This it of 4 channels is Imposed by the size of the memories used. inthe system) To store the address of the channel frequency in the memory, a W button is placed in the closed. position and. the Write pushbution is then depressed, ‘The Write button dis ables the memory byrass and enables the Station frequency number to be stored i the memory, Any stored number can be trated from the memory by simply enter- ing a new number In the word selected in ‘the memory, Giroult Oporetion Up/Down Counter and Memory — Four CD4029A presettable upfdown counters are used to accomplish two functions: First, Morage for the selected keyboard numbers i and second, the scanning mode. The ty depressing the Reset but ‘Wien the frst Key i depressed, fllow- ing iniialization, » BCD umber appears OF the, jam fines of all Tour CD4029A Sout Mioteneoy atthe sane {he sift signa from the Keyboard Is pro- cessed by ihe keyboard fond contol eet ‘so proet-enahle signal on one Sounters, thos allowing the BoD mumber to be loaded into that counter. Esch time a key Is depressed, «differen foumter ts fondeds than, four CDA020A Counters are foded sequently The CD#039A is a COS(MOS four-vord by eight bit random-acces NDRO men the FM tuner are Wi to the CD4029A counter outpus, ad @ senstiye tothe ats loved in the Counters Any word sleet fine ofthe ment ‘ry uni that fost high allow the eoutcr data toe stored in memory when the Waite Settch iy elored. (Fie woud-sclect switches Wi through Wa andthe Waite svi Tocated on the keyboard). ‘This sequence of Serta permits any” station frequ : Stored in memory at any Une, regardless of thetmade of operation. During novos! oper tion in he direct station slo sean Modes of operation, the outputs of the Up own coumers ae” hypasedatound. the temory nts Because of he low paver disipation of COSMOS parts, standby battery incor porated nthe system is sufficient 10 eh- ie tat infenmaton it memory. will no be destroyed should a power falar occur Keyboerd Load Logie — The Keyboard toat Tope ensures soquentat hing of the Countess, Some FM channelsare represented fia thvce gt nuamber (For exampte, 8.1). tlbersby e Tour digit number (for exampie; Ora): therefore, counters re headed with either three ors four-digit suber IA CDAOIBA counter, with associated de- coding gates, advenes the Keybourd digits {or he (proper CD&029A. counter in the Proper sequence, For example, if a 1 is Totccted asthe fst Keyboard digi, the CDAOIA operates asa divide-dy-4 Coie, nd the output from the CDAOK9A. that Ernnected he ost sii ‘ies the presen ounter (nike 100). The | of the 4 wiost sian pfdown "counters. presets only the most Spriffeancounter (100) and thereby stores ite ha eybonrd digit. It the fist key oud’ digit’ Is any number other thant, the CD4018A ‘operates as 3 dlvide-by-3 ‘hunter, ad the fst output oF heCD4O19A fates tobe energized Is he one connected to the CD4029A marked (10). Thus he second eybonrd dig selected is stored inthe GBao20A marked (10). The other digits are Sirected to ther respective up/down counter in sequences timing that control the. quencing derived. from two. CDAO47A Shonostable sultvirators. ‘The CD4O13A eedbed inthe set reset mode to determine the test digit and to preset the CD4OIBA The CD4O19A ANDIOR select gate pre- vents the enabling of any of the four counters ‘while the lines are unstable; ke., during the Time just af bec aed, Key Dpourd:-switel prevented by use of # CDAOATA one-shot circuit aml some pate delays. Elimination of bounce elit hates false triggering of the divide-by- ‘counter, ‘The Station selection with random therefore the system 3 set each tine power is turned on, Station Seen Control —__ Wien the scan button is depressed, a high-level voltage appears at tie KB input to the delayed nad be resckage CD4019A, The Vp on iis 10 this package ts Ie hrongh and enables the P.E. Input on the four upf Gown counters. This high level voltage allows 88.1 tobejammed into the upidown counters (0.1.1, 10). The Jam BR CDAOI9A con: trolled “by: the Scaneltesct 8.1 logic feeds the 88.1 number (0 the up/down count ‘The Scan circuit energizes {he Clock-Controi cireult and clock pulses are fed into. the up/down counters to Inciease the count toward 107.9, When the tuner locates station, the’ station ‘detect signal into the lock contrat circuit stops the clock and the counters stop counting. ‘The source of the ‘statton-detect. signal will depend. on fabrication of the complete tuner, whiel Is not covered in this Note, If no stations ate recelved. in. the scansup period, the ‘counters start counting down automatically After the maximum count (107.9) Is reached. ‘The. scanning up aid down continues i definitely until'n station ie received, To. ‘the count again, (if the. station re- ceived Is not desired) the Scan-Up (or Scen- Down) bution is depressed. If'the Resct ‘bution Is depressed, it affects the upfdows counter in the same manner ar the Se button dd previo the updown counter starts counting again from 88.1. The Reset Dutton ako resets the divide-by:9 counter CDADISA tn the Keyboard load control sub- system, Prescaler (divide-by-K) — The CD4059A, programmable divide-ny-N counter accepts Kis signal directly Trom the VCO. “Any VCO with 3 control voltage of 3 t0 17 volts will function in the system. “Since the upper apeating frequeney of the CD4OS9A at a [pp of $ volte fs approximately 1 Mite, afixed divide-by-k prescaler of 160 was chosen. “An ECL divide-by-eight unit feed- ing into an ECL-o‘TTL converter, which in win feeds a TTL divide-by-20 unit, pro- ries the requted operating mput requeney for the counter (0.6 MHz). Programmable Oivide-by-N Counter and 0.7 Miz Offset — Alter prescaling, any of 1¢ 100 FM channels selected will appear ak a clock input to the CD4039A counter. ‘The lock frequencies representing these channels ange between 0.6175 MHz and 0.74125, Milz, Fig. 6 shows the block diagram of the phaso-lock-toop, Without a presealer, the feference frequency (fF) is nominally equal tothe channelapacing frequency (Ie). How. ct, where presealng counter teempleyed, he vale of fama be reduced hy a asin by Referring to ip 6 MeeKNTy and fr Fi When the loop is phase-locked: and thus: In this design: fast Mile and NES# 410.7 where 4» FM channel Frequency tn Mia; Ten B81 < #<1079, and 10. ithe off fet of the local oscillator above fo be tuned. ‘Thus: : fre gh Miic= 1.25 Ki and 160 fo=AE25 (#4 10.7) (1) MUtz (#4 107M + 1m operation: ‘OBR Sy < 118.6 MHz GATS fy 741.25 Ke 494 fn KN where fp ranges between 26,965 MH. and 271T10 Miz. Therefore, ihe range oF N is Frequencies with Required Skits1 ‘Table tv — cB Bond jansmit and Receive Frequencies with Required Divide-by-N Mode » 2 JAM tin Jam in Oa080A in mit, YN Reaid for GD4089A In Receiver in nega 52 Mode iti) Teanwt Freq, Sz Mode” LO, FreqiMls) For Rocave With Otft 1 26085 (Ban Geass 27470 waa 2 26975 6305 20074127490 ease 2743 316908 5207 200801 27.400 sana 2744 497,008 6401 210081 27.400 waz 2740 5 77018 409 zio1e1 27470 saa 27 8 21.02 S05 2masi 27480 sao 740 727.09 _ 5401 270311 27.490 stos 7749 377.095 6411 D061 37810 zon —=276 9 77088 413 270641 27520 seot 2782 10 27075 sate zrorei 21830 35002759 M2709 sav7 2ree1 27840 scos 7c P9108 6a a0) 27500 ~S~C SIC 13. 27158423 zno+1 27870 ssa 2757 16 771% 625 2nas1 27.880 see 2750 1527136 barr znise1 27.500 soi 2700 16 27.158 431 aie+1 27.610 e627 3768 17 271889439 2ne+i 27620 e521 2702 18 2737885 274127830 e326 7709 192705 saa? zis 27.640 sees 2764 2027205 sean 32041 37.660 3a —=766 227.215 ans piaie1 27070 seat 2707 21255485 pari 27.600 $05 2768 33 27.255 ——~8a6t Tape 270 sea. a siven by’ 91, is added (o the N (5393) of the counter ie eceive mode for chan 1 Ne it ‘offnt number is added 10 the 8 of the counter by using CO4D19A-ANDOR. N BITOMHE _ sy felect ites, © CDADLSA flip Nop, and age SKI CDAOTA NAND gale. The function of tenn the CDAOI9A Isto tesiform he single st 0 t ff ande-by¥ jam inputs to two ste tn N min #7 Sie 5393 puts, both connected independently to the a a counter, One set of mene carries the ac- when Nis $393 and the counter outpu fre. ual Number que forthe ansninion Re a ne tO regueny.t —Hequency of Ue chamel desied, the oer eI tO Tes ee Ocenecuey that st of inputs avis the fied offset number, corresponds to channel 1. ‘Tables 1M and IV indicate thatthe proper local-oscilator Frequency for ch 27,820 MHz. This frequency beats with the incoming VCQ frequency, 26.96: generate a 455-kHe frequency. The if fre- fency ix represented by an N equal 10 Sate (8), 4 mnberexay 91 hhighor than the N sequired for the transmit frequency (N= $393). The offset number, Bi. tna, te st of spt carrying the fesnsmistonirequeney (Nis connected 10 the divide Ncotcr jam tines, andthe Sour cnt down ro that ine. A Signal that appears a the counter utp ted, n turn oth the jam inputs tothe fixed count of9!sand once een the counter counts down, The second: ouput of the ounter Irth tr utp Thns there have Been two countdowns totaling 5484 (5393+ ips andthe the tran or the receive {oct ostiator frequency Is avaibleee ‘offeet can be employed or not depending fo whether the Mp flop (CD4013A) ie held in reget or not, The Mip-lop resot switch ‘witches from init fo the: receive frequency. The output of the phase comparator 1 fof the CD4046A ig wsed in the phase-lock- Toop circuit, A phase difference between the divide-by-N vd the difference Frequency” pror the output of the phase co polailty of this cortection voltage pulls the he ti CO frequency in a dircetion that causes {he dividerdy.N output frequency to phase- Itc the. relerence frequeney. Inputs (© the comparator conslst of the divide-by.N Duiput anda reference derived from the TOON: erystalcontrolled oscillator, The oseilator fs built from a CD4007A dual Complementary pair pis invertora reference OF TOO Tl fs ahtained by using i CD4059A ‘with an N of 1000, ‘The eurput of the com parator is fed through an RC filler to the VCO.