Elettronica I Materiale Didattico

prof.ssa S. Rocchi ing. M.
Poli
Teaching guide: basic electronics

2008-09
Contents
Introduzione . . . . . . . . . . . . . . . . . . . . . Ringraziamenti . . . . . . . . . . . . . . . . . . . . Link a equazioni, gure, lavagne, parti e riferimenti NOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bibliograci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 3 4 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 8 8 8 8 9 9 9 9 9 9 10 10 10 10 10 11 11 11 11
Summary Part T1: Notes on Electricity . . . . . . . . . . . . . . . . . . . Part T2: Semiconductor physics . . . . . . . . . . . . . . . . . Part T3: Diode as non-linear device . . . . . . . . . . . . . . . Part A1: Diode applications . . . . . . . . . . . . . . . . . . . . Part T4: MOSFET device . . . . . . . . . . . . . . . . . . . . . Part T5: Bipolar Junction Transistor (BJT) . . . . . . . . . . . Part T6: MOSFET and BJT as non-linear devices . . . . . . . Part N1: Basics of Electrical Theory . . . . . . . . . . . . . . . Part A2: Single stage MOSFET and BJT congurations . . . . Part E1: Esempio di progettazione di un amplicatore CS . . . Part A3: Basic MOSFET-based congurations . . . . . . . . . Part T7: Ampliers frequency response . . . . . . . . . . . . . Part A4: Time-constant method application . . . . . . . . . . . Part T8: Ideal voltage amplier and feedback . . . . . . . . . . Part A5: Ideal voltage amplier and feedback applications . . . Part T9: Stability analysis of feedback ampliers . . . . . . . . Part E2: Compensation examples . . . . . . . . . . . . . . . . . Part T10: Techniques used to analyze feedback ampliers . . . Part E3: Examples of the Rosenstark and Blackman formulas . Part E4: Esercizi su amplicatori, retroazione e compensazione T1 Notes on Electricity Electric eld E . . . . . . . . . . . . . . . Flux of E . . . . . . . . . . . . . . . . . . Gauss law in vacuum . . . . . . . . . . . . Meaning of 0 . . . . . . . . . . . . . . . . permittivity . . . . . . . . . . . . . . . . Electric displacement eld (or electric ux Electrostatic potential V . . . . . . . . . . Electrostatic potential property (I) . . . . Electrostatic potential property (II) . . . E V on x dimension . . . . . . . . . . Potential energy U . . . . . . . . . . . . . Energy conservation law . . . . . . . . . . Example: potential energy barrier . . . . Metal conductivity schematic picture . . . (mobility) . . . . . . . . . . . . . . . . . J (current density) . . . . . . . . . . . . . Conductivity . . . . . . . . . . . . . . . . Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . density) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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T2 Semiconductor physics Band Theory of Solids . . . . . . . . . . . . . . Conduction . . . . . . . . . . . . . . . . . . . . Insulators, semiconductors and conductors . . . Fermi-Dirac statistics . . . . . . . . . . . . . . Electrical conductivity . . . . . . . . . . . . . . Semiconductors . . . . . . . . . . . . . . . . . . Semiconductors current pictures . . . . . . . . Doped semiconductors . . . . . . . . . . . . . . Symbols . . . . . . . . . . . . . . . . . . . . . . Conductivity for semiconductors . . . . . . . . Intrinsic semiconductors . . . . . . . . . . . . . Doped semiconductors n-type . . . . . . . . . . Doped semiconductors p-type . . . . . . . . . . p-n junction . . . . . . . . . . . . . . . . . . . . Reverse bias . . . . . . . . . . . . . . . . . . . . Forward bias . . . . . . . . . . . . . . . . . . . p-n diode . . . . . . . . . . . . . . . . . . . . . Diode equation . . . . . . . . . . . . . . . . . . Diode dynamic eects: transaction capacitance Diode dynamic eects: diusion capacitance . . Actual diode maximum limits . . . . . . . . . . Breakdown eect . . . . . . . . . . . . . . . . . Zener diode . . . . . . . . . . . . . . . . . . . .
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12 12 12 12 13 13 13 14 14 15 15 15 15 15 16 16 17 17 17 17 18 18 18 19 20 20 20 20 21 21 21 21 22 22 22 22 23 24 24 24 24 25 25 25 26 27 27 27 28 28 28 29
T3 Diode as non-linear device Diode as non-linear device: circuit analysis . . . . . . . . . . . . . Linear piecewise (OFF region) . . . . . . . . . . . . . . . . . . . . Equivalent resistance and equivalent circuit . . . . . . . . . . . . . Graphic picture of the diode linear piecewise in OFF region . . . . Linear piecewise (ON region) . . . . . . . . . . . . . . . . . . . . . Dierential conductance . . . . . . . . . . . . . . . . . . . . . . . . Dierential resistance . . . . . . . . . . . . . . . . . . . . . . . . . iD in forward region and small signal conditions . . . . . . . . . . Norton equivalent circuit (ON region) . . . . . . . . . . . . . . . . vD in forward region and small signal conditions . . . . . . . . . . Thevenin equivalent circuit . . . . . . . . . . . . . . . . . . . . . . Graphic picture of the diode linear piecewise in ON region . . . . . Graphic picture of the diode linear piecewise in breakdown region . Zener voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zener resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zener diode equivalent circuit in breakdown region . . . . . . . . . Linear piecewise approximation (LPA) for diodes . . . . . . . . . . LPA for Zener diodes . . . . . . . . . . . . . . . . . . . . . . . . . . Zener diode equivalent circuits . . . . . . . . . . . . . . . . . . . . How to choose the right region . . . . . . . . . . . . . . . . . . . . A1 Diode applications Rectier . . . . . . . . . . . . . Bridge rectier . . . . . . . . . Rectier with lter . . . . . . . Amplitude-modulation detector Zener regulated power supply . Zener limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
prof. S. Rocchi, ing. M. Poli - Dipartimento di Ingegneria dellInformazione - Universit` degli Studi di Siena a
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T4 MOSFET device MOSFET as capacitor with capacitance depending on gate voltage MOSFET device structure when inversion layer is present . . . . . Charge in the inversion layer . . . . . . . . . . . . . . . . . . . . . Medium charge density . . . . . . . . . . . . . . . . . . . . . . . . Current iD when inversion layer is present . . . . . . . . . . . . . . Validity eld of (T4.5): triode region . . . . . . . . . . . . . . . . . Graphics of iD vs. vDS in triode region . . . . . . . . . . . . . . . MOSFET as Voltage Controlled Resistor (VCR) . . . . . . . . . . MOSFET in saturation region . . . . . . . . . . . . . . . . . . . . . Pinch-o point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saturation region . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET is a voltage-controlled current generator . . . . . . . . . Channel modulation eect . . . . . . . . . . . . . . . . . . . . . . . Body eect (substrate bias eect) . . . . . . . . . . . . . . . . . . . Extension to p-channel MOSFETs . . . . . . . . . . . . . . . . . . MOSFET-p triode current . . . . . . . . . . . . . . . . . . . . . . . MOSFET-p saturation current . . . . . . . . . . . . . . . . . . . . MOSFET: limits of operation . . . . . . . . . . . . . . . . . . . . .
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30 30 32 32 32 32 33 34 34 34 35 36 36 36 36 37 37 37 37 38 38 38 39 39 39 39 39 39 39 40 40 40 40 40 40 41 41 41 41 42 43 43 44 44 45 45 45 46 46 46 46 46 47 48 48 49 49 49 50
T5 Bipolar Junction Transistor (BJT) Bipolar Junction Transistor (BJT): physical structure . . . . . . . . . . . . . . . . . Conduction when B-E is forward biased and B-C is reverse biased (graphic picture) BJT current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . iB current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iC current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iE current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . BJT current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . iB current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iE current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iC current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . BJT current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . iC current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iE current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . iB current when vBE = 0 and vBC = 0 . . . . . . . . . . . . . . . . . . . . . . . . . BJT non-linear circuit model: transport model . . . . . . . . . . . . . . . . . . . . . Forward Active Region (FAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Active Region (RAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BJT: Saturation Region (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BJT: Interdiction Region (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics pictures of iC vs. iB and vCE in FAR . . . . . . . . . . . . . . . . . . . . . Early eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BJT physical limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T6 MOSFET and BJT as non-linear devices MOSFET: LPA with vBS = 0 in triode region . . . . . . . . . . MOSFET: LPA with vBS = 0 in saturation region . . . . . . . Geometric interpretation of g0 . . . . . . . . . . . . . . . . . . . Geometric interpretation of gm . . . . . . . . . . . . . . . . . . MOSFET: LPA conditions in saturation region (small signal) . MOSFET equivalent circuit for id . . . . . . . . . . . . . . . . MOSFET equivalent circuit when vBS = 0 . . . . . . . . . . . . Evaluation of iD by means of circuit theory . . . . . . . . . . . MOSFET parasitic capacitances: triode region . . . . . . . . . MOSFET parasitic capacitances: saturation region . . . . . . . MOSFET linear equivalent circuit in high frequency condition . When can parasitic capacitors be neglected? . . . . . . . . . . . BJT: LPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BJT equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . BJT: Evaluation of ic and ib by circuit theory . . . . . . . . . . BJT: LPA conditions in FAR region (small signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS
IV
N1 Basics of Electrical Theory Quadripoles . . . . . . . . . . . . . . . . . . . . . . . . . . . Dierential input . . . . . . . . . . . . . . . . . . . . . . . . Single input . . . . . . . . . . . . . . . . . . . . . . . . . . . Dierential output . . . . . . . . . . . . . . . . . . . . . . . Single output . . . . . . . . . . . . . . . . . . . . . . . . . . Single-input, single-output linear quadripoles . . . . . . . . Input and output impedances . . . . . . . . . . . . . . . . . Voltage, current and power gains . . . . . . . . . . . . . . . Dierential-input single-output linear quadripoles . . . . . . Common mode and dierential mode voltages . . . . . . . . Common mode and dierential mode gains . . . . . . . . . Common-mode rejection ratio . . . . . . . . . . . . . . . . . Dierential mode and common mode input impedance . . . Unidirectional Linear Amplier . . . . . . . . . . . . . . . . Voltage amplier . . . . . . . . . . . . . . . . . . . . . . . . Trans-impedance amplier (current-to-voltage converter) . . Trans-conductance amplier (voltage-to-current converter) . Current amplier . . . . . . . . . . . . . . . . . . . . . . . . Maximum voltage transfer to the input impedance . . . . . Maximum current transfer to the input impedance . . . . . Maximum voltage transfer to the load . . . . . . . . . . . . Maximum current transfer to the load . . . . . . . . . . . . Maximum voltage transfer from the input to the load . . . Maximum current transfer from the input to the load . . . The Miller theorem . . . . . . . . . . . . . . . . . . . . . . . Miller theorem demonstration . . . . . . . . . . . . . . . . . Miller eect for capacitors . . . . . . . . . . . . . . . . . . . A2 Single stage MOSFET and BJT congurations Common source (CS) . . . . . . . . . . . . . . . . . . . CS: biasing . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity (denition) . . . . . . . . . . . . . . . . . . . CS: The design problem . . . . . . . . . . . . . . . . . . CS: Small-signal (LPA) equivalent circuit . . . . . . . . CS: Norton equivalent circuit . . . . . . . . . . . . . . . CS: equivalent conductance . . . . . . . . . . . . . . . . CS: voltage amplication . . . . . . . . . . . . . . . . . CS: simplifying hypotheses . . . . . . . . . . . . . . . . CS: estimation of the maximum voltage amplication . Common drain (CD) . . . . . . . . . . . . . . . . . . . . CD: biasing . . . . . . . . . . . . . . . . . . . . . . . . . CD: small-signal equivalent circuit . . . . . . . . . . . . CD: short-circuit id = ieq . . . . . . . . . . . . . . . . . CD: output equivalent conductance . . . . . . . . . . . . CD: voltage amplication . . . . . . . . . . . . . . . . . Common gate (CG) . . . . . . . . . . . . . . . . . . . . CG: biasing . . . . . . . . . . . . . . . . . . . . . . . . . CG: small-signal equivalent circuit . . . . . . . . . . . . CG: short-circuit id = ieq . . . . . . . . . . . . . . . . . CG: output equivalent conductance . . . . . . . . . . . . CG: current amplication . . . . . . . . . . . . . . . . . CG: input conductance . . . . . . . . . . . . . . . . . . CG: voltage amplication . . . . . . . . . . . . . . . . . MOSFET congurations summary . . . . . . . . . . . . Common emitter (CE) . . . . . . . . . . . . . . . . . . . CE: Biasing . . . . . . . . . . . . . . . . . . . . . . . . . CE: The design problem . . . . . . . . . . . . . . . . . . CE: Small-signal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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51 51 51 51 52 52 52 52 53 53 53 53 54 54 55 55 56 56 57 57 57 58 58 59 59 60 60 61 62 62 63 63 64 64 65 66 66 66 67 67 67 68 68 68 69 69 69 70 70 71 71 72 72 72 73 73 74 75
CONTENTS
E1
Esempio di progettazione di un amplicatore CS Speciche di progetto . . . . . . . . . . . . . . . . . . . . Dati . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analisi preliminare del circuito . . . . . . . . . . . . . . . Circuito equivalente per lo studio della polarizzazione . . Corrente erogata dai generatori di polarizzazione . . . . . Circuito equivalente di piccolo segnale . . . . . . . . . . . Guadagno di tensione . . . . . . . . . . . . . . . . . . . . Conversione delle speciche . . . . . . . . . . . . . . . . . Verica di centro banda . . . . . . . . . . . . . . . . . . . Sommario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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76 76 77 77 77 78 78 79 79 80 81 82 82 82 83 83 84 85 85 86 86 86 86 87 87 88 88 89 89 90 90 91 91 92 92 93 93 94 94 94 95 96 96 96 96 97 97 98 98 99 99 99 99 100 100 100 100
A3 Basic MOSFET-based congurations Diode-connected MOSFET connection . . . . . . . . . . Current mirror . . . . . . . . . . . . . . . . . . . . . . . Current mirrors . . . . . . . . . . . . . . . . . . . . . . . Dierential amplier (DA): large dierential signal . . . DA: iD1 = f1 (vd )iD2 = f2 (vd ) . . . . . . . . . . . . . . DA: plots of iD1 and iD2 . . . . . . . . . . . . . . . . . . DA: plots of vO1 and vO2 . . . . . . . . . . . . . . . . . DA: verication of the saturation region for M1 and M2 DA: evaluation of vO1 . . . . . . . . . . . . . . . . . . . DA: biasing equivalent circuit . . . . . . . . . . . . . . . DA: biasing . . . . . . . . . . . . . . . . . . . . . . . . . DA: small signal . . . . . . . . . . . . . . . . . . . . . . DA: common-mode small signal . . . . . . . . . . . . . . DA: dierential-mode small signal . . . . . . . . . . . . DA: complete vo1 . . . . . . . . . . . . . . . . . . . . . . DA: CMRR . . . . . . . . . . . . . . . . . . . . . . . . . DA: common source conguration with RS = 0 . . . . . T7 Ampliers frequency response Frequency response (denition) . . . . . . . . . Bode plot . . . . . . . . . . . . . . . . . . . . . Band-pass lter . . . . . . . . . . . . . . . . . . Reduction of a third order system to rst order Reduction of a n-th order system to rst order Time-constant method . . . . . . . . . . . . . . Note on time-constant method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A4 Time-constant method application Time-constant method example . . . . . . . . . . . . . . . . . . . . Output short-circuit current of circuit in Fig. A4.1 . . . . . . . . . Output equivalent impedance of circuit in Fig. A4.1 . . . . . . . . Norton equivalent of circuit in Fig. A4.1 . . . . . . . . . . . . . . . Transfer function of circuit in Fig. A4.1 . . . . . . . . . . . . . . . Time-constant method applied to circuit in Fig. A4.1 . . . . . . . 0 Evaluation of R1 by means of the time-constant method . . . . . . 0 Evaluation of R2 by means of the time-constant method . . . . . . 1 Evaluation of R2 by means of the time-constant method . . . . . . Evaluation of coecient a1 by means of the time-constant method Evaluation of coecient a2 by means of the time-constant method T8 Ideal voltage amplier and feedback Basic conguration of actual operation amplier Ideal operation amplier . . . . . . . . . . . . . . Ideal operation amplier: parameters . . . . . . . Ideal operation amplier: virtual short circuit . . Feedback . . . . . . . . . . . . . . . . . . . . . . Negative feedback . . . . . . . . . . . . . . . . . Closed-loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS
VI
Negative feedback circuits based on the ideal operation amplier . Feedback analysis of circuits based on the ideal operation amplier Closed-loop ideal gain . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity of AV0 with respect to A0 . . . . . . . . . . . . . . . . . Sensitivity of AV0 with respect to B . . . . . . . . . . . . . . . . . Noise suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feedback with non-linear amplier . . . . . . . . . . . . . . . . . . Bandwidth extension . . . . . . . . . . . . . . . . . . . . . . . . . . Gain-bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . Transition angular frequency and gain-bandwidth product . . . . . The bilar model . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage (shunt) sampling . . . . . . . . . . . . . . . . . . . . . . . Current (series) sampling . . . . . . . . . . . . . . . . . . . . . . . Voltage (series) mixing . . . . . . . . . . . . . . . . . . . . . . . . . Current (shunt) mixing . . . . . . . . . . . . . . . . . . . . . . . . A5 Ideal voltage amplier and feedback applications Voltage follower based on OA . . . . . . . . . . . . . . . . Non-inverting amplier . . . . . . . . . . . . . . . . . . . Inverting amplier . . . . . . . . . . . . . . . . . . . . . . Inverting adder . . . . . . . . . . . . . . . . . . . . . . . . Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . T9 Stability analysis of feedback ampliers Stability analysis . . . . . . . . . . . . . . . . . . Single-pole amplier . . . . . . . . . . . . . . . . Two-pole amplier . . . . . . . . . . . . . . . . . Ampliers with at least three poles . . . . . . . . The loop gain modulus . . . . . . . . . . . . . . . The loop gain phase . . . . . . . . . . . . . . . . Characteristic equation . . . . . . . . . . . . . . Loop gain phase . . . . . . . . . . . . . . . . . . Loop gain modulus . . . . . . . . . . . . . . . . . Gain and phase margins . . . . . . . . . . . . . . System with phase margin equal to 90 . . . . . System with phase margin equal to 60 . . . . . System with phase margin equal to 30 . . . . . What is the best phase margin? . . . . . . . . . . Compensation . . . . . . . . . . . . . . . . . . . . Compensation by reduction of the loop gain . . . Narrow-banding . . . . . . . . . . . . . . . . . . Pole dominant compensation . . . . . . . . . . . Miller compensation . . . . . . . . . . . . . . . . Comparing the eectiveness of the pole dominant E2 . . . . . . . . . . . . . . . . . . . . . . . . .
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101 101 101 101 101 102 102 103 103 103 104 104 105 105 105 106 106 107 107 108 108 109 109 109 109 110 110 110 110 111 111 112 112 113 113 113 114 114 115 116 117 119 121 121 122 122 123 125 125 125 126 126 126
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Compensation examples Compensation example . . . . . . . . . . . . . . . . Bode plots for the original and compensated systems Compensation example on a simple 3-stage amplier Miller compensation example . . . . . . . . . . . . . feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T10 Techniques used to analyze Rosenstarks formula . . . . . . . Return ratio . . . . . . . . . . . . Asymptotic gain . . . . . . . . . Direct gain . . . . . . . . . . . . Blackmans formula . . . . . . .
ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS
VII
E3
Examples of the Rosenstark and Blackman Return ratio example . . . . . . . . . . . . . . . . . Asymptotic gain example . . . . . . . . . . . . . . Direct gain example . . . . . . . . . . . . . . . . . Rosenstarks formula example . . . . . . . . . . . . Blackmans formula example . . . . . . . . . . . . Blackmans formula example: evaluation of Tsc . . Blackmans formula example: evaluation of Toc . . Blackmans formula example: evaluation of R0 . . Blackmans formula example . . . . . . . . . . . . Esercizi su Esercizio A . Esercizio B . Esercizio C . Esercizio D . Esercizio E . Esercizio F . Esercizio G . amplicatori, retroazione . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e . . . . . . .
formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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127 127 127 128 128 128 128 129 129 129 130 130 130 131 131 131 132 132
E4
compensazione . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Teaching guide: basic electronics Anno 2007-08
Introduzione
Il materiale di studio ` sostanzialmente un ipertesto organizzato in lavagne dove e la parte descrittiva ` essenziale, sono stati introdotti alcuni commenti raggiungibili e attraverso link. Fa parte del materiale una versione stampabile dellipertesto (in formato PDF) in cui i commenti sono evidenti. Nel quadro 1 ` riportata una sintesi del percorso didattico organizzato secondo un e lo logico in cui le singole parti sono numerate e richiamate con il corrispondente numero scritto sopra e sotto la freccia quando da queste occorre prelevare concetti e nozioni utili alla comprensione della parte considerata. Per esempio per comprendere la parte 4 sulla struttura e funzionamento del MOSFET occorre conoscere la sica dei semiconduttori trattata nella parte 2. Si dierenziano le parti applicative (app*,*) in cui sono riportate tipologie di circuiti per riettere svolgendo esercizi. Lipertesto ` organizzato secondo lo stesso lo logico, sopra le frecce che si e susseguono lungo il percorso sono riportate le formule e/o le gure utili per comprendere i diversi passaggi. Le denizioni, le dimostrazioni iniziano con un quadratino nero e terminano con le denizioni, le tesi, i commenti nali evidenziati con un rettangolo di contorno. Lo studente, a lezione, dovrebbe avere una stampa delle lavagne, in cui volutamente sono lasciati spazi bianchi per commenti. Comunque si suggerisce di associare ad ogni lavagna una o pi` pagine di commenti desunti dalla lezione del u docente o da integrazioni e riessioni in fase di studio. In questo modo lo studente potr` costruire un proprio libro per Elettronica I. a
Ringraziamenti
La prima versione dellipertesto di Elettronica I (elettronicaI 2007.*), sviluppato secondo il lo logico descritto, ` frutto di incontri e letture di documenti sugli strumenti e della Ricerca Metodologica Disciplinare sviluppati dal Prof. Filippo Ciampolini (Universit` di Bologna) al quale sono rivolti i nostri pi` sentiti ringraziamenti. a u
Istruzioni per lutilizzo dellipertesto
Link a equazioni, gure, lavagne, parti e riferimenti bibliograci
Il materiale di studio ` consultabile come un qualsiasi ipertesto. Le equazioni, le e gure, i riferimenti a lavagne, i riferimenti a parti e i riferimenti bibliograci sono link per consentire una navigazione dinamica e interattiva. Il seguente simbolo rappresenta un link a lavagna.
Dopo aver fatto click su un link ` suciente premere il tasto BACKSPACE e (versione HTML) o il pulsante INDIETRO del browser (versione HTML) o il tasto VISTA PRECEDENTE (versione PDF) per tornare alla pagina che si stava consultando prima della pressione sul link.
Istruzioni per lutilizzo dellipertesto
Inoltre per alcune lavagne sono presenti dei commenti in pi` lingue identicati da u bandiere in fondo alle lavagne stesse (si guardi la gura sottostante). Basta fare click sulla bandiera della lingua voluta per far apparire o scomparire il commento.
Nella versione PDF i commenti iniziano con il simbolo
e sono scritti in corsivo.
A causa delle nuove politiche di protezione di Internet Explorer, gli studenti che usano tale browser devono autorizzare la visualizzazione del contenuto bloccato facendo click sulla barra gialla che compare in alto alla pagina e selezionando Consenti contenuto bloccato... (si guardi limmagine sottostante).
NOTA
Summary
Part T1: Notes on Electricity
E (Electric Field), V (Electrostatic Potential), J (Current Density), (Conductivity), (Resistivity).
Part T2: Semiconductor physics
T1
Band Theory, Conductivity of Doped Semiconductors, p-n Junction, Diode, Zener Diode.
Part T3: Diode as non-linear device
T2
Diode Equation Approximation, Linear Circuit Models of two terminals device. Analysis methodology of circuits with diodes.
Part A1: Diode applications
T3
Diode applications.
Part T4: MOSFET device
T2
MOSFET as capacitor, Ohmic and Saturation Regions, Modulation channel eect, Body eect.
Part T5: Bipolar Junction Transistor (BJT)
T2 T4
Bipolar Junction Transistor (BJT), Forward and Reverse Active Regions, Saturation Region... Base width modulation eect parasitic capacitors. Comparison with MOSFET.
Summary
Part T6: MOSFET and BJT as non-linear devices
T2,T4 T5
MOSFET equations approximations, Linear Circuit Models, Analysis methodology of circuits with MOSFET (CS conguration as example of biasing circuit and small signal equivalent circuits). Parasitic capacitors. BJT equations approximations, Linear Circuit Models, Analysis methodology of circuits with BJT (CE conguration as example of biasing circuit and small signal equivalent circuits).
Part N1: Basics of Electrical Theory
Notes on two-port networks (Quadripoles). The Miller theorem.
Part A2: Single stage MOSFET and BJT congurations
T6 N1
MOSFET: CS, CD and CG congurations: voltage gain, current gain, input and output conductances. BJT: CE conguration: voltage gain, current gain, input and output conductances.
Part E1: Esempio di progettazione di un amplicatore CS
T6 A2
Esempio di progettazione con MOSFET.
Part A3: Basic MOSFETbased congurations
T6,A2 N1
MOSFET: diode conguration, current mirror, dierential amplier.
Part T7: Ampliers frequency response
T4 T5
Bandwidth, pole-dominant approximation, time-constant method.
Summary
Part A4: Timeconstant method application
T7
Example of the time-constant method.
Part T8: Ideal voltage amplier and feedback
A3
Ideal parameters, circuit model, comparison with CS, CD, CG congurations, introduction of multi-stage ampliers, active load. Feedback, unilar model: advantages and disadvantages in ampliers. Feedback topologies.
Part A5: Ideal voltage amplier and feedback applications
T8
Ideal voltage amplier and feedback applications
Part T9: Stability analysis of feedback ampliers
N1,T7 T8
Stability analysis: gain and phase margins, compensation techniques.
Part E2: Compensation examples
T9
Compensation examples.
Part T10: Techniques used to analyze feedback ampliers
T7 T8
Rosenstark and Blackman techniques.
Summary
Part E3: Examples of the Rosenstark and Blackman formulas
T10
Examples of the Rosenstark and Blackman formulas.
Part E4: Esercizi su amplicatori, retroazione e compensazione
T7,T8 T9,T10
Esercizi su amplicatori, retroazione e compensazione.
Part T1
Notes on Electricity
See [?]
Electric eld E
E = lim
Q0
F Q
P Q (Static conditions)
The electric eld vector E in a point is the electric force per unit charge exerted on a probe placed in the same point and whose charge tend to 0. (T1.1) Sclosed =
Sclosed
Flux of E
E n dS
E n
S
Q1 Q5 Q3
Gauss law in vacuum
Sclosed E =
Q 0
experimentally assumed
Q2
Q4 Q7 Figure T1.1
Q6
where the electrical permittivity in vacuum (0 ) is equal to 0 = 8.85412 1012
F m
Example (Fig. T1.1)

Sclosed
E n S =
Sclosed
En S =
Q1 + Q2 + Q3 + Q5 0
Joint constant between dimensions of Sclosed E and Q
Meaning of 0
(T1.1)
C2 [Charge] [F orce] [Surf ace] = [0 ] = [Charge] [0 ] [N m2 ]
for homogeneous and innite (i.e., unbounded) media
permittivity
(T1.2)
Sclosed E = Q r > 1
Sclosed E =
where = r 0
Electric displacement eld (or electric ux density) D
In most ordinary materials D = E
(T1.3)
VP = W
Electrostatic potential V
P O
where W
path connecting points P and O.
P O
E is the work (the amount of energy) transferred by E along an arbitrary
P O
W + W =0
OP
Electrostatic potential property (I)
P O
W = W
OP
O VP O = VOP Figure T1.2
P c
Electrostatic potential property (II)
(T1.4)
(T1.4)
P P
W = VP O + VOP
P P
a (T1.5) b O P
W = VP O VP O
Figure T1.3
10
WP P = V (V + V ) WP P = E x x WP P = Ex x
(T1.3) E
(T1.5)
E V on x dimension
Ex =
V x dV V = x dx
V P Ex
V +V P
(T1.6)
Ex = lim
x0
Figure T1.4
U = qV
Potential energy U
if q = qel = 1.6 1019 C q 1 V = 1 eV = 1.6 1019 J (1 eV is a very small amount of energy) P
. E P
Energy conservation law

(T1.6)
W = U + EC
where EC =
1 mv 2 2 0 V (x)
V d x
V (x) = E x + CON ST U (x) = q V (x) U (0) = 0
Example: potential energy barrier
1 2 U (0) + mv0 = W 2 x0 : vx0 = 0 U (x0 ) + 0 = W Ec must be positive so U (x) is a potential energy barrier for electrons; in the gure electrons cannot be at a distance greater than x0 from electrode P.
U (x) P EC x0 Figure T1.5 x

W
.
+ + + + +
Metal conductivity schematic picture

.
Free electrons
+ + + + +
Bound iones
+ + + + +
Figure T1.6
11
In the steady state (T1.7) v d = E = vd E [] =
(mobility)
where v d is the drift velocity. m2 V s . One dimensional example (Fig. T1.7)

O
vol=LA e E L wire
J P
A x
Figure T1.7 (T1.8) |v d | = L T I = electric charge owing through any cross section of the wire in the time unit N = number of electrons in volume L A I =
(T1.8)
J (current density)
qN T q N vd L
I = J=
q N vd I = A LA qN qN = we have: setting = LA vol (T1.9)

(T1.7)
J = vd
J = E J = E
Conductivity
= V =
Fig. T1.7 (T1.6) xP 0
E dx = E L
I =J A=
V V A= (expressed in module) L R
Resistivity
=
RA 1 and = L
Part T2
Semiconductor physics
See [?]
Band Theory of Solids
Plot of the available energies for electrons in the materials. The available energy levels form bands instead of discrete energies. For the conduction process is crucial whether or not electrons are in the conduction band and the energy gap amplitude (Eg ) between the valence band and the conduction band. .
Conduction band Conduction band
Conduction
Insulators, semiconductors and conductors
Eg 5 eV
Valence band
Eg 1 eV
Valence band
Conduction band Valence band
Insulators
Semiconductors
Conductors
Eg = 4 eV is the energy threshold between insulators and semiconductors.
13
Conduction band and Valence band

Although the number of states in the bands is actually innite, in an uncharged material the number of electrons is equal to the number of protons in the atoms, i.e. not all the possible states are occupied by electrons at any time. The probability of a given energy level to be occupied by an electron is given by: 1.2 1.0
6
EF /kT = 100
1+e
1
EEF kT
f (E)
Fermi-Dirac statistics
(T2.1) f (E) =
f (E) = 1 1+e
E EF
0.8 0.6 0.4 0.2
EF /kT = 0.1
EF kT
EF /kT = 1
0
11
22
33 44 E/EF
55
66
where k is the Boltzmann constant (k = 1.380 1023 J/K), T is the temperature in Kelvin, EF is the Fermi energy.
Electrical conductivity
Electrons must move between states to conduct an electrical current, so due to the Pauli exclusion principle full bands do not contribute to the electrical conductivity. E
Conduction band
E
Conduction band
E
Conduction band
(T2.1)
EF
EF
EF
Semiconductors
Valence band
Valence band
Valence band
f (E) T =0K Medium temp.
f (E) High temp.
f (E)
The electrons population in a given energy state depends on the Fermi function and on the electrons density in that state. In the gap there are no electrons because the density state is zero. At T = 0 K and for energies higher than the Fermi level, the Fermi function is zero (see gure) and so there are no electrons in the conduction band even though many free states are available.
14
If a voltage is applied to the semiconductor, for T > 0 K we have: . Electrons current Si Si Si Si Si Holes current
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Semiconductors current pictures
e .
hole+
electrons
C.B. + V.B.
+ + + + + + holes
. .
. Si
donor impurity contributes to free electrons
Si
acceptor impurity creates holes
Si
Si
Si
Si
Si
Doped semiconductors
n-type
FL
Si
Conduction band
p-type
Conduction band
FL
Valence band Valence band
15
p = holes concentration
Symbols
n = electrons concentration
(T1.7)
Conductivity for semiconductors
J = E = (nn + pp ) q E = = (nn + pp ) q p = n = ni e.g. for silicon ni =
(J and E are expressed in module)
Intrinsic semiconductors
1022 at T = 25 C and increases as temperature increases. cm3 cm2 n = 1350 V s = = (n + p ) ni q cm2 p = 500 V s
Introduction of DONOR atoms leads to a donor concentration ND = 1014 1021 atoms . cm3
Doped semiconductors n-type
For charge neutrality

+ (T2.2) ND + p = n
np
n ND
(T2.2)
at T = 25 C
Introduction of ACCEPTOR atoms leads to an acceptor concentration NA = 1014 1021 atoms . cm3
Doped semiconductors p-type
For charge neutrality

(T2.3) NA + n = p
pn
p NA
(T2.3)
at T = 25 C
Often semiconductors are doped with two types of doping atoms ND , NA with concentrations strongly dierent, ND NA for n-type semiconductors and NA ND for p-type semiconductors for p-type p NA ND for n-type n ND NA Conductivity can be controlled by introducing specic concentration of doping atoms.
16
When a p-n junction is formed, some of the free electrons in the n-region diuse across the junction and combine with holes forming negative ions. A space charge region builds up and a depletion region is created: the equilibrium is reached when the Coulomb force from ions inhibits any further transfer of electrons, in this condition the n-type and the p-type have the same Fermi level.
p-type
n-type .
p-n junction
. p n
p-type p-type
n-type . ++ ++ ++ + +
EF .
n-type
p n .
or
p n
. -
electrons lled holes
depletion region (W ) . holes removed electrons
+ + n
thermal current E p
p n
- -- ++ + + + +
Reverse bias
p
.
n
Figure T2.1
U = qV = Epotential of electrons in equilibrium condition. The applied voltage impedes the ow across the junction. For conduction in the device, electrons from the n region must move to the junction and combine with holes in the p region. The reverse voltage drives the electrons away from the junction.
(T1.6)
17
+ + n
E p
p n
+ + + +
Forward bias
p
.
The applied voltage assists electrons in overcoming the Coulomb barrier in depletion region. At the junction electrons and holes combine so that a continuous current can be maintained. Non-linear relation between current iD and voltage vD . . iD iD [A]
vD
1103
p-n diode
reverse current (IS ) 0.2 0.4 0.6 vD f orward bias
[V ]
reverse bias
Figure T2.2
(T2.4)
iD = IS e VT 1
vD
Diode equation
where VT = for for vD
vD < 5 VT
kT T = VT = 25mV at T = 25 C qel 11600 vD > 5 VT iD IS e VT iD IS
Diode dynamic eects: transaction capacitance
Reverse biasing voltage drives electrons and holes away from the junction, consequently the depletion region (positive and negative ions) increases with reverse voltage. A Q = (T2.5) CT = v W - - ++ - - ++ - - ++ - - ++ where A is the diode section area, W is the p-type n-type width of the depletion region and is the diW electric constant of the depletion region. . absence of free chagersinsulator
18
Forward biasing: the number of electrons crossing the junction depends on the forward voltage and the time before an electron recombines with a hole is nite, conseguently a capacitive eect arises.
Diode dynamic eects: diusion capacitance
Q CD = Q = iD T v where T is the time before an electron recombines with a hole. vD TS e VT T iD = T CD = v VT (T2.6) CD T iD VT
Actual diode maximum limits
Maximum reverse voltage: vbreakdown (reverse biasing) Maximum power dissipation: PD = vD iD (forward biasing) Breakdown eect is due to two dierent phenomena: Zener breakdown occurs predominantly with heavily doped junction regions and a low reverse voltage (< 6 V ). The high E removes electrons that can pass through the junction [?]. Avalanche breakdown occurs at high reverse voltage ( 6 V ): free electrons near the junction acquire high kinetic energy (being in a uniform acceleration eld) and so a high speed. As these high-speed electrons move through the material they inevitably strike atoms knocking an electron free from it. Both electrons are then accelerated by the electric eld and strike other atoms knocking additional electrons free and so on. In this way the reverse current rapidly increases [?]. Reverse bias .
Breakdown eect
p
.
+ + + + +
E
19
From a technological point of view, the Zener diodes are built so that the breakdown eect is possible at a suciently low reverse voltage thus preventing the overcoming of the maximum PD . . iD iD [A]
+
Zener diode
vD
breakdown region
vD [V ]
reverse bias f orward bias
Part T3
Diode as non-linear device
The diode equation (T2.4) can be expanded in Taylor series, linear circuit laws are usable when the series can be limited to the rst order:
Diode as non-linear device: circuit analysis
iD = iD0 +
(T2.4)
d iD d vD
vD =VD0
(vD VD0 ) +
1 d2 iD 2 2 d vD
vD =VD0
(vD VD0 ) +
VD0 = VD0 = 0V a b
vD VD0 = vD = vd = vD
Linear piecewise (OFF region)
iD
IS 1 IS 2 =0+ vD + 2v VT 2 VT D
if a b (i.e., a 10 b (T3.1) iD IS vD VT
10 IS 2 VT IS vD vD = 5mV ) then 2v VT 2 VT D 5
Equivalent resistance and equivalent circuit
vD rOF F
(T3.1)
vD VT = = iD IS
iD r OF F

Fig. T2.2
21
iD [A] iD [A]
Graphic picture of the diode linear piecewise in OFF region

.
21012 110
3
vD [mV ]
0.6
vD [V ] Figure T3.1
vD 5VT = 125mV = VD0 (T2.4)
VD0 = VD0 = 5VT = 125mV
(25 C)
Linear piecewise (ON region)
iD IS evD /VT = IS e(VD0 +vD )/VT vD =vd iD =id (T3.2) vD =VD0 + vd

(T3.2)
ID 0
iD = IS eVD0 /VT evD /VT = ID0 evd /VT

approx.
T aylor
iD = ID0 +
ID0 1 I 0 2 vd + D2 vd + VT 2 VT
if
ID0 1 I 0 2 VT vd 10 D2 vd vd = 5mV then (small signal conditions) VT 2 VT 5 ID0 vd VT
(T3.3)
iD = ID0 +
Dierential conductance
(T3.4)
g=
iD vD
=
vD =VD 0
I d iD = D0 d vd VT
Dierential resistance
(T3.5)
rON =
1 g
22
iD in forward region and small signal conditions
vd = vD VD0 iD = ID0 + iD = ID0 (T3.3)
(T3.2)
ID0 vD VD0 VT
VD0 VT
+ g vD . iD
Norton equivalent circuit (ON region)
Ieq = ID0
VD0 VT
Ieq
1 g
vD
.
theorem T hevenin
Veq =
Ieq = ID0 g
VD0 VT
1 g
vD in forward region and small signal conditions
Veq = ID0
VT VD0 VT
VT = VD0 VT ID0
(T3.6)
vD = Veq +
iD g . iD
Veq
Thevenin equivalent circuit
(T3.6)
1/g vD
23
. iD [A]
2103
A Vd0 ; Id0 B (V ; 0)
1103 0.5103 B 0.62 0.65
iD (A) 5 104 1 103 2 103 5 103
vD [V ] 0.62 0.63 0.65 0.67
Graphic picture of the diode linear piecewise in ON region

(T3.7)
vD [V ]
. Figure T3.2
tg
iD iD vD vD
=g
VD 0
(T3.6),Fig. T3.2
V = Veq = VD0 VT
(T3.8)
ID0 =2 103 A g=0.08S V = 0.62V r=1/g = 12.5
24
See Breakdown eect (
pag. 18) iD [A] .
Graphic picture of the diode linear piecewise in breakdown region
VZ
tg vD [V ]
ID0
. Figure T3.3
without considering the analytic expression of iD in breakdown zone, the 1 angular coecient of the geometric tangent in ID0 can be outlined; tg = gZ = rZ Veq = vD when iD 0
(T3.6)
(T3.7)
Zener voltage Zener resistance
graphically Veq = VZ rZ =
(T3.5),(T3.7)
1 tg . iD
actually iD is negative
VZ .
Zener diode equivalent circuit in breakdown region
(T3.5),(T3.6)
vD = VZ + iD rZ
(T3.9)
rZ vD
25
Generally the three linear piecewise are extended for larger values of vD (large signal conditions)
Linear piecewise approximation (LPA) for diodes
.
(T3.6) (T3.5),(T3.7) (T3.1)
region OFF vD = rOF F iD ; iD 0A vD = V + rON iD for for
condition Vbr. < vD < V vD > V (T3.10)
. .
I . II
ON
(T3.11)
region OFF vD = rOF F iD ; iD 0A vD = V + rON iD vD = VZ + rZ iD for for for
condition VZ < vD < V vD > V vD VZ (T3.12)
LPA for Zener diodes

(T3.8) (T3.11)
(T3.10)
. . .
I . II .
ON
III Zener
vD iD region . . I OFF iD rOF F vD VZ vD < V vD ON iD . . III Zener iD vD V vD vD VZ rON vD V condition
Zener diode equivalent circuits
. . II
iD
VZ
rZ
iZ
26
.
BEGIN
by means of circuit considerations
randomly Choose a region
Slitly more complex because a preliminary circuit analysis is required, but less time consuming Insert in the circuit the equivalent circuit associated with the choosen region
simpler, but it could be time consuming
How to choose the right region
Solve the linear circuit obtained after substitution
Are constraints of the choosen region verified?
NO
YES
The right operating region was choosen
END
Part A1
Diode applications
vI t
Rectier
vI
vO vO
vI t
Bridge rectier
vI
vO vO
Diode applications
28
vI t
Rectier with lter
vI
vO vO
Amplitudemodulation detector
The circuit schematic is the same of the rectier with lter but with a dierent RC time constant: the RC time constant must be higher compared with the period of the carrier, and it must be lower compared to the period of the modulated signal.
Zener regulated power supply
Diode applications
29
vI t
vI
vO vO
VZ V
Zener limiter
vI
t vI
vO
VZ +V
vO
(VZ +V )
Part T4
MOSFET device
MAP VIEW
GATE OXIDE Si O2
tox GATE
L W
vG
P-SUBSTRATE (BODY) SUBSTRATE METAL CONTACT
MOSFET as capacitor with capacitance depending on gate voltage
vG < 0
holes move towards the surface that becomes a zone where electrons can move. L Ceq 1 = ox A tox vG
tox is the Si O2 thickness ox is the Si O2 electrical constant A = L W is the gate area

SUBSTRATE METAL CONTACT OXIDE Si O2 P-SUBSTRATE (BODY)
GATE
tox
0 < vG < Vth
(Vth 1V )
Near the surface a depletion charge zone is created (negative ions). In this region electrons cant move. L
Ceq 2
A ox = tox + tdp
+ + + + +
OXIDE Si O2
GATE
tox tdp
vG

P-SUBSTRATE (BODY) SUBSTRATE METAL CONTACT
MOSFET device
31
vG Vth
INVERSION LAYER Free electrons in the p-substrate move towards the surface under the oxide. ox A = Ceq 1 = Cox Ceq 3 = tox L
++++++++++ vG
P-SUBSTRATE (BODY) SUBSTRATE METAL CONTACT OXIDE Si O2
GATE
tox til (inversion zone)
Figure T4.1 (T4.1) QIN V = Cox (vG Vth ) = Cox (vOX Vth ) Ceq (vG = vOX )
Cox
Ceq2 VT vG
MOSFET device
32
vDS
vGS
iS
S
+ vBS SOURCE
GATE
iD
D
i(x)
DRAIN
n+
n+
DEPLETION ZONE
MOSFET device structure when inversion layer is present
P-SUBSTRATE
BODY
B
x
Figure T4.2
Symbols
A position on the inversion layer is characterized by v(x) and i(x) where v(0) = v(S) 0, furthermore iD = iS .
D G S B G
(T2.4) + + vBS : n source - p substrate and n drain - p substrate diodes are reverse biased.
Charge in the inversion layer

Fig. T4.2
(T4.1)
Q(x) = ox tox
W L ox (vOX (x) VTn ) = W L Cox (vOX (x) VTn ) tox
(T4.2)
where Cox =
F m2
Medium charge density
(T4.3)
Fig. T4.1
v =
Q W L til
where til is the thickness of the inversion zone (Fig. T4.1).
Current iD when inversion layer is present
i(x) = J(x) W til where J(x) is the current density.

(T1.9) (T4.3) (T4.2)
i(x) =
Q(x)vd Q vd W til = W L til L W L ox vd (vOX (x) VTn ) tox L
i(x) =
MOSFET device
(T1.7)
33
i(x) =
W ox (vOX (x) VTn ) (n E(x)) tox
where n is the electrons (n carriers) mobility. i(x) = W with (T4.4) vOX (x) = vGS v(x) v(x) = vGS vOX (x)
i(x) = W Cox (vGS v(x) VTn ) n (T4.4) (T1.6)
d v(x) ox (vOX (x) VTn ) n tox dx

Cox
d v(x) dx
i(x)d x = n W Cox (vGS v(x) VTn ) d v(x)
by integrating x from 0 to the channel length L and v(x) from 0 to vDS

L 0 i(x)d x = n W Cox vDS 0
[(vGS VTn ) v(x)] d v(x)

2 vDS 2
iD L = n W Cox (vGS VTn ) vDS
being i(x) = iD = constant (T4.5) iD = kn vGS VTn vDS vDS 2
W A . [kn ] = 2 L V kn depends on the technology characteristic.

with kn = n Cox and kn = kn
vOX (x) VTn
(T4.4)
Validity eld of (T4.5): triode region
vOX (x) = vGS v(x) VTn v(x) as its maximum for x = L where v(x) = vDS vGS vDS VTn (T4.6) vDS vGS VTn
MOSFET device
(T4.5)
34
iD = 0 for
d iD = kn [(vGS VTn ) vDS ] = 0 vDS = vGS VTn d vDS iD /kn

6
vDS = 0 vDS = 2 (vGS VTn )
maximum
vGS
Graphics of iD vs. vDS in triode region
0 0 1 2 3 4 5 6
vDS vGS VTn = vDS kn 2 kn (vGS VTn )2 = v iD = 2 2 DS

(T4.6)
MOSFET as Voltage Controlled Resistor (VCR)
for vDS vGS VTn

(T4.5)
vDS
vGS VTn 10
iD kn (vGS VTn ) vDS 1 vDS 1 = = ReqV CR = iD iD kn (vGS VTn ) vDS vDS =0 Fig. T4.3 for vDS vGS VTn when vDS = vGS VTn
MOSFET in saturation region
and
(T4.4)
vOX (0) = vGS vOX (L) = vGS vDS = VTn
Q(x)|x=L = 0 therefore for x = L the inversion layer thickness is 0 and the current reaches its maximum value.
(T4.2)
MOSFET device
35
vDS
vGS
POF F
iS
S
+ vBS SOURCE
GATE
iD
D
DRAIN
n+
n+
DEPLETION ZONE
P-SUBSTRATE
BODY
B Figure T4.3 for vDS > vGS VTn

(T4.4)
Find x : vOX (x) = VTn v(x) = vGS VTn < vDS
vOX (x) = vGS v(x) = VTn and Q(x)|x=L = 0

(T4.2)
therefore for x = L the inversion layer thickness is 0 and the current reaches its maximum value.
vDS
vGS
+ POF F GATE
iS
iD
S
+ vBS SOURCE
n+
DEPLETION ZONE
D n+ DRAIN
P-SUBSTRATE
BODY
B Figure T4.4 for x = POF F the inversion layer is depleted, but electrons in POF F can still reach the drain due the electrical eld created by the voltage vDS VPOF F = vDS (vGS VTn ). id does not decrease and therefore the current reaches a saturation value.
Pinch-o point
MOSFET device
36
iD
Saturation region
(T4.6)
iD =
kn 2 (vGS VTn ) 2
(T4.7) vGS VTn Figure T4.5
iD /kn
vGS
MOSFET is a voltagecontrolled current generator
0 0 1 2 3 4 5 6
Figure T4.6
vDS
Actually for vDS vGS VTn (saturation region) the inversion layer length is Lil L iD = with Lil
(T4.7) (T4.7) kn W 2 (vGS VTn ) 2 Lil 1 L = Lil + L(vDS )
Channel modulation eect
vDS k W 2 iD = n (vGS VTn ) 2 L L(vDS )

kn W 2 2 (vGS VTn ) (1 + vDS ) = kn (vGS VTn ) (1 + vDS ) 2 L kn
(T4.8)
iD
103 < < 101
V 1
Body eect (substrate bias eect)
The substrate tension should be kept as lower as possible to avoid the conduction of diodes B-S and B-D. When vBS = 0, the width of the depletion layer and therefore also the voltage across the oxide are modied due to a change in the charge of the depletion region. This results in a dierent threshold voltage (T4.9) VTn = VT0 + vSB + 2F 2F
being F a physical parameter such that 2F = 0.6 V = 0.4 V 1/2 a technology related parameter and VT0 = Vth when vBS = 0.
MOSFET device
(T4.5),(T4.8) (T4.9)
37

vGS +
vDS
iS
S
+ vBS
GATE
iD
D p+
DRAIN DEPLETION ZONE
p+
SOURCE
Symbols
D G S B G SB D
N-SUBSTRATE
Extension to p-channel MOSFETs
BODY
B Figure T4.7 inversion layer is present when vGS < 0 V holes (positive charges) produce a current iD < 0 and move from the source when vGS < 0 V Regions S-B and D-B are diodes substrate (body) must not conduct then vBS > 0 V (the substrate tension should be kept as higher as possible to avoid the conduction of diodes S-B and S-D). VTp < 0 V
MOSFET-p triode current MOSFET-p saturation current
(T4.10)
iSD = kp vSG VTp
vSD vSD 2
(T4.11)
iSD =
kp vSG VTp 2
(1 + vSD )
MOSFET: limits of operation
Due to the MOSFET physical structure, it mainly has the following limits: Gate oxide breakdown (maximum VGS voltage): the gate oxide thickness (tox ) is very thin (in the order of 100 nm or even less for the technologies), so it can only sustain a limited voltage. Exceeding this limit can result in destruction of the device or in the reduction of its lifetime. Maximum VDS voltage: the MOSFET device has a maximum specied drain to source voltage, beyond which breakdown may occur. Exceeding the breakdown voltage causes the device to turn on, potentially damaging itself and other circuit elements due to excessive power dissipation.
Part T5
Bipolar Junction Transistor (BJT)
C C n p n+ E iE B
C B-C B B-E
Bipolar Junction Transistor (BJT): physical structure
iC iB
E
n+ tB
Si
n tB=0.1100m
n-p-n E-B-C
Figure T5.1
A BJT cannot be considered as two back-to-back diodes due to the thin thickness of the base region (tB ).
Energy
C-B-E: energy bands when the BE junction is forward biased and the BC junction is reverse biased. The forward bias on the BE junction causes electrons to move toward the base. Some of the electrons will combine with holes. However, since the base region length (tB ) is very thin and usually smaller than the electrons diusion length (mean length within which electrons combine with holes), the percentage of combined electrons is very small. Thus, most of the electrons reach the boundary of the BC depletion region. Because the collector is more positive than the base (the BC junction is reverse biased), these electrons are dragged into the collector across the BC depletion region.
Conduction when B-E is forward biased and B-C is reverse biased (graphic picture)
B-C
B-E
Figure T5.2
n C p n+ E
vCB
vBE
39
n C
n+ E iE
n-p-n BJT
C B E
BJT current when vBE = 0 and vBC = 0
iC
iF iB vCB B vBE
iC = iF
iB current when vBE = 0 and vBC = 0 iC current when vBE = 0 and vBC = 0
(T5.1)
iB =
iF F
20 < F < 500
iF = iC
(T2.4)
iC IS evBE /VT 1
(T5.2)
forward transport current
iE = iC + iB
iE current when vBE = 0 and vBC = 0
(T5.3)
iE =
F + 1 IS evBE /VT 1 F
n+ E iR iE
C iC iB vCB B vBE
iE = iR
iB current when vBE = 0 and vBC = 0 iE current when vBE = 0 and vBC = 0
(T5.1)
iB =
iR R
(T5.4)
0 < R < 20
iR = iE
(T5.2)
iR IS evBC /VT 1
(T5.5)
inverse transport current
40
iC = iR iB
iC current when vBE = 0 and vBC = 0
(T5.3)
iC =
R + 1 IS evBC /VT 1 R
(T5.6)
iC = IS evBE /VT 1
(T5.6)
(T5.2)
R + 1 IS evBC /VT 1 R
iC = IS evBE /VT evBC /VT
IS evBC /VT 1 R
iC current when vBE = 0 and vBC = 0
(T5.5)
iC = iT
iR R
(T5.7)
iE = IS
(T5.5)
(T5.3)
iE current when vBE = 0 and vBC = 0
iE = IS
(T5.2)
F + 1 vBE /VT 1 IS evBC /VT 1 e F IS evBE /VT evBC /VT + evBE /VT 1 F iE = iT + iF F (T5.8)
iB current when vBE = 0 and vBC = 0
iB =
iR iF + R F IS IS evBC /VT 1 + R F evBE /VT 1 (T5.9)
iB =
BJT non-linear circuit model: transport model
C iC
(T5.1),(T5.7)
iT
E iE

(T5.4),(T5.9)
iR R
iB
iF F
41
Forward Active Region (FAR)
IS IS evBE /VT iC IS evBE /VT + R IS vBE /VT F + 1 (T5.8) iE IS evBE /VT + e iC F F iC IS vBE /VT IS (T5.9) + e iB R F F
(T5.7)
vBE V
vBC 0
(T5.10)
vBC V
(T5.7)
vBE 0
Reverse Active Region (RAR)
IS vBC /VT e R R + 1 vBC /VT R + 1 iC IS e iE R R IS (T5.8) IS evBC /VT iE IS evBC /VT F IS vBC /VT IS iE (T5.9) iB e R F R iC IS evBC /VT vBE V1 vBC V2
Usually V1 > V2 due to dierent doping concentrations in the emitter and collector regions. iC IS evBE /VT
(T5.7)
vCE = vBC + vBE 0.2 V
BJT: Saturation Region (SR)
F + 1 vBE /VT e F IS vBE /VT IS vBC /VT (T5.9) iB + e e F R iE IS

(T5.8)
iBSAT > iBF AR (T5.11) iCSAT = F ORCED iBSAT
iBSAT >
iC F
F ORCED < F
vBE 4VT
vBC 4VT
4VT 0.1 V at T = 25 C
BJT: Interdiction Region (IR)
iC
IS R IS (T5.8) iE F IS IS (T5.9) iB F R
(T5.7)
42
C iB B vBE E
iC vCE iE
Graphics pictures of iC vs. iB and vCE in FAR
vCE = vBC + vBE FAR: vBE + vCB = vCE 0.7 V + vCB = vCE
iC
(T5.10)
iB 1 A
1 mA
0.7 V
vBE
0.7 V
vBE
iC iC vCE RAR 20 A 1 mA SAT FAR
iB
iB
RAR
0.7 V
5 V vCE
43
Early eect
When the forward active region is considered, given vBE , increasing vCE increases the reverse voltage on the collector-base junction and thus increases the width of the collector-base depletion region. Accordingly, the eective base length decreases and thus the percentage of electrons that can reach the collector-base junction increases. Since (given vCB ) the collector current is proportional to the percentage of electrons able to reach the collector-base junction, the increased amount of electrons leads to a greater collector current. This is the Early eect. This eect can be accounted for by including a factor in the collector current in (T5.10) iC (T5.12) iB iE IS evBE /VT 1+ vCE VA iC
IS vBE /VT e F = iC + iB
where VA is the Early tension.
VA
vCE
BJT physical limits
Maximum reverse voltage (vBC in FAR, vBE in RAR) Maximum power dissipation (iC vCE )
Part T6
MOSFET and BJT as non-linear devices
MOSFET as a non-linear device

1) Triode region vDS vGS VTn The Taylor series of (T4.5) in a neighborhood of iD = ID , vDS = VDS , vGS = VGS is iD = ID +
(T4.5)
MOSFET: LPA with vBS = 0 in triode region
iD vGS
vGS +
VDS , VGS
iD vDS
vDS + . . .
VGS , VDS
iD = ID + kn VDS vGS + kn (VGS VTn VDS ) vDS + . . . If components of order higher than the rst can be neglected then (T6.1) iD = ID + gm vgs + g0 vds
where, by denition, vDS = vds gm = kn VDS

biasing
vGS = vgs g0 = kn (VGS VTn VDS )
iD = ID + gm vgs + g0 vds = ID + id
linear behavior
45
2) Saturation region vDS > vGS VTn The Taylor series of (T4.8) in a neighborhood of iD = ID , vDS = VDS , vGS = VGS is kn 2 iD = ID + kn (VGS VTn ) (1 + VDS ) vGS + (VGS VTn ) vDS 2 1 2 + kn (1 + VDS ) vGS + kn (VGS VTn ) vGS vDS + . . . 2 by dening
(T4.8)
MOSFET: LPA with vBS = 0 in saturation region
vgs = vGS
vds = vDS 2ID VGS VTn
(T6.2) gm = kn (VGS VTn ) (1 + VDS ) = g0 = ID kn 2 (VGS VTn ) = 2 1 + VDS
if components of order higher than the rst can be neglected then (T6.3) iD = ID + gm vgs + g0 vds
iD = ID + gm vgs + g0 vds = ID + id
biasing
5
linear behavior
iD /kn
ID 3
vGS iD vDS iD vDS
Geometric interpretation of g0
g0 =
VGS
VGS
0 0 1 2 3 4
VDS
Figure T6.1
vDS
iD
vDS
Geometric interpretation of gm
ID gm = iD vGS
VDS
iD vGS
VDS
VTn VGS Figure T6.2
vGS
46
MOSFET: LPA conditions in saturation region (small signal)
1 2 If kn (VGS VTn ) (1 + VDS ) vGS kn (1 + VDS ) vGS , iD can be represented 2 by a linear function. The previous condition leads to vGS 2 (VGS VTn ) vGS (T6.4) vGS 1 (VGS VTn ) 5 .
G D
2 (VGS VTn ) 10
id 1 g0
MOSFET equivalent circuit for id
(T6.5)
id = gm vgs + g0 vds ig = 0
gm vgs
S
iD = ID (VGS , VDS , VBS ) + id

(T6.3)
(T4.8),(T4.9)
(T6.6) id = gm vgs + g0 vds + gmb vbs . id
MOSFET equivalent circuit when vBS = 0
gm vgs
1 g0
gmb vbs
Figure T6.3
Evaluation of iD by means of circuit theory
Being the circuit related to the linear iD , it can also be evaluated by means of the superposition principle: . circuit (T6.7) circuit . 2 id = iD when ID = 0
ID = iD
when
id = 0
linear-circuit analysis laws can be used
MOSFET parasitic capacitances: triode region
MOSFET equivalent circuit under small-signal condition (input signals have small variations with respect to the biasing (T6.6),Fig. T6.3 point) must be completed to take into account capacitive effects intrinsic in the MOSFET physical structure.
(T4.1),(T6.3)
47
Lov
Lov
GATE
S
Fig. T4.2 (T4.5)
SOURCE
D
DRAIN
n+
n+

P-SUBSTRATE
BODY
B
CGchannel = Cox = Cox A
(T6.8)
CGS = CGD =
1 C WL 2 ox
Due to the MOSFET technology process, source and drain diusions extend by Lov below the thin oxide (lateral diusion) giving rise to overlap capacitances equal to Cov = W Cov where Cov = Lov Cox 1 C W L + W Cov 2 ox
(T6.8)
CGS = CGD =
(T6.9)
CDB , CSB (transaction capacitances across the inverse-biased junction B-D and B-S)
(T2.5)
Lov
Lov
GATE
S
Fig. T4.3 (T4.7)
SOURCE
D
DRAIN
n+
n+
MOSFET parasitic capacitances: saturation region

P-SUBSTRATE
BODY
B 2 C W L + W Cov 3 ox = W Cov
(T6.8)
CGS CGD
(T6.10)
48
CGD gm vgs CGS 1 g0 gmb vbs
MOSFET linear equivalent circuit in high frequency condition
CDB
S
CSB
Figure T6.4
When the input signal frequency f is such that (T6.11) 1 Rs Cx 2f 10 1 Rp Cx 2f 10

CX
(T6.12)
When can parasitic capacitors be neglected?
vo =
Rs vx 1 Rs + j2f Cx
vx
Rs
vo
vo j2f Cx Rs = = vx 1 + j2f Cx Rs vo = vx
2f Cx Rs 1 + (2f Cx Rs )
2
(T6.11)
2f Cx Rs 1 + (2f Cx Rs )
2
for
1 Rs 2f Cx
(T6.13)
1 j2f Cx io = ix 1 + Rp j2f Cx io 1 = = ix 1 + j2f Cx Rp io = ix 1 1 + (2f Cx Rp )

2
io ix CX Rp
1 1 + (2f Cx Rp )
2
(T6.12)
for
1 Rp 2f Cx
(T6.14)
49
BJT as non-linear device

(T6.1)
By applying to equation (T5.12) the same procedure used for MOSFET ( pag. 44) we have that the Taylor series of (T5.12) in a neighborhood of iC = IC , iB = IB , vBE = VBE vCE = VCE is iC = IC + gm vbe + g0 vce
biasing linear behavior
(T6.15) iB = IB +
biasing
g vbe
linear behavior
BJT: LPA
where (T6.16) gm = iC vBE =

vCE
IC VT
(T6.17) g0 =
iC vCE
=
vBE
IC IS evBE /VT = VA VA + VCE
(T6.18) g =
(T6.16) (T6.18)
IC gm diB = = dvBE VT F F gm = gm r g g = 1 r
F =
(T6.15)
ic = gm vbe + g0 vce
ib
(T6.19)
ib = g vbe
Equivalent circuit
B C
BJT equivalent circuit
ic gm vbe
r
E
r0
Figure T6.5 IC = iC when ic = 0 IB = iB when ib = 0 ic = iC when IC = 0 ib = iB when IB = 0 small signal
BJT: Evaluation of ic and ib by circuit theory
biasing

(T6.7)
(T6.15)
50
BJT: LPA conditions in FAR region (small signal)
In analogy with the LPA conditions for MOSFET, the linear approximation
(T6.4)
(T6.15)
can be accepted if (T6.20) vBE = vbe 2 VT = 5 mV 10
Part N1
Basics of Electrical Theory

See [?], [?], [?]
Two-port networks (Quadripoles)

Denitions A Quadripole is an electrical circuit or device with two couple of terminals called input and output terminals. VI = V1 V1 is the input voltage, VO = V2 V2 is the output voltage, I1 , I1 are the input currents and I2 , I2 are the output currents. Note that voltages are referred V1 , V1 , V2 , V2 to the ground node and that currents I1 , I1 , I2 , I2 are conventionally taken as shown in the gure.
I1
1
I2
2
Quadripoles
VI
1
I1
Quadripole
I2
2
VO
INPUT TERMINALS
OUTPUT TERMINALS
Dierential input
The quadripole has a dierential input when ports 1 and 1 are controlled by two independent voltage (or current) generators. The quadripole is said to have a single input when one of the two input ports (port 1 for example) is wired to ground and the other one (port 1 for example) is controlled by an independent voltage (or current) generator.
VI1 VI2
ZS1 ZS2
1
Quadripole
Single input
VI1
ZS1
1
Quadripole
52
The quadripole has a dierential output if none of the output terminals is directly connected to ground.
Dierential output
Quadripole
ZO1
2
Quadripole
ZO
2
ZO2
Single output
The quadripole has a single output if at least one of the two output ports (port 2 for example) is wired to ground.
Quadripole
ZO
2
A quadripole is said to be linear when the relationship between input and output electrical variables can be written with linear equations. There are many ways to describe a linear quadripole, but the most common is the so called Z-parameters (impedance parameters), usually expressed in matrix notation: (N1.1) where VI VO = Z11 Z21 Z12 Z22 II IO VI = Z11 II + Z12 IO VO = Z21 II + Z22 IO VO II VO IO
Single-input, single-output linear quadripoles
(N1.2)
Z11 =
VI II
Z12 =
IO =0
VI IO
Z21 =
II =0
Z22 =
IO =0
(N1.3)
II =0
II
VI
Quadripole
VO
VI
Quadripole
VO
IO
The quadripole is said to be reciprocal if Z12 = Z21 . Note that Z11 , Z12 , Z21 , Z22 are function of s in the Laplace domain, are phasors in sinusoidal steady state, and in the special case when the frequency tends to zero they are constant (DC condition).
Let us consider a quadripole with a voltage (current) generator ES (IS ) at its input and loaded with an impedance ZL . Let the internal generator impedance be ZS .
ZS
ES
1
Quadripole
2
ZL
Input and output impedances
We call input impedance ZI , the equivalent impedance seen from the input terminals when the output terminals are loaded with ZL . Analogously, we call output impedance ZO , the equivalent impedance seen from the output terminals when the input generator is set to zero (ES =0 V, IS =0 A).
II
Quadripole
VI
1
ZL
2
ZI
1
IO
Quadripole
ZS
1
VO
2
ZO
53
The voltage gain is dened as:
AV =
Voltage, current and power gains
The current gain is dened as: The power gain is dened as:
VO VI IO AI = II PO AP = PI
GV = AV |dB = 20 log (|AV |) GI = AI |dB = 20 log (|AI |) GP = AP |dB = 10 log (|AP |)
Pay attention to the denition of GP : it has a 10 instead of a 20 because AP is the square of a gain. When a quadripole has a dierential input, the input generators and their internal impedances can be substituted by two generators producing the same voltages at nodes 1 and 1:
I1
1
IO
2
V1
Dierentialinput single-output linear quadripoles
VI
1
I1
Quadripole
VO
2
V2
Figure N1.1 When the quadripole is linear, by means of the superposition principle we can write: VO = A1 V1 + A2 V2 However this writing does not emphasize on the VO dependence on the real input voltage, i.e. the dierence V1 V1 , therefore other notations are introduced in the following sections. A dierential input can be seen as the weighed sum of two dierent voltages called dierential mode voltage and common mode voltage dened as: VDM = V1 V1 VCM = (V1 + V1 ) /2 VDM + VCM 2 With these denitions we can write (see Fig. N1.1):
Common mode and dierential mode voltages
(N1.4) V1 =
VDM + VCM 2
V1 =
VID /2 VICM VID -VID /2

Quadripole
VO = (A1 A2 )
VDM + (A1 + A2 ) VCM 2
(N1.5)
To simplify the above VO notation we dene:
Common mode and dierential mode gains
Dierential mode gain: Common mode gain: Therefore

(N1.5)
ADM = ACM
A1 A2 2 = A1 + A2
VO = ADM VDM + ACM VCM
(N1.6)
54
Commonmode rejection ratio
The common-mode rejection ratio (CMRR) of a dierential-input single-output quadripole is the ability of the quadripole to reject input signals common to both input terminals. A high CMRR is important in applications where the signal of interest is represented by a small voltage uctuation superimposed on a voltage oset, or when the signal of interest is in the dierence between inputs [?], [?]. (N1.7) CM RR = ADM ACM
A high CMRR means that the dierential mode gain is greater than the common mode gain. Assuming that the quadripole is loaded with the impedance ZL
VID /2 VICM VID -VID /2

Quadripole
VO
ZL
Dierential mode and common mode input impedance
the dierential mode input impedance is dened as VDM IDM

IID
RIDM =
VID
Quadripole
ZL
and the common mode input impedance is dened as

IICM
RICM
VCM = ICM
Quadripole
ZL
VICM
55
A unidirectional linear amplier is a linear quadripole working in only one direction, from input to output terminals. In other words, this means that a change in the input electrical variables produces a change in the output electrical variables, whereas a change in the output electrical variables does not produce any changes in the input electrical variables:
(N1.1)
VI VO
Z11 Z21
0 Z22
II IO
VI = Z11 II VO = Z21 II + Z22 IO
(N1.8)
Unidirectional Linear Amplier
From input terminals, a unidirectional linear amplier is simply seen as the impedance Z11 . From output terminals, it can be modeled with Thevenin or Norton theorems. Accordingly, there are four possible combinations: Signal source generator
voltage
ZO II
current
ZO
Output equivalent current voltage
ZI
VI
A _ VI
ZI
Z _ II
II
ZI
VI
Y _ VI
ZO
ZI
A _ II
ZO
ZO
ZI
VI
A _ VI
Voltage amplier

(N1.8),Fig. N1.2 (N1.2),(N1.3)
Figure N1.2 VI VO = Z11 , ZO = II IO VO VI Z21 Z11
ZI =
= Z22 , A =
II =0
=
IO =0
(N1.9)
(N1.9)
VI VO
ZI A ZI
0 ZO
II IO
(N1.10)
56
II
ZO
ZI
Z _ II
Transimpedance amplier (current-tovoltage converter)
Figure N1.3 VO VI = Z11 , ZO = II IO VO II

(N1.8),Fig. N1.3
(N1.2),(N1.3)
ZI =
= Z22 , Z =
II =0
= Z21
IO =0
(N1.11)
(N1.11)
VI VO
ZI Z
0 ZO
II IO
(N1.12)
ZI
VI
Y _ VI
ZO
Transconductance amplier (voltage-tocurrent converter)
Figure N1.4 VO VI = Z11 , ZO = II IO IO VI Z21 Z22 Z11

(N1.8),Fig. N1.4
(N1.2),(N1.3)
ZI =
= Z22 , Y =
II =0
VO =0
(N1.13)
(N1.13)
VI VO
ZI Y ZI ZO
0 ZO
II IO
(N1.14)
57
II
ZI
A _ II
ZO
Current amplier

(N1.8),Fig. N1.5 (N1.2),(N1.3)
Figure N1.5 VO VI = Z11 , ZO = II IO IO II Z21 Z22
ZI =
= Z22 , A =
II =0
VO =0
(N1.15)
(N1.15)
VI VO
ZI A ZO
0 ZO
II IO
(N1.16)
Given the Thevenin equivalent of an input source with VS and ZS , how do we deliver maximum voltage to the input impedance?
ZS
Maximum voltage transfer to the input impedance
VS ZI VI ZL
Figure N1.6 ZI VS ZI + ZS
(N1.17)
VI =
VI VS
max (VI ) = VS when |ZI | |ZS |
Given the Norton equivalent of an input source with IS and ZS , how do we deliver maximum current to the input impedance?
II
Maximum current transfer to the input impedance
IS ZS ZI ZL
Figure N1.7 ZS IS ZI + ZS
(N1.18)
II =
II IS
max (II ) = IS when |ZI | |ZS |
58
Given the Thevenin equivalent of the amplier output with VT and ZT , how do we deliver maximum voltage to the load ZL ?
II VT ZT
Maximum voltage transfer to the load
VI
VO
ZL
Figure N1.8 ZL VT ZL + ZT
(N1.19)
VO =
VO VT
max (VO ) = VT when |ZL | |ZT |
Given the Norton equivalent of the amplier output with IN and ZN , how do we deliver maximum current to the load ZL ?
II IN ZN ZL IO
Maximum current transfer to the load
VI
Figure N1.9 ZN IN ZN + ZL
(N1.20)
IO =
IO IN
max (IO ) = IN when |ZL | |ZN |
59
Given the Thevenin equivalent of an input source with VS and ZS and the Thevenin equivalent of the amplier output with VT = A VI and ZT = ZO (i.e., a voltage amplier), how do we deliver maximum voltage from the input to the load ZL ?
ZS VS ZI VI ZO
A _ VI
VO
ZL
Maximum voltage transfer from the input to the load

(N1.19) (N1.17)
Figure N1.10 |ZI | |ZS | and |ZO | |ZL | (N1.21)

(N1.17),(N1.19)
(N1.21)
AV =
VO ZI A ZL = A VS ZI + ZS ZL + ZO
1 A
(N1.22)
Given the Norton equivalent of an input source with IS and ZS and the Norton equivalent of the amplier output with IN = A II and ZN = ZO (i.e., a current amplier), how do we deliver maximum current from the input to the load ZL ?
II IS ZS ZI A _ II ZO ZL IO
Maximum current transfer from the input to the load

(N1.20) (N1.18)
Figure N1.11 |ZI | |ZS | and |ZO | |ZL | (N1.23)

(N1.18),(N1.20)
(N1.23)
AI =
A ZO IO ZS A = IS ZS + ZI ZO + ZL
1 A
(N1.24)
60
The Miller theorem

Consider the generic circuit in Fig. N1.12 and let be Z the equivalent impedance seen between nodes A and B. When the circuit is bidirectional, it is always possible to split Z into two impedances ZA and ZB connected between nodes A and B, respectively. The obtained circuit (Fig. N1.13) is equivalent to the original circuit if and only if Z =Z A 1 1k Z =Z k B k1
The Miller theorem
Figure N1.12 k= VB VA
ZA A B ZB
(N1.25)
being k is called the Miller factor is equal to the voltage gain between nodes B and A. NOTE: If the circuit is not bidirectional (VB /VA = VA /VB ) it is possible to use the Miller theorem but it is valid only in one direction.
Figure N1.13
Circuits in Fig. N1.14 are electrically equivalent only if there are no changes in the electrical variables. In others words they are equivalent if node voltages VA and VB are unchanged, and if the current owing out of the node A is the same of that owing in of the node B and if both are equal to the current owing in of impedance Z.
Z
IA
IB
IAB
A B ZA A B ZB
Miller theorem demonstration
For the circuits equivalence we must have IAB = IA and IAB = IB , thus 1k 1 VA 1 VA VB ZA = Z = = Z ZA Z ZA 1k (N1.26) V V A 1/k 1 k VB 1 B ZB = Z = = Z ZB Z ZB k1
Figure N1.14 k = VB VA VA VB 1k 1/k 1 (N1.26) I = = VA = VB AB Z Z Z IA = VA = IB = VB ZA ZB
61
1 , equations (N1.25) simplify When Z is the impedance of a capacitor C, i.e. Z = sC to ZA = 1 1 = sC (1 k) sCA 1 k Z = B = sC (k 1) sCB
Miller eect for capacitors
(N1.27)
this means that the capacitor C can be split into two capacitors with capacitances CA = C (1 k) and CB = C (1 1/k). When k < 0, CA and CB are greater than C and for high values of |k| we have CB C. The eective increment of CA is usually referred to as Miller eect.
Part A2
Single stage MOSFET and BJT congurations
MOSFET single stage ampliers

VDD
iD = ID + id ID depends on VDD and on VSS id depends on vi
RD
Common source (CS)

(T6.7)
(T6.3)
Rg
D B S
vo
vi RS
-VSS
Figure A2.1
63
ID can be calculated when vi = 0

VDD
RD ID
Hp: MOSFET in saturation region

D S
CS: biasing
Rg
IG
RS
-VSS
VGS = VSS ID RS VDD = (RD + RS ) ID + VDS VSS k ID = n (VGS VTn )2 (1 + VDS ) 2 0.1 (1 + VDS ) 1
(A2.1)
Figure A2.2 ANALYSIS PROBLEM Given: RD , RS , Rg VDD , VSS kn , VTn

(A2.1)
DESIGN PROBLEM Given: Rg , ID VGS , VDS kn , VTn

(A2.1)
Find: ID , VGS , VDS
Find: RS , RD , VDD , VSS
3 equations and 3 unknown variables: solve the system, verify the validity of the saturation region hypothesis.
3 equations and 4 unknown variables: 1 more constraint is issued or 1 more variable is specied. Solve the system, verify the validity of the saturation region hypothesis.
Consider the generic multivariable function G(x, y, z, . . .), the sensitivity of G with respect to variations of x (x) is dened as
x (A2.2) SG =
x G G x
Sensitivity (denition)
where x/G is a normalizing factor (the sensitivity is dimensionless) and G/x is the ratio between the variation on G caused by the variation of x and the variation of x itself. When x is suciently small then the sensitivity can be approximated with
(A2.3)
x SG =
x G G x
64
Concerning the DESIGN PROBLEM a constraint can be issued by setting the maximum sensibility of ID when VTn can vary from its nominal value. iD VSS /RS A = {IDA , VGS A } B = {IDB , VGS B } C = {IDC = ID , VGS C = VGS } VSS vGS

Fig. T6.2
(T4.8)
A ID C B VTmin VTnVTmax Figure A2.3
CS: The design problem
T SID n =
(A2.3)
ID VTn ID VTn hence
(A2.1)
(VGS VTn ) ID = kn (VGS VTn ) (1 + VDS ) VTn VTn ID (VSS ID RS VTn ) 2ID 2ID 0 = = RS 1 VGS VTn VTn VGS VTn VTn 2ID 2VTn VT = SID n = 2ID RS + VGS VTn 2ID RS + VGS VTn 1 VTn 1 VGS VTn . p ID 2 ID
VTn ID ID VTn
T SID n p RS
But VGS > VTn and VDS > VGS VTn when the MOSFET is in saturation region, therefore RS < therefore 1 VTn 1 VGS VTn RS < min p ID 2 ID VSS VTn VDD + VSS VGS + VTn , RD ID ID
(A2.1)
VSS VTn ID
and RS <
VDD + VSS VGS + VTn RD ID
1 id is evaluated when VDD = VSS = 0 and, as discussed above, if vgs (VGS VTn ) 5 MOFSET equations for saturation region can be linearized by means of the Taylor approximation. .
CS: Small-signal (LPA) equivalent circuit
Rg
MOSFET equivalent circuit

G D
gm vgs
1 g0
gmb vbs
vi
S
RD
RS
65
By applying Norton theorem
Rg
DB
ieq gmb vbs
gm vgs
1 g0
CS: Norton equivalent circuit
vg = v i
S
RS
BD
vds=vbs 1 gmb
ieq = gm vgs + vds (g0 + gmb ) vgs = vi ieq RS vds = ieq RS ieq = gm (vi ieq RS ) ieq RS (g0 + gmb ) ieq [1 + RS (gm + gmb + g0 )] = gm vi gm vi 1 + (gm + gmb + g0 ) RS
(A2.4)
ieq =
66
vbs = vgs
gout =
ix 1 g0 gmb vbs
ix vx
S
gm vgs
ix = (gm + gmb ) vgs + g0 vds vx = vds + ix RS vgs = vsg = ix RS

BG
gm
vx
RS
CS: equivalent conductance
gout
= gm + gmb
gm ix RS + g0 vx g0 ix RS vx (gm + g0 ) ix RS + g0 vx = vx
gout = gout
gout = (gm + g0 ) gout RS + g0 gout [1 + (gm + g0 ) RS ] = g0 gout =
g0 1 + (gm + gmb + g0 ) RS
ieq
1 gout
RD
vo
ieq
1 gout
vo
(A2.5)
gout = gout +
1 g0 = + GD RD 1 + (gm + gmb + g0 ) RS gm vi 1 + (gm + gmb + g0 ) RS g0 + GD 1 + (gm + gmb + g0 ) RS
ieq vo = = gout (A2.5)

(A2.4)
CS: voltage amplication

(A2.6)
gm vo = vi g0 + GD + (gm + gmb + g0 ) RS GD
CS: simplifying hypotheses
RS RS g0
= 0 = 0 = 0
vbs = 0 gout = g0 + GD vbs = 0 gout = GD

(A2.6)
(A2.6)
vo gm = vi g0 + GD vo = gm RD vi
(A2.7) (A2.8)
67

(A2.8) (A2.1)
(T6.2)
VDD + VSS = RD ID + VDS
vo 2ID = gm RD = RD vi VGS VTn
CS: estimation of the maximum voltage amplication
Under the hypothesis of balanced output swing (i.e., the output signal has the same up and down voltage excursion range) RD ID = VDS = VDD + VSS 2 VDD + VSS VDD + VSS VGS VTn
=2 1
(A2.9)
|gm RD | =
It was chosen VGS = 2 because this value makes (A2.9) maximum and gives a safe MOSFET bias point.
VDD
Rg
D B S
-VSS
Common drain (CD)
vi RS vo
-VSS
Figure A2.4
CD: biasing
(A2.1)
Same as CS
68
Rs
CD: small-signal equivalent circuit
gm vgs vi
1 g0
gmb vbs
RS
BD
1 gmb
CD: short-circuit id = ieq
(A2.10)
ieq = gm vi
ix 1 g0 vx
CD: output equivalent conductance
g0 = g0 + gmb
1 gm
(A2.11)
gout =
1 ix = = gm + g0 rout vx
GBD
gout
69
io 1 gout
gmvi
RS
vo
CD: voltage amplication
vo = gm vi req rout RS = = rout + RS 1 RS RS gout = 1 1 + gout RS + RS
req = RS / out /r
gout
(A2.12)
vo gm RS = gm req = vi 1 + gout RS gout gm gm RS vo vi 1 + gm RS io = vo gm vi RS 1 + gout RS
g0 + gmb gm
VDD
RD
Common gate (CG)
D B S
-VSS
vo
RS
is
-VSS
CG: biasing
(A2.1)
Same as CS
70
id 1 g0
gm vgs
CG: small-signal equivalent circuit
RD
gm = gm + gmb
RS is
GB

ieq = gm vgs + g0 vds
vds = vgs
CG: short-circuit id = ieq
ieq = (gm + g0 ) vgs
gm vgs
1 g0
ieq
vsg = (is + ieq ) RS vgs = vsg

ieq [1 + (gm + g0 ) RS ] = (gm + g0 ) RS is
ieq
S
is
RS
(A2.13)
ieq =
(gm + g0 ) RS is 1 + (gm + g0 ) RS
GB
71
gout = ix =
ix vx + g0 vds
ix
gm vgs
1 g0
ix vx
gm vgs
vx = vds + ix RS
CG: output equivalent conductance
vsg = vgs = ix RS
RS gout
GB
gout =
gm ix RS + g0 (vx ix RS ) vx
gout = gm RS gout g0 RS gout + g0
(A2.14)
gout =
1 rout
1+
(gm
g0 + g0 ) RS
io 1 gout
ieq
RD
CG: current amplication
GB
io rout 1 1 + (gm + g0 ) RS = = = ieq RD + rout 1 + gout RD 1 + (gm + g0 ) RS + g0 RD io io ieq (gm + g0 ) RS = = + g )R + g R is ieq is 1 + (gm 0 S 0 D
(A2.13)
(A2.15)
72
gin
ix = vx
id 1 g0
gm vgs
vx = (id + ix ) RS
id = gm vgs + g0 vds
RD
vo
ix
S
vds = vo vx vo = id RD vgs = vx
vx
RS
GB
CG: input conductance
gin
id =
gm vx
+ g0 (idRD vx )
id (1 + g0 RD ) = (gm + g0 ) vx
id =
gm + g0 vx 1 + g0 RD g + g0 vx + ix RS vx = m 1 + g0 RD g + g0 RS = ix RS vx 1 + m 1 + g0 RD gm + g0 RS 1 + g0 RD
(A2.16)
gin =
ix = vx
1+
1 1 + 2g0 RD + (gm + gmb ) RS = RS (1 + g0 RD ) RS
vs =
is gin
CG: voltage amplication
vo = RD io io RD io vo = = gin RD vs is /gin is
(A2.15)
(A2.17)
Simplifying hypotheses: CGS and CGD are negligible (central-band hypothesis) rin gout g0 + GD (A2.5) (A2.11) (A2.14)
(A2.5) (A2.6) (A2.5)
MOSFET congurations summary
CS (RS =0, VBS =0) CS (RS =0) CD CG

(A2.15) (A2.12) (A2.14) (A2.6) (A2.11)
(A2.16)
vo /vs gm gout (A2.6) (A2.12) (A2.17)
io /is (A2.15)
73
Simplifying hypotheses: g0 = 0, CGS and CGD are negligible rin CS (RS =0, VBS =0)
(A2.6) (A2.5) (A2.6) (A2.5)
gout GD GD gm + gmb + GD 1 RS
vo /vs gm RD (A2.6) (A2.12)

gm RD
io /is
gm RS 1 + gm RS
RS 1 + gm RS
CS (RS =0) CD
(A2.12) (A2.14) (A2.15) (A2.11)
CG
BJT single stage ampliers

VCC
RC
Common emitter (CE)
iC = IC + ic
iB = IB + ib
iC Rg iB B iE RE
C
IC and IB depend on VCC and VEE ic and ib depend on vi

vi
vo
E
-VEE
Figure A2.5
VCC
Hp: BJT in FAR

RC
CE: Biasing
VEE = IB Rg + VBE + IE RE VCC + VEE = RC IC + RE IE + VCE IC = IB F IE = IC + IB (A2.18) VCE VA 1 + VCE 1 VA VBE 0.7 V (see note )
IC IB
B C
IE Rg RE
VBE is considered approximately 0.7 V to avoid the exponential equation in the system resolution.
-VEE
Figure A2.6
74
ANALYSIS PROBLEM Given: RC , RE , Rg VCC , VEE F

(A2.18)
DESIGN PROBLEM Given: Rg , IC VBE , VCE F

(A2.18)
Find: IC , IB , IE , VCE , VBE
Find: RC , RE , IB , IE , VCC , VEE
5 equations and 5 unknown variables: solve the system, verify the validity of the SAR region hypothesis.
5 equations and 6 unknown variables: 1 more constraint is issued or 1 more variable is specied. Solve the system, verify the validity of the SAR region hypothesis.
Concerning the DESIGN PROBLEM a constraint can be issued by xing the maximum variation iC when the temperature varies (i.e., VT changes). iC T2 VEE RE T0 T1 A iC C B IC IB IE IC
T1 < T0 < T2 A = {ICA , VBEA } B = {ICB , VBEB } Hp: Rg < RE
CE: The design problem
0.68 0.7 0.72

(expanded axis)
(A2.18)
VEE
vBE [V]
VEE =
IC Rg + VBE + IC RE F
VEE = VBE + IC RE iC = VBEB VBEA = ICA ICB = IC RE
75
Rg
gm vbe r vi
E
r0 RC
vo
CE: Small-signal circuit
RE
Figure A2.7 The small-signal circuit is similar to that seen for the MOSFET common source conguration, thus to nd the voltage amplication we can follow the same procedure ( pag. 64). Accordingly, for r0 = we have vo gm r RC F RC = = vi Rg + r + (1 + gm r ) RE Rg + r + (1 + F ) RE
Part E1
Esempio di progettazione di un amplicatore CS
Dato lamplicatore in gura
VDD
rout R1 rin Rg CI M1 RL vi vo RD CO
Speciche di progetto
R2
RS
CS
-VSS
Figure E1.1 Si progetti il circuito in maniera da soddisfare le seguenti speciche: Guadagno di tensione: AV = 2 Resistenza di ingresso di piccolo segnale: rin 100 k Resistenza di uscita di piccolo segnale: rout = 10 k Potenza dissipata in polarizzazione: P 10 mW
77
Tensione di alimentazione: VDD = VSS = 5 V Resistenza di carico: RL = 10 k
Dati
Resistenza di sorgente: Rg = 50 Condensatori di disaccoppiamento: CI = CO = CS = 1 F Frequenza operativa del segnale di ingresso vi : fi = 10 kHz Parametri del MOSFET-n: VTn = 1 V kn = 150 A/V
2
= 0.01 V1
Analisi preliminare del circuito
Prima di procedere bisogna capire in quale congurazione a singolo transistore si trova il MOSFET-n M1 . Per fare questo ` utile identicare i terminali di uscita e di ingresso. Come ` possibile e e vedere in Fig. E1.1 il segnale vi ` applicato al gate di M1 attraverso la resistena Rg e e il condensatore di disaccoppiamento CI , dunque il terminale di ingresso ` il GATE. e Inoltre il segnale di uscita viene prelevato dal DRAIN attraverso il condensatore di disaccoppiamento CO . In denitiva M1 ` in congurazione common source ( pag. 62) e, considerata e la presenza della resistenza di source RS e del condensatore CS , ` in una conge urazione common source con resistenza di source e condensatore di disaccoppiamento.
VDD
Circuito equivalente per lo studio della polarizzazione
In polarizzazione (cio` a frequenza nulla) i condensatori e di disaccoppiamento sono dei circuiti aperti quindi il circuito equivalente per lo studio della polarizzazione ` e quello riportato in Fig. E1.2. La tensione al nodo di gate VG ` ottenibile con il e partitore resistivo tra VDD e VSS ed ` data da e VG = R2 (VDD + VSS ) VSS R1 + R2
R1
RD
M1
La tensione al nodo di source VS ` e

R2 RS
VS = ID RS VSS dove con ID si ` intesa la corrente di drain (source) di e M1 . Inne la tensione al nodo di drain VD ` e VD = VDD ID RD Figure E1.2
-VSS
78
Dunque
(E1.1)
V DS (E1.2) ID =
VGS = VG VS =
R2 (VDD + VSS ) ID RS R1 + R2 = VD VS = VDD + VSS (RD + RS ) ID
kn 2 (VGS VTn ) (1 + VDS ) 2
Dal momento che si desidera che M1 lavori in zona di saturazione ( essere soddisfatte le condizioni: (E1.3) VGS > VTn VDS VGS VTn
pag. 34) devono
Oltre a ID che scorre in M1 i genereatori di polarizzazione erogano la corrente I12 che scorre nelle resistenze R1 , R2 data da:
Corrente erogata dai generatori di polarizzazione
I12 =
VDD + VSS R1 + R2
Quindi la corrente IT erogata dai generatori ` e (E1.4) IT = ID + VDD + VSS R1 + R2
Circuito equivalente di piccolo segnale
Il circuito equivalente di piccolo segnale ` ottenuto dalla linearizzazione attorno al e punto di polarizzazione del circuito in Fig. E1.1, quindi bisognerebbe conoscere il punto di lavoro di M1 per poter essere sicuri che si trovi in zona di saturazione. A questo punto del progetto, per`, non abbiamo questa informazione e lunica alternao tiva possibile ` ipotizzare che M1 si trovi in zona di saturazione. Supponiamo inoltre e che la frequenza operativa fi del segnale di ingresso sia tale da ritenere i condensatori di disaccoppiamento dei corto circuiti, mentre quelli parassiti dei circuiti aperti (ipotesi di centro banda). Sotto tali ipotesi che andranno vericate nel seguito il circuito per piccolo segnale ` il seguente e
rin Rg rout
gm vgs vi R1= 2 =R
1 g0
gmb vbs RD RL vo
SB
Figure E1.3
79
Lispezione visiva di tale gura ci suggerisce alcune semplicazioni: dato che i terminali di source e di body sono cortocircuitati tra loro si ha vbs = 0 e quindi il generatore pilotato gmb vbs eroga corrente nulla: questo signica che tale generatore ` lequivalente di un circuito aperto e dunque pu` essere eliminato dal circuito. e o Inoltre (E1.5) rin = R1 / 2 /R
e come ` facilmente ricavabile da (A2.5) e (E1.6) rout = 1/g0 / D = r0 / D /R /R
A seguito di tali considerazioni il circuito per piccolo segnale diviene

Rg
gm vgs vi rin rout RL vo
SB
Figure E1.4
Riferendosi a Fig. E1.4 si ha vgs = rin vi rin + Rg
Guadagno di tensione
vo = rout / L gm vgs = gm rout / L /R /R (E1.7) AV =
rin vi rin + Rg
vo rin = gm rout / L /R vi rin + Rg
Le informazioni ricavate nora sono utili a convertire le speciche in equazioni da risolvere. Per adesso concentriamoci sulle speciche riguardanti AV , rin e rout . In particolare da (E1.6), dalla denizione di g0 ( pag. 46) e dalle speciche di progetto si ha rout = r0 / D = 10 k /R
Conversione delle speciche
solitamente r0 RD quindi ipotizzando che valga tale relazione (va vericato in seguito) la rout diviene (E1.8) rout RD = 10 k
e sotto tali condizioni si ha (E1.9) rout / L RD / L RL /2 = 5 k /R /R
80
Per le speciche rin = R1 / 2 deve essere maggiore di 100 k. Imponendo arbitrari/R amente R1 = R2 la specica viene tradotta in rin = R1 /2 e quindi (E1.10) R1 200 k
Sotto le condizioni (E1.8), (E1.9) e (E1.10), la (E1.7) si semplica in AV gm RL /2 essendo rin Rg . Dunque la specica sul guadagno impone 2ID gm RL /2 = 2 gm = = 0.4 mS VGS VTn = 5000ID VGS VTn che sostituita nella (E1.2) d` a (E1.11) ID = 1 A 1 533 A 1875 (1 + VDS ) 1875
dove ` stata utilizzata lapprossimazione VDS 1, sempre vera considerato che e = 0.01 V1 e che VDS VDD + VSS = 10 V. Inoltre (E1.12) VGS VTn = 5000ID 2.67 V VGS 3.67 V
Conoscendo la corrente di drain (source) si pu` vericare la condizione r0 RD o usata in precedenza ( pag. 46) r0 = 1 1 + VDS 188 k RD ID ID
cos` confermando che lipotesi fatta ` corretta. e Utilizzando la specica sulla potenza massima e tramite la (E1.4) si pu` trovare un o valore opportuno per R1 = R2 PT = ID (VDD + VSS ) + (VDD + VSS ) 2R1
2
10 mW
R1 21.4 k
in altri termini se si rispetta la (E1.10) si rispetta anche questultima condizione. Fissiamo pertanto arbitrariamente (E1.13) R1 = 200 k
Dalle equazioni (E1.3), (E1.12), (E1.13) e i dai dati del progetto si possono soddisfare le condizioni di polarazzazione di M1 in (E1.1) (E1.14) 3.67 = 5 533 106 RS VDS = 10 533 106 (RD + RS ) RS 2495 RD 11257
quindi la (E1.8) garantisce la zona di saturazione del transistor perch soddisfa e questultima condizione. Lunica ipotesi non ancora vericata ` quella di centro banda fatta per ricavare il e circuito per piccolo segnale. Secondo la teoria ( pag. 48) si deve vericare che alla frequenza operativa le reattanze capacitive di CI , CO e CS siano tali da poter essere trascurate rispetto alle resistenze viste ai loro capi. Essendo CI = CO = CS = 1 F si ha XC I = XC O = XC S = 1 15.92 2 10 103 1 106
Verica di centro banda
81
e CI ` in serie con la resistenza Rg +rin 100 k 15.92 , quindi XCI ` sicuramente e trascurabile. e CO ` in serie con la resistenza RL +rout 20 k 15.92 , quindi XCO ` sicuramente e trascurabile. CS ` in parallelo con la resistenza RS e quella data da (A2.11) dunque e 1 1 e / S/ /R / 1241 15.92 , quindi XCS ` sicuramente trascurabile. gm g0 In conclusione anche lipotesi di centro banda ` vericata. e Riassumento si ha Polarizzazione:
Sommario
R1 = R2 = 200 k VGS = 3.67 V > VTn VDS = 3.34 V > VGS VTn IR1 ,R2 = 25 A
RS = 2495 ID = 533 A VS = 3.67 V PT = 5.6 mW
RD = 10 k VG = 0 V VD = 330 mV
Piccolo segnale: rin = 100 k rout = 9.49 k AV = 1.85
A causa delle approssimazioni fatte i valori reali sono leggermente diversi dai precedenti, ma non cos` diversi da giusticare una progettazione eseguita senza approssimazioni (in polarizzazione si dovrebbe risolvere un sistema di 3 equazioni in 3 incognite, inoltre una delle equazioni ` di terzo grado) e Polarizzazione non approssimata: VGS = 3.647 V > VTn VDS = 3.223 V > VGS VTn IR1 ,R2 = 25 A ID = 542.36 A VS = 3.647 V PT = 5.7 mW VG = 0 V VD = 423.58 mV
Piccolo segnale non approssimato: rin = 100 k rout = 9.5 k AV = 1.996
Part A3
Basic MOSFET-based congurations
Diodeconnected MOSFET connection
MOSFET-n iDS iDS D G SB
MOSFET-p
GD ROUT
iSD G
SB
D
iSD
SB
ROUT GD
SB
|iDS |
vx
ix
DG
gm vgs
1 g0
SB
VTn
|vGS | = |vDS | vx 1 = ix gm + g0
(A3.1)
ROUT =
kn1 = kn2
VDD
VDD req iIN R1
VTn1 = VTn2 1 = 2
Current mirror
W L iD1 iD2
=
1
W L
2 2
kn = 1 vGS VTn1 2 kn2 = vGS VTn2 2
(1 + 1 vGS ) (1 + 2 vDS 2 )
M1
M2
83
(A3.2)
iD1 = iD2
W L W L
(1 + 1 vGS )
1
(1 + 2 vDS 2 )
2
Small-signal circuit for req evaluation
(A3.1)
D1G1G2 1 g01 vgs S1S2
D2 gm vgs 1 g02 req
req =
(A2.5)
1 = r02 g02
VDD
Current mirrors
MS
iIN
n1iIN
n2iIN
nmiIN
M1
M2
Mm
Hp: M1 and M2 in saturation region and perfectly matched =0
VDD
Dierential amplier (DA): large dierential signal
2iD1 kn 2 + VTn (VGS1 VTn ) VGS1 = iD1 = 2 kn ISS = iD1 + iD2 vd = vi1 vi2 = VGS1 VGS2 vi1 2iD1 2iD2 vd = kn kn 4 2 2 iD1 iD2 (iD1 + iD2 ) vd = kn kn 2 2 kn vd kn vd = ISS 2 iD1 iD2 2 iD1 iD2 = ISS 2 2
2 kn vd 2
RD iD1 v O1 M1 VS ISS RS v O2 M2
RD iD2 vi2
-VSS
4iD1 iD2 =
ISS
(iD1 + iD2 ) (iD1 iD2 ) =
ISS
kn 2 v 2 d
84
2 2 ISS (iD1 iD2 ) = ISS 1 2 (iD1 iD2 ) = ISS 2 (iD1 iD2 ) = ISS 2 2
kn 2 v 2ISS d kn 2 2 v ISS 1 2ISS d kn 2 v 1 1 2ISS d

2 2 4 kn vd kn vd 2 + I 4ISS SS 2 kn vd 4ISS
iD1 iD2 = ISS
11
iD1 iD2 = vd ISS
kn ISS
(A3.3)
gm1,2
iD1 iD2 vd ISS

2 kn vd 1 4ISS
kn ISS
2 vd
if 4ISS kn
2 kn vd 1 4ISS
vd 2
ISS kn
an increase in ISS leads to an increase in vd but also to a greater power dissipation being PD = (VDD + VSS ) ISS . ISS = 2ID1 = 2ID2 vd 2 ISS kn vd 2 2ID1 = 2 (VGS1 VTn ) kn
thus vd 0.2 (VGS1 VTn ) iD1 iD2 i +i D1 D2

2 kn vd 4ISS
(A3.3)
= gm1,2 vd = ISS 1 1
2 kn vd 4ISS
iD1 ISS + iD1 = gm1,2 vd
2 kn vd 4ISS
iD1 iD2
DA: = f1 (vd) = f2 (vd)
iD1 =
ISS vd + gm1,2 2 2
2 kn vd 4ISS
(A3.4)
iD2 + ISS iD2 = gm1,2 vd ISS vd gm1,2 2 2
2 kn vd 4ISS
iD2 =
2 kn vd 4ISS
(A3.5)
iD1 = ISS ?
(A3.4)
vd ISS = gm1,2 2 2 kn vd ISS 1 1

2 kn vd 4ISS
2 kn vd 4ISS
ISS = ISS 1 = vd kn ISS
2 kn vd 4ISS

2 kn vd kn 1 2 4 2 2 2 1 kn vd 4kn vd ISS + 4ISS = kn vd 2ISS 2 = I vd 4ISS SS ISS vd = 2 = 2 (VGS VTn ) kn
85
=0
iD1 = 0?
(A3.4)
vd ISS = gm1,2 2 2 kn vd ISS 1
2 kn vd 4ISS
ISS = ISS
2 kn vd 4ISS
2 1 kn kn vd = 1 vd ISS 4ISS 2 1 kn vd kn 2 4 2 2 2 1 kn vd 4kn vd ISS + 4ISS = kn vd 2ISS 2 = I vd 4ISS SS ISS = 2 (VGS VTn ) vd = 2 kn
=0
iD1
iD2 ISS
DA: plots of iD1 and iD2

2 VGS VT n
ISS 2 vd
2 VGS VT n
Figure A3.1
vO1 = VDD RD iD1

vO1
vO2 = VDD RD iD2

vO2 VDD
DA: plots of vO1 and vO2

2 VGS VT n
VDD RD vd
ISS 2
2 VGS VT n
Figure A3.2 around vd = 0 we have vO2 > 0 (non-inverting stage) vd vO1 < 0 (inverting stage) vd
86
DA: verication of the saturation region for M1 and M2
vDS1 vGS1 VTn
vDG1 VTn
vGD1 VTn
vGD1,M AX = vG1,M AX vD1,M IN = vG1,M AX (VDD RD ISS ) VTn vG1,M AX VDD + VTn RD ISS this limits the amplitude of the input signal (vd 0.2 (VGS1 VTn )). Note that when RD ISS VTn , vG1,M AX can be as high as VDD . vO1 = VDD RD vO1 ISS vd + gm1,2 2 2 ISS vd = VDD RD gm1,2 RD = VO1 vo1 2 2
biasing small signal
DA: evaluation of vO1
thus vo1 1 = gm1,2 RD vd 2 ISS VO1 = VDD RD 2
VDD vi1=vi2=0 RD iD1 v O1 M1 VS ISS RS v O2 M2 RD iD2 vi2 RD
VDD
VDD
RD VO1 M1 VO2 M2 VS ISS/2 2RS ID2
ID1
DA: biasing equivalent circuit
vi1
VS ISS/2 2RS
-VSS
-VSS
-VSS
1
Figure A3.3
Considering only half circuit VDD = RD ID1 + VDS1 + 2RS ID1 VSS = (RD + 2RS )
(A2.1)
ISS + VDS1 VSS 2
DA: biasing
VG1 = 0 VD1 = VO1 = VDD RD ID1 = VDD RD VS1 = VSS + 2RS ID1 = VSS + RS ISS ISS 2
87
DA: small signal
From Fig. A3.3, the small-signal equivalent circuit is obtained setting VDD = VSS = 0 and according to (N1.4) we can consider input signal as the superposition of two dierent signals: the common-mode signal vicm and the dierential-mode signal vd vi1 = vicm + vd 2 vi2 = vicm vd 2
RD id1 vo 1
DA: commonmode small signal
When vd = 0 we have vi1 = vicm = vi2 and thus the circuit is perfectly symmetric. In this case we can analyze only half circuit.
vicm
M1
2RS
Figure A3.4

G D
(A3.4)
gm1,2vgs1 vicm
1 g01
gmb1vbs1 RD
vo 1
2RS
g01 = 0
(A2.8)
vo1 = vo |vd =0
gm1,2 RD vo1 = vicm 1 + 2 gm1,2 + gmb1 RS
(A3.6)
88
When vicm = 0 ISS = iD1 + iD2 = ID1 + id + ID2 id VS = RS ISS VSS = constant i.e. there are no small-signal variations on the source node and VS is zero from a small-signal point of view. Accordingly, the small-signal equivalent circuit for the dierential-mode analysis can be obtained from Fig. A3.3 simply considering half circuit and VS = 0.
vd 2 RD id1 M1 vo 1
(N1.5)
DA: dierentialmode small signal
2RS
Figure A3.5

G D
(A3.4)
vd 2
gm1,2vgs1
1 g01
RD
vo1
SB
RS = 0
(A2.8) vo1 gm RD = 1,2 vd 2
g01 = 0 (A3.7)
vo1 = vo |vicm =0
(A3.8)
gm1,2 =
2ID1 = VGS1 VTn
2ID1 = 2ID1 /kn
2ID1 kn =
ISS kn
DA: complete vo1

(A3.7)
(A3.6)
vo1 = vo1 + vo1 =
gm1,2 RD vd vicm gm1,2 RD 1 + 2gm1,2 RS 2
(A3.9)
89
(N1.7)
CMRR =
ADM = ACM
DA: CMRR
1 + 2gm1,2 RS gm1,2 RD = gm1,2 RD 2 2 1 + 2gm1,2 RS
(A3.10)
A higher CMRR cannot be obtained with a higher RS because, given VDD and VSS , a higher RS leads to a smaller biasing current ID1 thus to a smaller gm1,2 (see (A3.8)) that produces a smaller CMRR. We can have a higher CMRR substituting the resistance RS with a current mirror (i.e., a xed output current and a high output equivalent resistance).
DA: common source conguration with RS = 0
vo = gm RD = Av vi A higher Av cannot be obtained with a higher RD because, given VDD and VSS , a higher RD leads to a smaller biasing current ID thus to a smaller gm (see (A3.8)) that produces a smaller Av . We can have a higher Av substituting the resistance RD with a current mirror, this conguration is called dierential amplier with active load.
(A2.7)
Part T7
Ampliers frequency response
For a linear system with transfer function A (s)
x(t)
A(s)
Figure T7.1
y(t)
we have y(t) = h sin (t + ) when x(t) = k sin (t), in other words the systems response to a sinusoidal signal is still a sinusoidal signal with dierent amplitude and phase, but the same frequency. Since every complex signal can be expressed as a linear combination of sinusoids, the output is also a combination of sinusoids. However, every sinusoid has an amplitude and a phase dierent compared to the input. Parameters h and depend on the input frequency according to relationships
Frequency response (denition)
(T7.1)
h() = k |A (j)|
() = arg [A (j)]
1 kh 0.5 x(t)/k, y(t)/k
0.5
1 0 t 2
91
There are several ways to plot a transfer function. Among these, the so called Bode plot is preferred when a magnitude and phase plots are required. A Bode magnitude plot is a graph of logarithm magnitude as a function of the logarithm of frequency. A Bode phase plot is a graph of the transfer function phase (in degrees) versus the logarithm of frequency. 1 has the following Bode magnitude and Bode For example the function A(s) = 1+s phase plots. 1 Im {A (j)} 20 log |A (j)| = 20 log A (j) = arctan = arctan () , Re {A (j)} w2 + 1
0
Bode plot
20 log |A (j)|
20 slope: 20 dB/decade
40
60 103
102
101
100
101
102
103
(log )
A (j)
30
60
90 103
102
101
100
101
102
103
(log )
Apart from specic circuits, every electronic circuit is a band-pass lter, i.e. a circuit that transmits frequencies within a certain range with an almost constant gain AV 0 and rejects (attenuates) frequencies outside that range. The portion of passed spectrum is called passband, whereas the limiting frequencies are called low-cut frequency fL high-cut frequency fH . fL and fH are the freand quencies in which the gain is 1/ 2 (i.e., -3 dB) of the gain in the passpand (AV 0 ). Frequencies greater than fH and lower than fL are considered high and low frequencies, respectively.
low passband high
Band-pass lter
AV 0
AV 0 2
fL
fH
When fH fL the system is broadband (broad bandwidth), otherwise it is narrowband (narrow bandwidth).
92
Reduction of a third order system to rst order
Let us consider the below transfer function with a passband gain A0 , no nite zeros and three poles p1 , p2 , p3 AH (s) = where a1 = 1 1 1 + + p1 p2 p3 a2 = 1 1 1 + + p1 p2 p1 p3 p2 p3 a3 = 1 p1 p2 p3 A0 A0 = (1 + s/p1 ) (1 + s/p2 ) (1 + s/p3 ) 1 + a 1 s + a 2 s2 + a 3 s3
For simplicity, let us consider p1 < p2 < p3 (it is always possible to organize poles in rising order). When p1 p2 < p3 (dominant pole condition) we can write a1 1 p1 a2 1 p1 p2 a3 = 1 p1 p2 p3 p1 1 a1 p2 a1 a2 p3 a2 . a3
This means that under a dominant pole condition, poles can be simply obtained from the transfer function coecients. Furthermore, being p1 the smallest pole, it is, approximately, the high-cut frequency fH p1 1 = 2 2a1
Given the n-th order transfer function AH (s) = A0 A0 = (1 + s/p1 ) (1 + s/p2 ) (1 + s/pn ) 1 + a1 s + a2 s2 + + an sn p1 p2 < < pn Generalizing the above procedure for the k -th pole, we have (T7.2) pk ak1 ak
the dominant pole approximation can be applied when
Reduction of a n-th order system to rst order
However, we are not interested in nding all poles, we need only p1 , because it represents the high-cut frequency and every circuit works in its passband, and p2 from which it is possible to evaluate how good the dominant pole approximation is. For example, when p2 10 p1 the error on fH is lower than 10%. The higher is the ratio p2 /p1 , the lower is the percentage error on fH . Accordingly, we need only coecient a1 and a2 of the transfer functions.
93
The general form of a systems high frequency response is AH (s) = 1 + b 1 s + b 2 s2 + + b m sm 1 + a1 s + a2 s2 + + an sn
with m n. It was proven that
Time-constant method
n1 0 Ri Ci
(T7.3)
a1 =
i=1
(T7.4)
a2 =
i=1
n j=i+1
0 Ri Ci
i Rj Cj
0 where Ri is the resistance seen by capacitor Ci with all the other capacitors 0 open circuited. The superscript 0 in Ri means that the other capacitors have a 0 1 i = . Rj is the resistance seen capacitance, i.e. an open circuit since lim C0 jC by capacitor Cj with capacitor Ci short circuited and all the other capacitors open circuited.
The time-constant method is valid only for independent capacitors. We say that n capacitors are independent if it is possible to assign the voltage of each one, independently of the voltage of all the others, i.e. parallel or series capacitors are NOT independent. Each independent capacitor introduces one pole in the transfer function. Accordingly, before applying the time-constant method, the network must be simplied in such a way to have only independent capacitors.
Note on time-constant method
C1
C2
Ck
CEQ =
i=1
Ci
C1 C2
Ci CEQ =
k
i=1
i=1
j=1,j=i
Ck
Cj
Part A4
Time-constant method application
Given the following circuit

Rs i1 vs C1 vc C2 gvc RL vo
is
i2
io
Time-constant method example
Figure A4.1 evaluate its high-cut frequency. First, let us evaluate exactly the transfer function vo /vs in the Laplace domain.
vc
Output short-circuit current of circuit in Fig. A4.1
is
Rs i1
i2
C2 gvc
ieq
vs C1
vc
95
The voltage drop on C2 is vc due to the output short-circuit i2 = sC2 vc ieq = i2 gvc = sC2 vc gvc = (sC2 g) vc is = i1 +i2 = sC1 vc +sC2 vc = s (C1 + C2 ) vc = sC2 g 1 + sRs (C1 + C2 ) vs vc Rs vc = vs 1 + sRs (C1 + C2 )
(A4.1)
ieq = vs
The equivalent circuit for evaluating the output equivalent impedance Zout is
Output equivalent impedance of circuit in Fig. A4.1
Rs
is i1 C1 vc
C2
i2 gvc
ix vx
that can be simplied in

C2 i2 gvc ZEQ vc ix vx
where (A4.2) ZEQ = Rs / / 1 Rs = sC1 1 + sRs C1
ix = i2 + gvc , vc =
ix =
1 + gZEQ sC2 vx 1 + sC2 ZEQ
vx sC2 ZEQ vx sC2 vx ZEQ vx , i2 = = = 1 1 1 + sC2 ZEQ 1 + sC2 ZEQ ZEQ + + ZEQ sC2 sC2
hence (A4.3) Zout = vx 1 + sC2 ZEQ = ix sC2 (1 + gZEQ )
96
From (A4.1) and (A4.3) the Norton equivalent of the circuit is
ieq
Norton equivalent of circuit in Fig. A4.1
Zout
RL
vo
Figure A4.2
vo =
Fig. A4.2
(A4.3)
Transfer function of circuit in Fig. A4.1
Zout (sC2 g) RL 1 + sC2 ZEQ ieq RL = vs RL + Zout 1 + sC2 [RL (1 + gZEQ ) + ZEQ ] 1 + sRs (C1 + C2 )
(A4.2)
vo (sC2 g) RL = vs 1 + s [Rs (C1 + C2 ) + (1 + gRs ) RL C2 ] + s2 Rs RL C1 C2
(A4.4)
According to (T7.3) and (T7.4), coecients a1 and a2 of the transfer function in (A4.4) can be evaluated as
Time-constant method applied to circuit in Fig. A4.1
a1 =
i=1 1
0 0 0 Ri Ci = R1 C1 + R2 C2
a2 =
i=1
2 j=i+1
0 As dened before ( pag. 92), R1 is the resistance seen by capacitor C1 with 0 C2 open circuited; R2 is the resistance seen by capacitor C2 with C1 open circuited; 1 R2 is the resistance seen by capacitor C2 with C1 short circuited.
0 Ri Ci
i 0 1 Rj Cj = R1 C1 R2 C2
0 The equivalent circuit for the evaluation of R1 is
Rs
ix gvc vx vc=vx RL
Evaluation of R0 by means 1 of the time-constant method
(A4.5)
0 R1 = Rs
97
Rs
ix
vx gvc vc
i2
RL
vc = ix Rs , i2 =
ix = (gvc + i2 )
vRL vc vx ix Rs vx = = RL RL RL ix Rs vx ix = gvc i2 = gRs ix RL vx Rs = ix 1 + gRs + RL RL

0 R2 =
(A4.6)
vx = RL + gRs RL + Rs ix
Rs
ix vx vc gvc
i2
RL
Since vc = 0, there is no current owing in Rs and the current generator controlled 1 by vc is o. Thus the simplied equivalent circuit for R2 is
ix vx RL i2
(A4.7)
1 R2 =
vx = RL ix
98
Evaluation of coecient a1 by means of the time-constant method Evaluation of coecient a2 by means of the time-constant method
a1 = Rs C1 + (RL + gRs RL + Rs ) C2
(A4.5)
(T7.3),(A4.6)
hence (A4.8) a1 = Rs (C1 + C2 ) + (1 + gRs ) RL C2
that is the same coecient a1 in (A4.4) evaluated in a simpler way.

(A4.5)
(T7.4),(A4.7)
a2 = Rs C1 RL C2 = Rs RL C1 C2
(A4.9)
that is the same coecient a2 in (A4.4) evaluated in a simpler way.
Part T8
Ideal voltage amplier and feedback
VDD v2 vid v1
VDD
VDD
Diff. Ampl. A1
v3
C.S. Ampl. A2
v4
C.D. Ampl. A3
vo
RL
-VSS
Basic conguration of actual operation amplier
RoutA1 RinA2
-VSS
RoutA RinA
2
-VSS
RoutA3
Eects of reactive elements are neglected due to the operational frequency considered. vo v3 v4 vo = v2 v1 v2 v1 v3 v4 RinA2 v3 = A1 vid A1 vid RinA2 + RoutA1 RinA3 A2 v3 v4 = A2 v3 RinA3 + RoutA2 RL vo = A3 v4 depends on RL RL + RoutA3 RoutA3 = minimum output resistance among CS, CG, CD congurations
VDD v+ i+ io vivo
Ideal operation amplier
-VSS
Ideal operation amplier: parameters
vo A= = v+ v (T8.1) i+ = 0 i = 0 io = anything, it depends partially on the external circuit
100
Rin+ = Rin = Rout = 0 (T8.2) v+ v = vid = vo A
Ideal operation amplier: virtual short circuit
lim vid = 0
v+ v
(T8.3)
Feedback
Feedback is a system control technique consisting in looping back the system output signal to the input of the system itself. Feedback can be positive or negative, however in electronic engineering the most commonly used is the negative one. Fig. T8.1 shows the basic structure of a feedback amplier. A(s) is the transfer function of the basic amplier, B is the feedback block and S , SI , SF are signals that are expressed in the same unit. The transfer function of the feedback system is given by S = SI SF
Negative feedback
SF = B SO SO = A(s) S = A(s) (SI SF ) SO = A(s) (SI B SO ) A(s) A(s) SI = SI 1 + B A(s) 1 + T (s)
SI
S"
A(s)
SO
SF
Figure T8.1
(T8.4)
SO =
where T (s) = B A(s) is the loop gain. According to (T8.4) the closed-loop gain AV (s) of the whole system is
Closed-loop gain
(T8.5)
AV (s) =
A(s) SO = SI 1 + T (s)
101
Eq. (T8.3) is valid only when the ideal operation amplier is into a circuit with negative feedback.
v+
Negative feedback circuits based on the ideal operation amplier

vi1
v-
resistive feedback network input coupling output definition vi2
vo
Feedback analysis of circuits based on the ideal operation amplier
1) vi1 = vi2 = = 0 2) remove OA vd 3) evaluate (T8.6) vo 4) the feedback is negative if d vd < 0 d vo
Feedback properties
Let us dene AV0 = AV (0), A0 = A(0) and T0 = T (0) = BA(0) = BA0 . When |A0 | (i.e., |T0 | ) we have
Closed-loop ideal gain
(T8.5)
T0
lim AV0 = lim
T0
A0 1 = 1 + T0 B
(T8.7)
this means that the closed-loop gain is independent of the amplier when the latter has an ideal innite gain (|A0 | ). Actually, we cannot have amplier with innite gain, however (T8.7) can be considered practically true for A0 10. One of the primary purposes of using feedback is to reduce the sensitivity of the system to parameter variations. To illustrate this, evaluate the sensitivity of (T8.5) with respect to parameter variations of A0 using (A2.3). 1 A0 AV0 A0 1 + BA0 BA0 = = AV0 A0 AV0 (1 + BA0 )2 1 + T0
Sensitivity of AV0 with respect to A0
(A2.3)
A0 S AV =
0
(T8.8)
note that (T8.8) tends to 0 when T0 .
Sensitivity of AV0 with respect to B
(A2.3)
B SAV0 =
B AV0 T0 1 = AV0 B 1 + T0
(T8.9)
in other words, every variation in B is reported to the system output with a unity gain.
102
When a real system is analyzed, noise signals must be considered. In order to simplify the analysis, let us consider four possible noise signals d1 , d2 , d3 and d4 injected in four points of the feedback system.
d1 SI S"
A(s)
d2 SO
Noise suppression
SF d4 d3
d1 , d2 and d4 can be considered parametric variations of A0 , whereas d3 is a parametric variation of B. Accordingly, from (T8.8) we expect a noise suppression factor of 1/ (1 + T0 ) and from (T8.9) we expect no suppression. Evaluating the complete closed-loop transfer function when SI = 0 we have (T8.10) AV |SI =0 = d2 (d1 d4 ) A0 d3 T0 + 1 + T0 1 + T0 1 + T0
conrming what stated before. Real ampliers are not linear. However, when a non-linear amplier is inserted in a feedback loop, its non-linearity can be seen as a superimposed noise signal dN L injected as shown in the gure
dNL
Feedback with non-linear amplier
SI
S"
A(s)
SO
SF
and, according to (T8.8), the non-linearity is reduced by a factor 1/ (1 + T0 ). This makes the amplier more linear. A0 (ideal, open-loop) vo dN L (superimposed noise) vo
linear region
vi
vi
103
A0 + dN L (real, open-loop) vo
A0 + dN L / (1 + T0 ) (real, closed-loop) vo
linear region
linear region
vi
vi
Feedback increases the system bandwidth (compared to the bandwidth of the basic amplier). To prove this, consider the simple case when the basic amplier has a single pole
Bandwidth extension
A(s) =
A0 1 + s/p
(T8.5)
AV (s) =
A0 1 + BA0 1 +
s p (1 + BA0 )
(T8.11)
Therefore, the bandwidth of the closed-loop system is (1 + BA0 ) times bigger than that of the basic amplier. This is an advantage for almost every type of circuits. However, the increased bandwidth can be a drawback since high frequency noise can be injected into the system. According to (T8.11), the gain-bandwidth product (GBW) between the basic amplier A(s) and the closed-loop gain AV (s) is constant
Gainbandwidth product
(T8.11)
|A0 | p =
A0 p |1 + BA0 | 1 + BA0
(T8.12)
A0 is the closed-loop gain, p is the amplier 1 + BA0 bandwidth and p |1 + BA0 | is the closed-loop bandwidth. This simple property says that the feedback extends the closed-loop bandwidth at the expense of a reduction in gain (with respect to the basic amplier A(s)). where A0 is the amplier gain, Given a transfer function A(s), the angular frequency at which |A(j)| = 1 is called transition angular frequency T . Accordingly, for a single-pole transfer function A0 A(s) = the transition angular frequency is 1 + s/p |A0 | A0 = 1, thus = |A(jT )| = 1 + jT /p 2 1 + (T /p ) (T8.13) T = p A2 1 |A0 | p 0 (|A0 | 1)
Transition angular frequency and gainbandwidth product
comparison of (T8.13) and (T8.12) shows that, for a single-pole transfer function, the gain-bandwidth product is approximately equal to the transition angular frequency.
104
20 log |A0 | A0 1 + BA0
20 log
p |1 + BA0 |
Figure T8.2
Feedback topologies
The unilar model presented in Part T8 is only an idealization. In fact, in a system every block is connected to others blocks at least with two wires, as shown in Fig. T8.3.
signal mixing
A(s)
sampling
load
The bilar model
Sm
Ss
Figure T8.3 Note that the block is equal to the block B in T8.1 only if the sampled (Ss ) and the mixed (Sm ) signals are expressed with the same unit (e.g. Volt, Ampere). In this case = B is a unitless quantity. When the sampled (Ss ) and the mixed (Sm ) signals havent the same unit, the quantity is such that Sm = Ss (i.e., Sm and Ss have the same unit). According to the bilar model, there are two possible combinations for the sampling network, and two for the mixing network.
ZO
A(s)
VO
load
Voltage (shunt) sampling
VO
Figure T8.4
ZOUT
(T8.14)
ZOUT =
ZO 1 + T0
105
ZO IO
A(s)
load
Current (series) sampling
IO
B
ZOUT
Figure T8.5
(T8.15)
ZOUT = ZO (1 + T0 )
ZI
signal
A(s)
Voltage (series) mixing
VF ZIN
Figure T8.6
B
(T8.16)
ZIN = ZI (1 + T0 )
ZI
signal
A(s)
Current (shunt) mixing
IF ZIN IF
Figure T8.7
B
(T8.17)
ZIN =
ZI 1 + T0
Part A5
vi vo
Figure A5.1 v+ = 0
Voltage follower based on OA
(T8.6)
v = vo
vo
vd = vo
d vd = 1 d vo
negative feedback
Verify the feedback type for the circuit
vi vo

(T8.3)
(T8.1),(T8.2)
v+ = vi
v = vo
vo =1 vi
(A5.1)
107
vi R vo
Non-inverting amplier
Figure A5.2 v =
R vo
vo R1 R1 + R2
(T8.6)
v+ = 0 vd = vo R1 R1 + R2
R1 d vd = = > 1 negative feedback d vo R1 + R2

(T8.3)
(T8.1),(T8.2)
vi = v+ = v =
vo R1 R1 + R2
vo = vi
1+
R2 R1
(A5.2)
R2 R1
vi vo
Inverting amplier
R1
(T8.6)
Figure A5.3
R2
v =
vo
vo R1 R1 + R2
v+ = 0 vd = vo R1 R1 + R2
d vd R1 = < 0 negative feedback d vo R1 + R2

(T8.1),(T8.2) (T8.3)
108
v+ = v = 0 vo = R2 vi R1
vi vo + =0 R1 R2 (A5.3)
vo R2 = vi R1
R2
R1
Inverting adder
vi1 vi2
R1 vo
Figure A5.4
(T8.1),(T8.2) (T8.3)
vi vo vi1 + 2 + =0 R1 R1 R2 R2 R1 (A5.4)
vo = (vi1 + vi2 )
R2
R1
Subtractor
vi1
R1 vo vi2 R2
Figure A5.5 R2 R2 R2 vi + vi = (vi vi1 ) R1 1 R1 2 R1 2

(A5.3)
(A5.2)
vo =
(A5.5)
Part T9
Stability analysis of feedback ampliers
Stability analysis
An amplier A(s) stable in an open-loop system could not be stable in a feedback loop: to use A(s) in a closed-loop system it is necessary a stability analysis. If the stability analysis results in a possible instability, a compensation procedure on the amplier has to be applied. A stability analysis starts from the loop gain T (s) dened in Part T8. However, to calculate T (s) it is possible to use the following sequence of operations instead of computing the whole system closed-loop gain. Consider a single-pole basic amplier with transfer function A(s) = A0 1 + s/p The related closed-loop trans-
where p is the angular frequency of the pole. fer function is
Single-pole amplier
AV (s) =
A0 1 + BA0 1 +
s p (1 + BA0 )
thus the feedback moves the closed-loop pole p,cl along the negative (p is negative) real axis to (T9.1) p,cl = p (1 + BA0 )
in other words the feedback system is always stable. Consider a stable amplier with two real and negative poles A(s) = A0 (1 + s/p1 ) (1 + s/p2 )
the related closed-loop transfer function has two poles given by
Two-pole amplier
s2 + (p1 + p2 ) s + (1 + BA0 ) p1 p2 = 0 (T9.2) 1 1 s = (p1 + p2 ) 2 2 (p1 + p2 ) 4 (1 + BA0 ) p1 p2

2
(T9.4)
Eq. (T9.2) shows that poles become closer as BA0 is increased from zero.
110
(p1 + p2 ) 1, the poles are coincident, and for greater values of 4p1 p2 1 BA0 the poles are complex conjugates with a real part equal to (p1 + p2 ). 2 Accordingly, a feedback system based on a stable basic amplier with two poles is always stable. When BA0 =
Ampliers with at least three poles
When a basic amplier with three or more poles is considered, a stability analysis is required.
Consider the generic loop gain transfer function in the Bode form
m1 m2
(1 + s/nz,i ) T (s) = T0
i=1 n i=1
(1 s/pz,i )
(1 + s/p,i )
i=1
with modulus
m1 m2
1 + (/nz,j )
2 i=1
1 + (/pz,j )
The loop gain modulus
|T (j)| = |T0 | i=1
1 + (/p,j )2
i=1
where nz,i are the angular frequencies of zeros with negative real part, pz,i are the angular frequencies of zeros with positive real part, p,i are the poles angular frequencies (we cannot have poles with negative real part since we are considering only stable circuits), m = m1 + m2 is the degree of the numerator, and n is the degree of the denominator. Circuits we are interested in have always n > m, i.e. the degree of the denominator is always greater than that of the numerator. Therefore, wm lim |T (j)| = |T0 | and lim |T (j)| |T0 | n 0 since n > m. Thus, |T (j)| 0 w is a continuous-always-positive function of , it tends to |T0 | when 0 and is approximately zero for high values of ; hence, |T (j)| decreases as increases. Furthermore, from (T8.4) we have |T0 | = |B A0 |; consequently, considering that |B| 1 (we use always passive components to build the feedback block), |T (j)| decreases as B decreases. The phase of the loop gain at the angular frequency is always given by
m1
(T9.3)
T (j) =
i=1
arctan
nz,i
m2
The loop gain phase
arctan
i=1
pz,i
arctan
i=1
p,i
Note that, as regards phase, the zeros with a positive real part behave like poles. Therefore, lim T (j) = 0 and lim T (j) 90 (m1 m2 n) = 90 (n m).
0
Thus, T (j) is a continuous function of , it is equal to 0 when 0 and tends to an integer multiple of 90 for high values of (n m is integer since both n and m are integers).
The poles of the feedback amplier are the zeros of denominator of (T8.5), i.e.
Characteristic equation
(T9.4)
1 + T (s) = 0 T (j) = 1 |T (j)| = 1 and T (j) = 180
this is called the characteristic equation of the feedback loop.
111
From the above considerations, considering B=1 (i.e., the worst case condition for the loop gain modulus) and calling T the angular frequency at which |T (jT )| = 1 and the phase of the loop gain at that frequency = T (jT ) we can have the following cases
Im [T (j)]
Loop gain phase
> 180 The feedback system is stable since there is no value of B (0 B 1) and such that T (j) = 1.
unit circle
1
T (j) T (0) Re [T (j)]
(1, 0)
T (jT ) B =1 B = 0.5
Im [T (j)]
< 180 There is at least one value of B (0 B 1) and of such that T (j) = 1. The feedback system is unstable.
T (jT )
unit circle
1
T (0) Re [T (j)]
(1, 0) T (j)
B =1 B = 0.5
Im [T (j)]
= 180 The feedback system is on the border between stability and instability. This means that a little alteration in T0 , i.e. a variation of B, can produce an unstable system.
1
T (jT )
unit circle
T (0) Re [T (j)]
(1, 0) T (j)
B =1 B = 0.5
Loop gain modulus
Analogously, considering B=1 (i.e., the worst case condition for the loop gain modulus) and calling 180 the frequency at which T (j180 ) = 180 and M the modulus of the loop gain at that frequency M = |T (j180 )| we can have
Im [T (j)] M
unit circle
M <1 The feedback system is stable.
T (j180 )
T (0) Re [T (j)]
(1, 0) T (j)
180
B =1 B = 0.5

Im [T (j)] M T (j180 )
112
unit circle
1
T (0) Re [T (j)]
M >1 The feedback system is unstable.

(1, 0) T (j)
180
B =1 B = 0.5
Im [T (j)] M T (j180 )
unit circle
1
T (0) Re [T (j)]
M =1 The feedback system is on the border between stability and instability.

(1, 0) T (j)
180
B =1 B = 0.5
To simplify the stability analysis, two parameters are commonly introduced Phase margin P M = 180 + T (jT )
Gain and phase margins
Gain margin GM = 20 log
1 T (j180 )
where T and 180 are dened above. According to the previous analysis we have a stable system only if P M > 0 or, alternatively, if GM > 0. However, since phase margin and gain margin are equivalent, usually only the phase margin is considered. Time response av (t)
P M = 90
System with phase margin equal to 90
The system is stable, but its response in the time domain is slow (i.e., it reaches the 90% of the steady state in relative high time).
Frequency response
(dB) 1
|AV (j)| / |AV 0 |
2 103
102
101
100
101
102
103
/H
113
Time response av (t)
P M = 60
The system is stable and its response in the time domain is fast even if there are some initial oscillations. The passband is greater than systems with a 90 phase margin.
Frequency response
1 (dB)
|A (j)| / |A0 |
2 103
102
101
100
101
102
103
/H
Time response av (t) P M = 30 The system is stable and its response in the time domain is fast but there are too initial oscillations. The passband is greater than systems with a 60 phase margin but there is a no at passpand due to the peak in the frequency response.
Frequency response
1 (dB)
|A (j)| / |A0 |
2 103
102
101
100
101
102
103
/H
What is the best phase margin?
According to the previous plots, systems with 60 phase margin are stable and faster than system with P M = 90 . The only drawback is the presence of some initial oscillations. However, this oscillations rapidly stabilize thus they do not heavily aect the system time-domain response.
114
Compensation
The term compensation refers to methods used for modifying the loop gain T (s) of a feedback system so that the it is stable for any desired value of the closed-loop gain. The most common compensation methods are the compensation by reduction of the loop gain and the compensation by reduction of the ampliers bandwidth. The latter is usually referred to as narrow-banding. For both cases, the most dicult condition to compensate is when B = 1 ( pag. 100), since for a unity-gain feedback (i.e., B = 1) the closed-loop gain is approximately equal to 1 (from (T8.7) we have AV 1/B = 1). Therefore, the loop gain is equal to the transfer function of the basic amplier. Accordingly, only the case when B = 1 is compensated since if the system is stable for a unity-gain feedback, it will be stable for every value of B 1 (remember that B is always lower or equal to 1, since it is obtained using passive networks ( pag. 100)). This compensation technique aims at the reduction of the gain of the basic amplier and it is usually used when a dominant pole is already present in the amplier. When the basic amplier has a dominant pole 1 , the transition angular frequency can be written as ( pag. 103) T |A0 | 1 , where A0 has the usual meaning. In a dominant-pole amplier the phase margin is given by P M = 90 arctan
(T9.9)
T 2
where 2 is the angular frequency of the second pole. Hence, we can nd the value of |A0 | needed to achieve the desired phase margin. Accordingly, we have (T9.5) |A0 | = tan (90 P M ) 2 2 = 1 1 tan (P M )
Compensation by reduction of the loop gain
an example of this compensation technique is plotted in Fig. T9.1. Note that the Bode modulus plot before compensation (solid line) and the Bode modulus plot after compensation (dashed line) are parallel: this means that the pole angular frequencies are unchanged. Furthermore, note that the phase is not aected by this compensation technique. Only the transition angular frequencies T (i.e., the transition angular c frequency before compensation) and T (i.e., the transition angular frequency after compensation) and the loop gains are changed.
100 1 c T 2 T
50
20 log |A (j)|
50
50
A (j)
100
100 115 150 162 200 104
150
200 104
103
102
101
100
101
102
103
before compensation
after compensation
Figure T9.1
115
Consider the generic transfer function of the basic amplier (i.e., the transfer function of the loop gain since B = 1) in the Bode form
m1 m2
(1 + s/nz,j ) (T9.6) A(s) = A0

j=1 n j=1
(1 s/pz,j )
(1 + s/p,i )
i=1
where p,1 < p,2 < < p,n , nz,1 < nz,2 < < nz,m1 and pz,1 < pz,2 < < pz,m2 . The narrow-banding compensation technique requires the modication of the angular frequency of the rst pole (i.e., p,1 ) such as to obtain a dominant pole system
m1 m2
(1 + s/nz,j ) (T9.7) A(s) = A0

j=1 j=1 n
(1 s/pz,j )
(1 + s/D )
i=2
(1 + s/p,i )
Narrowbanding
c where T is the transition angular frequency of the compensated system and p,2 is the angular frequency of the second pole. Note that the approximations in (T9.8) are correct only if D p,i for every i [2..n], if D nz,i for every i [1..m1 ] and if D pz,i for every i [1..m2 ]. From (T9.8), we obtain a general equation for evaluating the angular frequency of the dominat pole D that leads to the desired phase margin
where D is the angular frequency of the dominat pole obtained after the compesation. In a dominant pole system we can write c T |A0 | D n c c T T (T9.8) arctan 90 arctan P M = 180 + A(jT ) 90 p,i p,2 i=2
(T9.9)
D =
p,2 . |A0 | tan (P M )
As stated before, the narrow-banding compensation technique is based on the modication of the angular frequency of the pole of the transfer function with lowest angular frequency. To this aim, the most commonly used techiques are the pole dominant compensation and the Miller compensation.
116
The basic amplier circuit ( pag. 100) of a feedback system usually consists of cascaded stages. Each stage can introduce one or more poles and/or zeros in the transfer function. Let us suppose that nodes Ni and Nj of the basic amplier contribute to the pole p1 of the system transfer function with the lowest angular frequency p,1 according to the general equation (T9.10) p,1 = 1 Req,ij Ceq,ij
Pole dominant compensation
where Req,ij and Ceq,ij are the equivalent resistance and capacitance seen between nodes Ni and Nj .
Ni
signal stage 1 stage k stage n load
Nj
With the pole dominant compensation technique, the designer modies the angular frequency of p1 by connecting a parallel capacitor between nodes Ni and Nj such as to make p1 a dominant pole (hence the name of this technique). The new angular frequency of p1 is given by
(T9.10)
D =
1 Req,ij (Ceq,ij + CC )
(T9.11)
where CC is the so called compensating capacitor.

Ni
signal stage 1 stage k
CC Nj
stage n
load
Then, by using (T9.9) and (T9.11) we evaluate the capacitance of CC that leads to the desired phase margin
(T9.11) (T9.9)
CC =
|A0 | tan (P M ) Ceq,ij . p,2 Req,ij
(T9.12)
Note that a value of CC lower than zero means that either the system does not need compensation or the desired phase margin is not achievable.
117
Consider the amplier circuit in Fig. T9.2 with the input modelled as a Thevenin equivalent and the output modelled as a Norton equivalent.
A vi R1 C1 v1 g1v1 R2 C2 vo B
Miller compensation
Figure T9.2 The circuit has 2 poles with angular frequencies 1 = 1/ (R1 C1 ) and 2 = 1/ (R2 C2 ) and its transfer function vo /vi is (T9.13) vo 1 = g1 R2 . vi (1 + sR1 C1 ) (1 + sR2 C2 )
The Miller compensation technique requires the modication of the above amplier by connecting a capacitor CM and a resistor RM between nodes A and B as shown in Fig. T9.3. In the following, we evaluate the capacitance of CM and the resistance of RM needed to obtain the desired phase margin.
A vi R1 C1 v1 CM RM g1v1 R2 C2 vo B
Figure T9.3 Note that this modication of the circuit in Fig. T9.2 does not alter its the passband voltage gain since the circuits in Fig. T9.2 and in Fig. T9.3 are equivalent in the passband region.
118
The circuit in Fig. T9.3 has three poles and one zero; its transfer function is 1 1 + s RM CM vo g1 = g1 R2 vi a 3 s3 + a 2 s2 + a 1 s + 1
(T9.14)
where coecients a1 , a2 , a3 can be evaluated by resorting to the time-constant method ( pag. 92) and result to
(T7.3) (T7.4)
Furthermore, by neglecting the contribution of the third pole, the angular frequencies of the zero, the rst and second pole are given by z = 1 RM 1 g1 CM . (T9.16)
a1 = R1 C1 + R2 C2 + CM [R1 (1 + g1 R2 ) + R2 + RM ] a2 = R1 C1 [R2 C2 + (R2 + RM ) CM ] + R2 C2 (R1 + RM ) CM . a3 = R1 C1 R2 C2 RM CM
(T9.15)
(T7.2)
It is clear that the angular frequency of the zero depends on the value of RM . Actually, the zero is unwanted since it may be a source of instability when we put the amplier in a feedback system, hence its angular frequency should be set as high as possible to make negligible the eect of the zero on the phase margin. To be more specic we should set the value of z such that z 2 . This can be achieved simply choosing RM as close as possible to 1/g1 . Indeed, when RM 1/g1 we reach the desired condition z . Additionally, notice that k = g1 R2 is the passband voltage gain between nodes A and B. Therefore, we have z and
(T9.16)
1 1 c = 1 a1 R1 C1 + R2 C2 + CM [R1 (1 + g1 R2 ) + R2 + RM ] c R1 C1 + R2 C2 + CM [R1 (1 + g1 R2 ) + R2 + RM ] 2 a1 = a2 R1 C1 [R2 C2 + (R2 + RM ) CM ] + R2 C2 (R1 + RM ) CM
c 1
Now, let us consider the following conditions k<0 |k| 1
1 R1 C1 + R2 C2 + CM [R1 (1 k) + R2 + 1/g1 ] R1 C1 + R2 C2 + CM [R1 (1 k) + R2 + 1/g1 ] c 2 R1 C1 [R2 C2 + (R2 + 1/g1 ) CM ] + R2 C2 (R1 + 1/g1) CM
(T9.17)
this condition is required (see below) otherwise the Miller compensation cannot be used this condition is usually true since the circuit is an amplier If this condition is false than the amplier is not correctly compesated. However, the Miller compensation can still be used and the only drawback is that the actual phase margin after the compensation is dierent from the desired one. A value C2 /CM 10 is accettable.
CM NOT much lower than C2
Under these conditions, (T9.17) approximates to

c (T9.18) 1
1 1 R1 C1 + R2 C2 + R1 (1 k) CM R1 [C1 + (1 k) CM ] g1 C1 /R2 + g1 CM R1 [C1 + (1 k) CM ] R1 R2 [C1 (C2 + CM ) + C2 CM ] C1 CM + C2 CM C1 + C2
c (T9.19) 2
119
From (T9.18) it is clear that the capacitor CM is seen by the circuit as if it was in parallel to C1 and multiplied by 1 k. This is called Miller eect (hence the name of this compensation technique) ( pag. 60) and it is a direct consequence of the Miller theorem ( pag. 59). Comparison of the angular frequencies of the poles of the circuits in Fig. T9.2 and Fig. T9.3 shows that the Miller compensation modies both the rst and the second pole of the circuit. To be more specic, the angular frequency of the rst pole of the c compensated circuit is lower than the rst pole in the original circuit (i.e., 1 < 1 ), whereas the angular frequency of the second pole in the compensated circuit is higher c than the second pole in the original circuit (i.e., 2 > 2 ). This phenomenon is called pole splitting. Finally, by applying (T9.9) we obtain the capacitance of CM that leads to the desired phase margin
(T9.19) (T9.18)
CM =
C1 C1 + C2 |A0 | tan (P M ) . |k| g1 R1 |k|
(T9.20)
As in the case of the dominant pole technique ( pag. 116), a value of CM lower than zero means that either the system does not need compensation or the desired phase margin is not achievable. Considering the circuit in Fig. T9.2, let us compensate it for a given phase margin P M with both the pole dominant compesantion and the Miller compesantion. By observing the circuit we can have 2 possible cases: 1 < 2 and 1 > 2 . First let us suppose 1 < 2 . In this case, with the pole dominant compensation we have to introduce a capacitor CC between node A and ground as shown in Fig. T9.4.
A vi R1 C1 CC v1 g1v1 R2 C2 vo B
Comparing the eectiveness of the pole dominant compensantion and the Miller compensantion
Figure T9.4 Therefore the angular frequencies of the poles of the compensated system are 1 R1 (C1 + CC ) (T9.21) c = = 1 2 2 R2 C2 c = 1
and by applying (T9.9) we obtain 1 1 R2 C2 = R1 (C1 + CC ) |A0 | tan (P M ) R2 C2 |A0 | tan (P M ) C1 . R1
(T9.22)
CC =
Comparison of (T9.22) and (T9.20) shows that if 1 < 2 the dominant pole compensation is more eective (i.e., CC < CM ) than the Miller compensation if R2 C1 + C2 C1 + C2 C2 |A0 | tan (P M ) < |A0 | tan (P M ) |k| g1 R2 < R1 |k| g1 R1 C2 k2 < C1 + C2 C2 |k| < C1 + C2 C2
(T9.23)
Note that this condition was obtained ignoring the term C1 / |k| in (T9.20) and the term C1 in (T9.22) since they are divided by |A0 | tan (P M ) and hence negligible.
120
Now let us consider the case when 1 > 2 . In this case, with the pole dominant compensation we have to introduce a capacitor CC between node B and ground as shown in Fig. T9.5.
A vi R1 C1 v1 g1v1 R2 B C2 CC vo
Figure T9.5 Therefore the angular frequencies of the poles of the compensated system are 1 R1 C1 (T9.24) 1 c = 2 R2 (C2 + CC ) c = 1 = 1
and by applying (T9.9) we obtain 1 1 R1 C1 = R2 (C2 + CC ) |A0 | tan (P M ) R1 C1 |A0 | tan (P M ) C2 . R2
(T9.25)
CC =
Comparison of (T9.25) and (T9.20) shows that if 1 > 2 the dominant pole compensation is more eective (i.e., CC < CM ) than the Miller compensation if R2 C1 + C2 C1 + C2 R1 C1 |A0 | tan (P M ) < |A0 | tan (P M ) g1 1 |k| < R2 |k| g1 R1 R2 C1
2 2 g1 R1 <
(T9.26)
C1 + C2 C1
g1 R1 <
C1 + C2 C1
As done in the previous case, this condition was obtained ignoring the term C1 / |k| in (T9.20) and the term C2 in (T9.25) since they are divided by |A0 | tan (P M ) and hence negligible.
Part E2
Compensation examples
Compensation example
Given the basic amplier with the following transfer function (i.e., the loop gain transfer function since B = 1) A(s) = A0 (1 + s/1 ) (1 + s/2 ) (1 + s/3 )
where A0 = 3000, 1 = 1 rad/s, 2 = 10 rad/s e 3 = 100 rad/s, calculate the dominant pole required to give a phase margin of 60 . As explained above we have to add a dominant pole to the system, let us call D the angular frequency of the added pole. The new system will have a compensated transfer function given by AC (s) = A0 (1 + s/D ) (1 + s/1 ) (1 + s/2 ) (1 + s/3 )
In a single-pole system the gain-bandwidth product ( pag. 103) is approximately equal to the transition angular frequency. This is also approximately true for a system with a dominant pole ( pag. 92). Accordingly, since D is the bandwidth ( pag. 92) of the compensated transfer function and A0 is its gain, we can evaluate the transition angular frequency of the c c compensated system simply with T |A0 | D and thus P M = 180 + AC (jT ) where
(T9.3) c AC (jT ) = arctan c T D
arctan
c T 1
arctan
c T 2
arctan
c T 3
c We dont know T but we can write
arctan arctan
c T D c T 2
= arctan (|A0 |) 90 since |A0 | 1 = arctan

c T 3 c c 0 since T 2 and T 3
thus the phase margin only depends on the angular frequency 1 P M = 90 arctan
c T . 1
122
We want a phase margin of 60 so P M = 90 arctan

c T 1
= 60 arctan 3 3
c T 1
= 30
c and thus T = 1 tan (30) = 1
D =
1 3 192.5 rad/s . |A0 | 3
c T = tan (30) 1
This is the angular frequency of the dominant pole that makes the phase margin equal to 60 . Now we have to verify all the assumptions used to nd the value of D .
c T |A0 | D arctan (|A0 |) 90 c T 2 c T 3 P M = 60
D
? ? ? ? ?
c T = 0.51 rad/s |A0 | D = 0.57 rad/s arctan (3000) = 89.981 arctan (0.57/10) = 3.26 arctan (0.57/100) = 0.327 P M = 60.148
c 1 T 2 3 T
100
50
20 log |A (j)|
Bode plots for the original and compensated systems
50
90 120
A (j)
100
180 229
150
270
200 105
104
103
102
101
100
101
102
103
360 104
before compensation after compensation
Given the following amplier

R1 g1v1 vi C1 v1 R2 C2 v2 A g2v2 R3 C3 vo B
Compensation example on a simple 3-stage amplier
Figure E2.1 with R1 = 50 R2 = 10 k R3 = 500 C1 = 1 nF C2 = 20 nF C3 = 1 nF g1 = 200 mS g2 = 400 mS. Supposing to use this amplier as a basic amplier in a feedback system with B = 1, compensate the amplier so that its phase margin is 60 .
123
The circuit voltage transfer function vo /vi is A(s) = 1 g1 R2 g2 R3 g1 g2 R2 R3 = 1 + sR1 C1 1 + sR2 C2 1 + sR3 C3 (1 + sR1 C1 ) (1 + sR2 C2 ) (1 + sR3 C3 ) 1 =
Thus |A0 | = 4 105
1 = 5 krad/s R2 C2 1 1 2 = = 2 Mrad/s 3 = = 20 Mrad/s. R3 C3 R1 C1
According to the previous section we can compensate the amplier connecting a capacitor between nodes related to the system pole with lowest angular frequency. Since the pole with lowest frequency is 1 , we have to connect a capacitor between nodes A (see Fig. E2.1) and ground (i.e., in parallel with C2 ).
R1 g1v1 vi C1 v1 R2 C2 CC v2 A g2v2 R3 C3 vo
The angular frequency of the dominant pole is D =
1 , the pole with R2 (C2 + CC ) angular frequency 1 is no more present, and the second pole of the system has an angular frequency equal to 2 (it is not aected by CC ). Now we have to nd the capacitance CC that gives an amplier with a phase margin of 60 . D =
(T9.9)
1 2 = R2 (C2 + CC ) |A0 | tan (P M )
Hence CC = |A0 | tan (P M ) C2 35 F R2 2
(this is only an example, usually the compensating capacitor has smaller capacitance). Now we have to verify the underlying hypotheses of equation (T9.9): 5 105 2.325 c = 3.32 T = |A0 | D 3 ? arctan 2 107 Consider the example circuit in Fig. E2.2 with R1 = R2 = 10 k, C1 = 100 pF, C2 = 1 pF and g1 = 50 mS.
A B g1v1 C1 v1 R2 C2 vo
Miller compensation example
vi
R1
Figure E2.2 By using the time-constant method ( = 1 1 = 1 Mrad/s R1 C1 1 = 2 = 10 Mrad/s R2 C2 pag. 92) the circuit poles are
(T7.2)
(E2.1)
and its passband gain is A0 = g1 R2 = 500.
124
The passband gain between nodes A and B is equal to k = g1 R2 = 500, thus, we can compensate the circuit using the Miller compensation connecting a capacitor CM and a resistor RM = 1/g1 = 20 between nodes A and B.
A vi R1 C1 v1 CM RM g1v1 R2 C2 vo B
Figure E2.3 Hence, we have

(T9.20)
CM =
C1 C1 + C2 |A0 | tan (P M ) 150 fF |k| g1 R1 |k|
(E2.2)
and C2 /CM 6.67 < 10 means that the Miller compensation is eective. By using the pole dominant compensation we have to introduce a capacitor CC between node A and ground since 1 < 2 .
A vi R1 C1 CC v1 g1v1 R2 C2 vo B
Figure E2.4 Therefore,

(T9.22)
CC =
R2 C2 |A0 | tan (P M ) C1 766 pF R1
(E2.3)
thus it is clear that the Miller compensation is more eective seeing that CM CC . This result can be simply obtained evaluating the condition in (T9.23) that, being false, reveals that the Miller compensation is more eective than the pole dominant compensation for the considered circuit
(T9.23)
|k| <
C1 + C2 C2
500 <
101 1012 10. 1 1012
(E2.4)
Part T10
Techniques used to analyze feedback ampliers
Rosenstarks formula is a powerful methodology for evaluating the closed-loop gain of a feedback system when the system complexity is so high to make Kirkos laws not eective. According to Rosenstark formula the closed-loop gain of a system is
Rosenstarks formula
(T10.1)
AV =
GA T + GD 1+T
where GA is the asymptotic gain, GD is the direct gain and T is the return ratio (not to be confused with the loop gain dened in Part T8). Note that equation (T10.1) is valid even for systems without feedback, in this case GA = T = 0, thus AV = GD . Consider a circuit with a non-zero number of dependent generators (in a feedback system there is at least one dependent generator). Each generator has a control law given in the form y = k x, where x is the controlling electrical variable, k is the gain and y is the generated electrical variable. For example, in the circuit
Rs gvc
R1 vs R2 vc vo
Return ratio
there is a dependant current generator g vc controlled by the voltage vc . In this case k is a conductance. To evaluate the return ratio, set all independent generators to zero (e.g. vs = 0), choose a dependent generator (e.g. g vc ) and substitute it with an independent generator Y generating the same electrical variable with the same polarity. Let us call the controlling variable X (e.g. X = vc ). The return ratio is dened as (T10.2) T = k X Y
Techniques used to analyze feedback ampliers
126
Asymptotic gain
Calling so the systems output signal (e.g. so = vo ) and si the systems input signal (e.g. si = vs ), the asymptotic gain is dened as the systems gain so /si when T . According to (T10.2), T is equivalent to k (e.g. g ) (T10.3) GA = lim
T
so so = lim k si si
The direct gain is dened as the systems gain so /si when T 0 (i.e., k 0).
Direct gain
(T10.4)
GD = lim
T 0
so so = lim k0 si si
Blackmans formula is useful to evaluate equivalent impedances in complex systems. Consider the case when the equivalent impedance Zeq between nodes A and B of the network in gure is required.
Z A B
network
Blackmans formula
Blackmans formula states that (T10.5) Zeq = Z0 1 + TSC 1 + TOC
where Tsc is the return ratio (same denition as for the Rosenstarks formula) when nodes A and B are short-circuited, Toc is the return ratio when nodes A and B are open-circuited and Z0 is the equivalent impedance seen from A-B when the dependent generator used for evaluating Tsc and Toc is o.
Part E3
Examples of the Rosenstark and Blackman formulas
Rs
is i1
is
R1 v1 R2 v2
Return ratio example

X = Rs is is = i1 + Y R2 Rs X i1 = v1 R1 X R1 v1 = (X + v2 ) 1+ R2 Rs v2 = R2 is = is = X R1 R2 X Rs R2 1+ +Y Rs
v1 = 1 + X=
i1 =
X (Rs + R2 ) + Rs Y R1
T = g
X R1 Rs = g Y R1 + R2 + Rs
Rs
is
gvc
is
R1 vs R2 vc vo
Asymptotic gain example

Note that if g then vc 0 because the product g vc must be nite (otherwise the circuit violates the conservation of energy law because is able to produce an vs innite energy g vc from a nite source of energy vi ).vc 0 is = Rs vo = R2 is = vs R2 Rs GA = vo R2 = vi Rs
128
Rs
is
is
is
R1 R2 vo
Direct gain example
vs
vo = R2
vs R1 + R2 + Rs
GD =
vo R2 = vi R1 + R2 + Rs
Rosenstarks formula example
Joining previous results we have AV = (1 gR1 ) R2 R1 + R2 + (1 gR1 ) Rs
Given the circuit in gure evaluate the equivalent resistance between nodes A and B (i.e., ground).
Rs gvc A
Blackmans formula example
R1 vs R2 vc vo
Rs
R1
Blackmans formula example: evaluation of Tsc

R1 and Rs are in parallel X = R1 / s Y /R Tsc = g
X = gR1 / s /R Y
129
Rs
R1
Blackmans formula example: evaluation of Toc
There is no current owing in Rs , and the current generated by Y goes all in R1 X=0 Toc = g X =0 Y
Rs
ix
Blackmans formula example: evaluation of R0

vx = R1 + Rs ix
R1 vx
R0 =
Blackmans formula example
Joining previous results we have Req = (R1 + Rs ) (1 gR1 / s ) = R1 + (1 gR1 ) Rs /R
Part E4
Esercizi su amplicatori, retroazione e compensazione
Dato il seguente circuito
VI
Esercizio A
a1 =
(T7.4) (T7.3) n 0 Ri Ci , i=1
VO
n1
a2 =
i=1
n j=i+1
calcolare la funzione di trasferimento in bassa frequenza ( = 0). Calcolare i coecienti a1 ed a2 della funzione di trasferimento, nel dominio di Fourier, con il metodo delle costanti di tempo; vericare la validit` dellapprossimazione a polo dominante a e, dopo aver denito la frequenza di taglio, nel caso sia valida lapprossimazione calcolarla numericamente (R1 = R2 = R3 = 1 k, C1 = C2 = C3 = 1 pF). Si consideri il seguente circuito a due poli
0 Ri Ci
i Rj Cj
RS VS
Esercizio B
C VI
G VI R C VO
Dopo aver ricavato la funzione di trasferimento VO /VS nel dominio di Laplace ed evidenziato il guadagno in continua, compensare opportunamente il circuito al ne di ottenere un circuito a polo dominante con un margine di fase pari a 60 ; si giustichi inoltre la scelta del metodo di compensazione usato. RS = 50 , R1 = 5 k, R2 = 1 k, G = 30 mS, C1 = 5 pF, C2 = 10 pF
131
Si consideri il seguente circuito a due poli
G VI IS
Esercizio C
Dopo aver ricavato la funzione di trasferimento VO /IS nel dominio di Laplace ed evidenziato il guadagno in continua, compensare opportunamente il circuito al ne di ottenere un circuito a polo dominante con un margine di fase pari a 60 ; si giustichi inoltre la scelta del metodo di compensazione usato. Per la compensazione del circuito si consideri B = 1 1 . R1 = 5 k, R2 = 1 k, G = 30 mS, C1 = 5 pF, C2 = 10 pF Si consideri il seguente circuito a due poli
VI
VO
R VS
Esercizio D
C VI
G VI R C VO
Ricavare la funzione di trasferimento VO /VS nel dominio di Laplace evidenziando il guadagno in continua. Supponendo di retroazionare tale amplicatore (blocco A) con un guadagno B = 1 valutare la frequenza di taglio del sistema retroazionato. Dimostrare analiticamente la formula utilizzata nel calcolo. R1 = 10 k, R2 = 1 k, G = 10 S, C1 = C2 = 1 pF Dato il seguente amplicatore dierenziale (con specchio di corrente sui source), calcolare il CMRR evidenziando e commentando tutti i passaggi.
VDD
RD RC
RD
Esercizio E
vi
M vi
-V S S
132
Dati i seguenti amplicatori basati su MOSFET e BJT e polarizzati con 4 resistori, trovare le condizioni in forma simbolica per raggiungere lo stesso guadagno e commentare il risultato. (VSS = VDD = VCC = VEE = 5 V)
VDD VCC
RD CO Rs M RL vo vi RS CS CI
RC CO Q
Esercizio F
Rs CI
RL
vo
vi
RE
CE
-V S S
-V E E
Esercizio G
Disegnare due amplicatori in congurazione invertente e non invertente rispettivamente, utilizzando un amplicatore operazionale caratterizzato da un guadagno di tensione A = 104 10%, Ro = 500 . Calcolare come la tolleranza su A si ripercuota sul guadagno di tensione dellamplicatore retroazionato.
Bibliography
[1] J. Millman and A. Grabel, Microelettronica, 2nd ed. McGraw-Hill, 1988. [2] URL: http://hyperphysics.phy-astr.gsu.edu/hbase/hframe.html [3] URL: http://en.wikipedia.org/wiki/Zener breakdown [4] URL: http://en.wikipedia.org/wiki/Avalanche breakdown [5] URL: http://en.wikipedia.org/wiki/Two-port network [6] URL: http://en.wikipedia.org/wiki/Common-mode rejection ratio
Index
Eq. T1.1, 8 Fig. T1.1, 8 Eq. T1.2, 9 Eq. T1.3, 9 Fig. T1.2, 9 Eq. T1.4, 9 Eq. T1.5, 9 Fig. T1.3, 9 Eq. T1.6, 10 Fig. T1.4, 10 Fig. T1.5, 10 Fig. T1.6, 10 Eq. T1.7, 11 Fig. T1.7, 11 Eq. T1.8, 11 Eq. T1.9, 11 Eq. T2.1, 13 Eq. T2.2, 15 Eq. T2.3, 15 Fig. T2.1, 16 Fig. T2.2, 17 Eq. T2.4, 17 Eq. T2.5, 17 Eq. T2.6, 18 Eq. T3.1, 20 Fig. T3.1, 21 Eq. T3.2, 21 Eq. T3.3, 21 Eq. T3.4, 21 Eq. T3.5, 21 Eq. T3.6, 22 Fig. T3.2, 23 Eq. T3.7, 23 Eq. T3.8, 23 Fig. T3.3, 24 Eq. T3.9, 24 Eq. T3.10, 25 Eq. T3.11, 25 Eq. T3.12, 25 Fig. T4.1, 31 Eq. T4.1, 31 Fig. T4.2, 32 Eq. T4.2, 32 Eq. T4.3, 32 Eq. T4.4, 33 Eq. T4.5, 33 Eq. T4.6, 33 Fig. T4.3, 35 Fig. T4.4, 35 Eq. T4.7, 36 Fig. T4.5, 36 Fig. T4.6, 36 Eq. T4.8, 36 Eq. T4.9, 36 Fig. T4.7, 37 Eq. T4.10, 37 Eq. T4.11, 37 Fig. T5.1, 38 Fig. T5.2, 38 Eq. T5.1, 39 Eq. T5.2, 39 Eq. T5.3, 39 Eq. T5.4, 39 Eq. T5.5, 39 Eq. T5.6, 40 Eq. T5.7, 40 Eq. T5.8, 40 Eq. T5.9, 40 Eq. T5.10, 41 Eq. T5.11, 41 Eq. T5.12, 43 Eq. T6.1, 44 Eq. T6.2, 45 Eq. T6.3, 45 Fig. T6.1, 45 Fig. T6.2, 45 Eq. T6.4, 46 Eq. T6.5, 46 Eq. T6.6, 46 Fig. T6.3, 46 Eq. T6.7, 46 Eq. T6.8, 47 Eq. T6.9, 47 Eq. T6.10, 47 Fig. T6.4, 48 Eq. T6.11, 48 Eq. T6.12, 48 Eq. T6.13, 48 Eq. T6.14, 48 Eq. T6.15, 49 Eq. T6.16, 49 Eq. T6.17, 49 Eq. T6.18, 49 Eq. T6.19, 49 Fig. T6.5, 49 Eq. T6.20, 50 Eq. N1.1, 52 Eq. N1.2, 52 Eq. N1.3, 52 Fig. N1.1, 53 Eq. N1.4, 53 Eq. N1.5, 53 Eq. N1.6, 53 Eq. N1.7, 54
Index
135
Eq. N1.8, 55 Fig. N1.2, 55 Eq. N1.9, 55 Eq. N1.10, 55 Fig. N1.3, 56 Eq. N1.11, 56 Eq. N1.12, 56 Fig. N1.4, 56 Eq. N1.13, 56 Eq. N1.14, 56 Fig. N1.5, 57 Eq. N1.15, 57 Eq. N1.16, 57 Fig. N1.6, 57 Eq. N1.17, 57 Fig. N1.7, 57 Eq. N1.18, 57 Fig. N1.8, 58 Eq. N1.19, 58 Fig. N1.9, 58 Eq. N1.20, 58 Fig. N1.10, 59 Eq. N1.21, 59 Eq. N1.22, 59 Fig. N1.11, 59 Eq. N1.23, 59 Eq. N1.24, 59 Eq. N1.25, 60 Fig. N1.12, 60 Fig. N1.13, 60 Fig. N1.14, 60 Eq. N1.26, 60 Eq. N1.27, 61 Fig. A2.1, 62 Fig. A2.2, 63 Eq. A2.1, 63 Eq. A2.2, 63 Eq. A2.3, 63 Fig. A2.3, 64 Eq. A2.4, 65 Eq. A2.5, 66 Eq. A2.6, 66 Eq. A2.7, 66 Eq. A2.8, 66 Eq. A2.9, 67 Fig. A2.4, 67 Eq. A2.10, 68 Eq. A2.11, 68 Eq. A2.12, 69 Eq. A2.13, 70 Eq. A2.14, 71 Eq. A2.15, 71 Eq. A2.16, 72 Eq. A2.17, 72 Fig. A2.5, 73 Eq. A2.18, 73 Fig. A2.6, 73 Fig. A2.7, 75 Fig. E1.1, 76 Fig. E1.2, 77 Eq. E1.1, 78
Eq. E1.2, 78 Eq. E1.3, 78 Eq. E1.4, 78 Fig. E1.3, 78 Eq. E1.5, 79 Eq. E1.6, 79 Fig. E1.4, 79 Eq. E1.7, 79 Eq. E1.8, 79 Eq. E1.9, 79 Eq. E1.10, 80 Eq. E1.11, 80 Eq. E1.12, 80 Eq. E1.13, 80 Eq. E1.14, 80 Eq. A3.1, 82 Eq. A3.2, 83 Eq. A3.3, 84 Eq. A3.4, 84 Eq. A3.5, 84 Fig. A3.1, 85 Fig. A3.2, 85 Fig. A3.3, 86 Fig. A3.4, 87 Eq. A3.6, 87 Fig. A3.5, 88 Eq. A3.7, 88 Eq. A3.8, 88 Eq. A3.9, 88 Eq. A3.10, 89 Fig. T7.1, 90 Eq. T7.1, 90 Eq. T7.2, 92 Eq. T7.3, 93 Eq. T7.4, 93 Fig. A4.1, 94 Eq. A4.1, 95 Eq. A4.2, 95 Eq. A4.3, 95 Fig. A4.2, 96 Eq. A4.4, 96 Eq. A4.5, 96 Eq. A4.6, 97 Eq. A4.7, 97 Eq. A4.8, 98 Eq. A4.9, 98 Eq. T8.1, 99 Eq. T8.2, 100 Eq. T8.3, 100 Eq. T8.4, 100 Fig. T8.1, 100 Eq. T8.5, 100 Eq. T8.6, 101 Eq. T8.7, 101 Eq. T8.8, 101 Eq. T8.9, 101 Eq. T8.10, 102 Eq. T8.11, 103 Eq. T8.12, 103 Eq. T8.13, 103 Fig. T8.2, 104
Index
136
Fig. T8.3, 104 Fig. T8.4, 104 Eq. T8.14, 104 Fig. T8.5, 105 Eq. T8.15, 105 Fig. T8.6, 105 Eq. T8.16, 105 Fig. T8.7, 105 Eq. T8.17, 105 Fig. A5.1, 106 Eq. A5.1, 106 Fig. A5.2, 107 Eq. A5.2, 107 Fig. A5.3, 107 Eq. A5.3, 108 Fig. A5.4, 108 Eq. A5.4, 108 Fig. A5.5, 108 Eq. A5.5, 108 Eq. T9.1, 109 Eq. T9.2, 109 Eq. T9.3, 110 Eq. T9.4, 110 Eq. T9.5, 114 Fig. T9.1, 114 Eq. T9.6, 115 Eq. T9.7, 115 Eq. T9.8, 115 Eq. T9.9, 115 Eq. T9.10, 116 Eq. T9.11, 116 Eq. T9.12, 116 Fig. T9.2, 117 Eq. T9.13, 117 Fig. T9.3, 117 Eq. T9.14, 118 Eq. T9.15, 118 Eq. T9.16, 118 Eq. T9.17, 118 Eq. T9.18, 118 Eq. T9.19, 118 Eq. T9.20, 119 Fig. T9.4, 119 Eq. T9.21, 119 Eq. T9.22, 119 Eq. T9.23, 119 Fig. T9.5, 120 Eq. T9.24, 120 Eq. T9.25, 120 Eq. T9.26, 120 Fig. E2.1, 122 Fig. E2.2, 123 Eq. E2.1, 123 Fig. E2.3, 124 Eq. E2.2, 124 Fig. E2.4, 124 Eq. E2.3, 124 Eq. E2.4, 124 Eq. T10.1, 125 Eq. T10.2, 125 Eq. T10.3, 126
Eq. T10.4, 126 Eq. T10.5, 126

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prof.ssa S. Rocchi ing. M.

Teaching guide: basic electronics

76 76 77 77 77 78 78 79 79 80 81 82 82 82 83 83 84 85 85 86 86 86 86 87 87 88 88 89 89 90 90 91 91 92 92 93 93 94 94 94 95 96 96 96 96 97 97 98 98 99 99 99 99 100 100 100 100

Teaching guide: basic electronics Anno 2007-08

Istruzioni per lutilizzo dellipertesto

Link a equazioni, gure, lavagne, parti e riferimenti bibliograci

Istruzioni per lutilizzo dellipertesto

Nella versione PDF i commenti iniziano con il simbolo

e sono scritti in corsivo.

Part T1: Notes on Electricity

E (Electric Field), V (Electrostatic Potential), J (Current Density), (Conductivity), (Resistivity).

Part T2: Semiconductor physics

Part T3: Diode as non-linear device

Part A1: Diode applications

Part T4: MOSFET device

Part T5: Bipolar Junction Transistor (BJT)

Part T6: MOSFET and BJT as non-linear devices

Part N1: Basics of Electrical Theory

Notes on two-port networks (Quadripoles). The Miller theorem.

Part A2: Single stage MOSFET and BJT congurations

Part E1: Esempio di progettazione di un amplicatore CS

Esempio di progettazione con MOSFET.

Part A3: Basic MOSFETbased congurations

MOSFET: diode conguration, current mirror, dierential amplier.

Part T7: Ampliers frequency response

Bandwidth, pole-dominant approximation, time-constant method.

Part A4: Timeconstant method application

Example of the time-constant method.

Part T8: Ideal voltage amplier and feedback

Part A5: Ideal voltage amplier and feedback applications

Ideal voltage amplier and feedback applications

Part T9: Stability analysis of feedback ampliers

Stability analysis: gain and phase margins, compensation techniques.

Part E2: Compensation examples

Part T10: Techniques used to analyze feedback ampliers

Rosenstark and Blackman techniques.

Part E3: Examples of the Rosenstark and Blackman formulas

Examples of the Rosenstark and Blackman formulas.

Part E4: Esercizi su amplicatori, retroazione e compensazione

Esercizi su amplicatori, retroazione e compensazione.

Gauss law in vacuum

where the electrical permittivity in vacuum (0 ) is equal to 0 = 8.85412 1012

Example (Fig. T1.1)

Joint constant between dimensions of Sclosed E and Q

C2 [Charge] [F orce] [Surf ace] = [0 ] = [Charge] [0 ] [N m2 ]

for homogeneous and innite (i.e., unbounded) media

Electric displacement eld (or electric ux density) D

In most ordinary materials D = E

path connecting points P and O.

E is the work (the amount of energy) transferred by E along an arbitrary

Electrostatic potential property (I)

O VP O = VOP Figure T1.2

Electrostatic potential property (II)

if q = qel = 1.6 1019 C q 1 V = 1 eV = 1.6 1019 J (1 eV is a very small amount of energy) P

Energy conservation law

V (x) = E x + CON ST U (x) = q V (x) U (0) = 0

Example: potential energy barrier

U (x) P EC x0 Figure T1.5 x

Metal conductivity schematic picture

In the steady state (T1.7) v d = E = vd E [] =

where v d is the drift velocity. m2 V s . One dimensional example (Fig. T1.7)

q N vd I = A LA qN qN = we have: setting = LA vol (T1.9)

Band Theory of Solids

Insulators, semiconductors and conductors