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).+( '&0( 4+-0$3*+%&-$&3$-0$ 4+- 2& )0$))& *%+8&8(2(01

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 Struttura fondamentale della gerarchia
5'")"#$%'*+%*6'60"%)
della memoria
Al4(&5"-*5-"-&6-((+&6)*.+07+&6+((+&8!9&
crescere della distanza dalla CPU
6)3)02)*5-&)(&5#*.#:&3+&+23-0.+&(+&
cresce anche il costo e la capacità di
5+;+5).<&6)&3-3#")77+7)#0-
memorizzazione.

La gerarchia può
consistere di più livelli, ma
in ogni istante di tempo i
dati sono copiati solamente
tra ciascuna coppia di
livelli adiacenti, per cui ci
si può concentrare su due
soli livelli.

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&44$))(8(2$>(->3+'+>'(%$00+>0%&3(0$>(-'(%(,,(B>
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!"##$%&"'()'*+,-#+,$'($#$**$,$',.)."#$+,
),$',/+/0),
Corrispondenza tra indirizzi in
memoria e in cache
I blocchi di memoria con indirizzo
Problema: ad una posizione in
00001, 01001, 10001, 11001
cache hanno
sono gli
associate
ultimi logpiù
2 8=3 parole di
bit uguali
memoria.
→ mappati nello stesso blocco
Come è possibile sapere se il dato
presente nella cache corrisponde
effetivamente alla parola richiesta?

!"#$%&'&&(")*+',-%*'-)./")&/"%
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! D 8(0 *(< )(7-(E(4&0(#( '$22K(-'(%(,,+ '$2 '&0+ %(4:($)0+ %&**%$)$-0&-+ (2 H&7

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J)06)")77#&6-(&,(#55#L&3#62(#&J023-"#&6)&,(#55@)&0-((+&5+5@-L

1200 22
= 75 𝑚𝑜𝑑 64
16

𝐼𝑛𝑑𝑖𝑟𝑖𝑧𝑧𝑜 𝑑𝑒𝑙 𝑑𝑎𝑡𝑜 𝑖𝑛 𝑏𝑦𝑡𝑒

𝑖𝑛𝑑𝑖𝑟𝑖𝑧𝑧𝑜 𝑑𝑒𝑙 𝑏𝑙𝑜𝑐𝑐𝑜 = = 75
𝐵𝑦𝑡𝑒 𝑝𝑒𝑟 𝑏𝑙𝑜𝑐𝑐𝑜

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E%$/.$-,&>'(>3())B

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431)4+.F,2<)(+)4$S,T09,
= ,(#55@)&6)&H"#**+&6)3-0*)#0-&5#3;#".+0#&3+HH)#")&3)**&;-0+(.[\D&
< ? ,+1+$$)#'"%B'>%0+/B"%B+#%0#)$.+#'#+%'5%65"11"%
= *-&(+&6)3-0*)#0-&6-(&,(#55#&A ."#;;#&H"#**+&")*;-..#&+((+&6)3-0*)#0-&6-((+&
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+55-**#&+((+&5+5@-

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 A)#$'*E'&4)EE0#%)&%F'

! H,E4311-+,)<<)#.$'$'.+,)44),1)1-$,23'3,#);;#&<<).+,+',2$.,

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3;'+,2$.,#);;#&<<),6 E4311-+,

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1)1-$,B)11$223,*+#$..3,.#)7+.$,+'*+1$C,$,<&3W,$22$#$,32<+.).3,+',
&',E43113,%&)4&'%&$,)<<)#.$'$'.$,),%&$4,2$.,

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+',&',E43113,*$4,2$.,X '$1$22)#+3,13'>#3'.)#$,+',<)#)44$43,+,.); *+,
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 A)#$'*J4K)D*G'&*!EE0#%)&%F'*
Cache set-associativa a 4 vie
L’implementazione richiede tag indice offset
– 4 comparatori 31 30 12 11 10 9 8 3210

– 1 multiplexer 4-to-1 22 8

Tramite l’indice Index

0
V Tag Data V Tag Data V Tag Data V Tag Data

viene selezionato 1
2
uno dei 256 set 253
254
I 4 tag nel set 255
22 32
sono confrontati in
parallelo
Il blocco viene
selezionato sulla
base del risultato
4-to-1 multiplexor
dei confronti
Hit Data

- Valeria Cardellini, A.A. 2007/08 41

!"#$%&'&&(")*+',-%*'-)./")&/"%
 GF)8&),,%*+'--)*#)#$'*E'&*)EE0#%)&%F'*

! 8)1-$,6UV)M,2$.,)2231+).+:$,),13'>#3'.3,13',1)1-$,)*,)11$223,
*+#$..39,
= > 5#3;+"+.#")&)0?-5-&6)&P&
= 2(.-")#"-&").+"6#&$#"0).#&6+(&32(.);(-a-"&
= )(&,(#55#&A 6)*;#0),)(-&6#;#&(+&6-5)*)#0-&I).CM)**&-&(+&*-(-7)#0-&6-(&*-.&

! H',&'),1)1-$,)*,)11$223,*+#$..3S,+4,E43113,X *+2<3'+E+4$,<#+7),
*$44),*$1+2+3'$,Y+.5T+22,

!"#$%&'&&(")*+',-%*'-)./")&/"%
 A08<"08&0*&")*-'*&'#8%#$'*+%*%8+%"%==)6'8&0*
Confronto tra le tecniche di indirizzamento
Set associative:
Direct mapped: il blocco 12 può
Fully associative:
il blocco 12 può essere essere disposto
il blocco 12 può
disposto solo sul blocco ovunque nel set 0
essere disposto
4 (12 mod 8) (12 mod 4)
ovunque
Blocco 01234567 01234567
Blocco 0 1 2 3 4 5 6 7 Blocco

Set Set Set Set

0 1 2 3
ricerca
ricerca

ricerca

Memoria di livello inferiore

Blocco 00000000001111111111222222222233
01234567890123456789012345678901
F. Tortorella © 2007
Calcolatori Elettronici II
Università degli Studi
Cache - 21 di Cassino

!"#$%&'&&(")*+',-%*'-)./")&/"%
 ;%6'8E%08'*+'-*&), '*)EE0#%)&%F%&:
Dimensione del tag e associatività
• Aumentando il grado di associatività
– Aumenta il numero dei comparatori ed il numero di bit per il tag
• Esempio
– Cache con 4K blocchi, blocco di 4 parole, indirizzo a 32 bit
– r = log2(4*4)=4 → n-r = (32-4) = 28 bit per tag e indice
– Cache ad indirizzamento diretto
• s = log2(4K) = 12
• Bit di tag totali = (28-12)*4K = 64K
– Cache set-associativa a 2 vie
• s = log2(4K/2) = 11
• Bit di tag totali = (28-11)*2*2K = 68K
– Cache set-associativa a 4 vie
• s = log2(4K/4) = 10
• Bit di tag totali = (28-10)*4*1K = 72K
– Cache completamente associativa
• s=0
• Bit di tag totali = 28*4K*1 = 112K
AAC - Valeria Cardellini, A.A. 2007/08 42

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4 decisioni da
prendere
CPU CACHE MEM

1. Dove posizionare un blocco ?

Tecnica di indirizzamento
2. Come reperire un blocco ?

3. Quale blocco sostituire

in corrispondenza di un miss ? Algoritmo di sostituzione

4. Come gestire un’operazione

di scrittura ? Strategia di aggiornamento

F. Tortorella © 2007
Calcolatori Elettronici II
Università degli Studi
Cache - 2
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4 decisioni da
prendere
CPU CACHE MEM

1. Dove posizionare un blocco ?

Tecnica di indirizzamento
2. Come reperire un blocco ?

3. Quale blocco sostituire

in corrispondenza di un miss ? Algoritmo di sostituzione

4. Come gestire un’operazione

di scrittura ? Strategia di aggiornamento

F. Tortorella © 2007
Calcolatori Elettronici II
Università degli Studi
Cache - 2
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Cache L2
Processor DRAM
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