FROM 10 cc + Boe DATE TIME: ‘SUBJECT ATTACHMENT BODY Laura Fleming 1013011997 33:26:46 (Cagunarintel EM issues Craig and | met with Ed Davis and Vincent Pinto. Ed is engineering manager for Livermore and Vincent is designer of graphics subsystem. This meeting ‘was about EMI issues - where we stand and what to do next. (NEC sales guy) in lobby - he says is now there for RDRAM (but unforcasted so they are having a hard time delivering better than the 4 week leadtime). Price is 10.50 for '533MHz components, Note: Defensive shialds up! This meeting was active listening so | asked {questions to get Inte's real feelings on the table. In general, Ed wants to see us succeed and wants to work to resolve issues. Ed's issues 1. Cirrus Laguna PLL design is poor - too much ground bounce. (I talked to Cirrus this morning, and they blame Rambus for spilling the beans to Intel on this issue. They say that Intel has now latched onto it as an excuse.) 2. Rambus layout guidelines are too constraining. Intel would like to see ‘a vector sat of layout options. Cutting the vec/gnd pianes are a bad idea (we told them that before), but ail other signal routing on Intel motherboards is on layer 4, and they want the ground plane next to that layer for good signal quality for the rest of the board. He also mentioned that we were very involved with Cirrus on layout issues from the beginning, but EMI issues seemed to be left unl the end when it was too late to fix them. 3. OPSD EM| issues getting steadily worse. Their baseline EMI is creeping Up steadly. They are starting to use SSC across the board to help. They ‘would like fo see @ spec from Rambus that says we will not add more than X to the baseline. Just squeaking under the FCC limit by tweaking the board in trial and error seems too risky and prone to error to Intel. Each time they do a board spin it costs them $250K for the board, full qualvalidation and paperwork. Even if they change the silkscreen, their ‘customers then have to go through a process of obsoleting the old version (throwing away remaining inventory) and doing a full qualification of the ‘new board. Costs money and more importantly Time to Market. Intel said that they have taken Cirrus off of two other boards due to the ‘above issues. They said they asked Cirrus to fx the 5465 PLL and Cirrus ‘said no, they were going to focus on the next generation part (54687). Intel (Ed) took that as a sign that they did not want the business. Cirrus sales guy said today that this was not the case. Other intel contact, program managers and materials engineers are teling Cirrus different things. “JohnV/Mikek, let's get together to strategize on how we work ‘with Cirus on this issue. (Note, other issues contributed to this ecision too. Cirrus shw drivers delivered on 10/20 did not improve performance as much as expected. They are the poorest performing AGP 30 chip ofall the Intel suppliers.) Ed also mentioned that Cirus should consider using a technique developed bby Mel Base at Intel called Digital Waveform systhesis instead of a PLL. ‘Supposedly patented by Intel aver 15 yrs. ago, now a more viable technology since process geometries have shrunk. **Donnelly"* have we ever looked at this technique for clock synthesis? R 214404 (OUTSIDE COUNSEL ONLY cx0965-001Booy Ed said he would like a meeting where we summarize the issues to date and talk about options for fixing the problems. | suggested that Rambus/Intel have an engineering meeting and asked if he had a problem having Cirrus there. He said that a three way meeting would be ok if Cirus is really willing to work the issue. ‘We need to scramble to see if we can win back the boards in the short term highly dependent on Cirus.. For the longterm, we need to provide a ‘broposal to Intel on how we close this issue. Right now Rambus has a black ‘eye at OPSD on EMI. This will come back to haunt us the next time Cirrus is up for a design win or even S3. | am ultimately concemed about Direct, ‘although Ed agreed that we have done our homework there and are working with the right folks (Don Weiss). Ed said he is going to fork out $2800/day to Howard (Howie) Johnson in ‘Washington to consult on how Rambus could provide a loser set of layout ‘guidelines that would help us pass EMI. “"Richard"* Ed said he was going {0 call you about working the issue. He asked if Rambus might be wiling, to pick up the tab for Howie's consulting services. | said | would do the following: 1. follow up with Cirrus, assess their level of committment and what resources they are willing to bring to bear on the problem. 2. provide a proposal to Intel on what resources Rambus could bring to the problem. | think that we should offer to foot the bil for just the board fab (about 10k?), and gather data that proves we pass FCC requirements, but ‘not pick up the tab on the consulting services. “"Richard, please provide {Your opinion on what we might gain by employing Howard Johnson. Other notes: '517MHz and 773MHz spikes are the major concern. A walking h pattern is used to drive the LCD when measuring EMI. This pattern is supposedly worst ‘case as it loggles each pixel on the screen. “Rich, do you have any familiarity with this test? Opinions and suggestions welcome. Regards, Laura ‘Rambus Confidential information may be contained in this email"* Laura Fleming Rambus Inc. fleming@rambus.com (650-903-4757 test R 21440; oursice BouNSS ony ‘x0965-002