VERILOG IMPLIMENTATION OF AN ARM COMPATABLE CORE

By, M.M.RAJASEKHARA REDDY M.SRINIVAS G.VENKATESH M.SHYAM MOHAN K.VEERREDDY

(08A91A0469) (08A91A0462) (08A91A0429) (08A91A0465) (08A91A0455)

Under the guidance of P.BUJJIBABU, M.Tech. Asst.Professor

Project Description
Our project was to design a Reduced Instruction Set Computer (RISC) using a Verilog hardware description language. DESIGN SPECIFICATIONS: 1. Processor would be a 32-bit processor. 2. Processor would follow a Von Neuman style. 3. In a register style instruction there would be one write register and two read registers.

SELECTION OF ISA
The ARM architecture has been designed to allow very small, yet high- performance implementations, and small implementations allow devices with very low power consumption. FEATURES: 1. A large uniform register file A load/store architecture 2. Instruction fields are Uniform and fixed-length instruction fields, to simplify instruction decode. 3. Control over both Arithmetic Logic Unit (ALU) and shifter in every data- processing instruction 4. Load and Store multiple to maximize data throughput

Pipe Line Stages

Features of our ARM

Our ARM supports six modes of operation: 1. User mode (usr): the normal program execution state 2. FIQ mode (fiq): designed to support a data transfer or channel process 3. IRQ mode (irq): used for general-purpose interrupt handling 4. Supervisor mode (svc): a protected mode for the operating system

Registers Banks

Exceptions

Summary of the ARM7 instruction set

Branch and Branch with link (B, BL)

Branch instructions contain a signed 2's complement 24 bit offset The instruction can therefore specify a branch of +/- 32Mbytes Branch with Link (BL) writes the old PC into the link register (R14) of the current bank

Data processing
The first operand is always a register (Rn). The second operand may be a shifted register (Rm) s bit indicate whether to update status flags in PC register or not. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and update flags so S bit is 1.

Shift
When the second operand is specified to be a shifted register, the Shift field in the instruction controls the operation of the barrel shifter. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15).

Some more data processing Instructions

Immediate operand rotates Using R15 as an operand Q, TST, CMP & CMN opcodes

PSR Transfer (MRS, MSR)

Operand restrictions

Multiply and Multiply-Accumulate (MUL, MLA)

Single data transfer (LDR, STR)

Block data transfer (LDM, STM)

Register list - Address Alignment

Software interrupt (SWI)

Processor Block Diagram