Switch Level Modeling & Delays

ABHISHEK SAINI IITR

Switch Level Modeling

Switch modeling elements:
MOS switches
nmos and pmos

Instantiation of NMOS and PMOS Switches

Logic Table for NMOS and PMOS Switches

CMOS Switches
Keyword: cmos Symbol: Instantiation:

Equivalent to the above method

Bi-directional Switches
Three types of bidirectional switches are in verilog which are defined by the following keywords:
tran tranif0 tranif1

Bidirectional. Symbol

Bidirectional.
Instantiation of bidirectional switches

Bidirectional switches are typically used to provide isolation between busses or signals.

Power and Ground

Keywords: supply1 and supply0 supply1 is equivalent to Vdd and places logic 1 on a net. supply0 is equivalent to ground and places logic 0 on a net. Example:

Resistive Switches
These switches have higher sourceto-drain impedance than regular switches and reduces the strength of the signals passing through them. These switches are declared with keywords that have an r prefixed to the corresponding keyword for the regular switches.

Contd..
Keywords for resistive switches:

Delay Specification on Switches

MOS and CMOS Switches

Contd..
Bidirectional pass switches:

Example 1
CMOS NOR Gate

Verilog Code

Example 2
2-to-1 Multiplexer

Verilog Code

Timing and Delays

Functional Verification Vs Timing Verification Increasingly important as circuits have become smaller and faster. Check timing Perform a timing simulation Perform a Static timing verification Designers first do a pure functional verification and then verify timing separately with a static timing verification tool.

Timing Simulation
Delay models: Three types of delay models used in Verilog
Distributed delay model Lumped Delay model Pin-to-pin (path) Delay model

Distributed Delay Model

Distributed delays are specified on a per element basis. Distributed delays
modeled by assigning delay values -in gate level modeling modeled by assigning delays in the continuous assignmentin data flow modeling

Example

Lumped Delays
Lumped delays are specified on a per module basis. they can be specified as a single delay on the output of the gate of the module. The cumulative delay of all paths is lumped at one location. They are easy to model compared with distributed delays.

Example

Verilog Code

Pin-to-Pin Delays
Delays are assigned individually to paths from each input to each output. Delays can be separately specified for each input/output path

Example

Path Delays
Pin-to-Pin delays are named as path delays. The delay values got directly from Data Books for standard elements. For larger Digital Circuits, a low level circuit simulator like SPICE may be used. Designer needs to know the I/O pins of the module rather than the internals of the module so easier to model, even though it is very detailed

Specify Blocks
Path delays are assigned in Verilog within the keyword specify and endspecify. The statements within these keywords constitute a specify block. Specify blocks contain the statements to do the following: Assign pin-to-pin timing delays across module paths Set up timing checks in the circuits Define specparam constants

Example

Contd.
Inside specify blocks Parallel connections Full connections Conditional Connections

Parallel Connection

A parallel connection is specified by symbol => and used as shown below: (<source_field> => <destination_field>) = <delay_value>; In parallel connection each bit in the source field is connects to its corresponding bit in the destination field.

Contd.

Full Connection
Here every bit in source field connected to every bit of the destination. A full connection is denoted by *>

Contd

specparam
specparam values are often used to store values for non-simulation tools, such as delay calculators, synthesis tools and layout estimators. Example:

Conditional Path delays

Also called as state dependent path delays (SDPD). Example:

Delay Specifications
Pin-to-Pin timing can also be expressed in more detail by specifying rise, fall and turnoff delays. One, two, three , six or twelve delay value can be specified for any path. Four, five, seven, eight, nine, ten or eleven delay value specification is illegal. Order in which delays are specified must be strictly followed.

Example

Min, max and typical delays(min:typ:max)

Specparam t_rise = 8:9:10, t_fall = 12:13:14, t_turnoff = 10:11:12; (clk=> q) = (t_rise, t_fall, t_turnoff); This can be repeated for one, three, six or twelve delays for each one of them, three values representing the min, typ, max in order. Selection can be done at command line with +mindelays, +typdelays, +maxdelays in VerilogXL and similarly in other verilog versions

Handling x Transitions
Verilog uses pessimistic method to compute delays for transitions to the x state. This approach dictates that if x transition delays are not explicitly specified.
Transition from x to a known state should take maximum possible time Transition from a known state to x should take minimum possible time

Example

Computation result

Timing Checks
Path delays are specified to get greater timing accuracy than what one gets by specifying gate delays. Setting constraints to check if these timings are violated during simulation. Timing critical, high-speed sequential circuits like microprocessors are to be verified. $setup, $hold and $width are commonly used timing checks and they are inside the specify block

$setup and $hold Checks

$setup task
Syntax:
$setup( data event, reference event, limit) Data event: Signal that is monitored for violation. Reference event: Signal that establishes a reference for monitoring the data_event signal Limit: Minimum time required for setup of data event.

Example
Violation is reported if

$hold task
Syntax:
$hold(reference event, data event, limit) Data event: Signal that is monitored for violation. Reference event: Signal that establishes a reference for monitoring the data_event signal Limit: Minimum time required for hold data event.

Example
Violation is reported if

$width Check
$width is used to check that the width of the signal meets minimum width requirement. Syntax: $width(reference_event, limit) reference_event: edge-triggered event

Limit : minimum width of pulse

Delay Back Annotation

 Standard Delay File (SDF) RTL, Synthesis (pre-layout time estimates), layout, post-layout time estimates. The post-layout time estimates are sent back and again run on the synthesis net list to check for constraint satisfaction. SDF is used for back annotation