Matakuliah Tahun Versi

: T0324 / Arsitektur dan Organisasi Komputer : 2005 :1

Pertemuan 15 Organisasi I/O: I

Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu :

Mahasiswa dapat membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )

Chapter 4.
Input/Output Organization: I

Processor

Memory

Bus

I/O device 1

I/O de vice n

Figure 4.1. A single-bus structure.

4

Address lines Bus Data lines Control lines

Address decoder

Control circuits

Data and status registers

I/O interf ace

Input dev ice

Figure 4.2. I/O interface for an input device.

ST ATUS

DIRQ KIRQ SOUT

SIN

CONTR OL 7 6 5 4

DEN 3

KEN 2 1 0

Figure 4.3. Registers in kyboard and display interf e aces.

WAITK

WAITD

Move TestBit Branc h=0 Move TestBit Branch=0 Move Move Compare Branc 0 h Move Call

#LINE,R0 #0,ST TUS A WAITK DA TAIN,R1 #1,ST TUS A WAITD R1,DATA OUT R1,(R0)+ #$0D,R1 WAITK #$0A,DA TA OUT PROCESS

Initialize memory pointer. Test SIN. Wait for character to be entered. Read character. Test SOUT. Wait for displa to becomeready y . Send characterto display . Store characterand adv ance pointer. Chec if Carriage Return. k If not, get anothercharacter. Otherwise, send Line Feed. Call a subroutineto process the input line.

Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the disp

Program 1 COMPUTE routine

Program 2 PRINT routine

1 2 Interrupt occurs here

i i +1

Figure 4.5. Transfer of control through the use of interrupts.

Vdd Processor R I NTR INTR INTR1 INTR2 INTR n

Figure 4.6.An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.

Processor

INTR1 Dev ice 1 INTA1 Dev ice 2

I NTRp Dev ice p INTA p

Priority arbitration circuit

Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

10

Processor

I NT R

INTA

Dev ice 1

Dev ice 2

Dev icen

(a) Daisy chain

I NT R 1

Processor

INTA1 INTR p

Dev ice

Dev ice

INTA p Priority arbitration circuit

Dev ice

Dev ice

(b) Arrangement of priority groups

Fi gure 4.8. Interrupt pri ori ty schem es.

11

Main Program

Move Clear BitSet BitSet . . .

READ

#LINE,PNTR EOL #2,CONTR OL #9,PS

Initialize buffer pointer. Clear end-of-line indicator. Enable keyboard interrupts. Set in terrupt-enable in the PS. bit

In terrupt-serviceroutine MoveMultiple R0-R1, (SP) Move PNTR,R0 MoveByte DATAIN,R1 MoveByte R1,(R0)+ Move R0,PNTR CompareByte #$0D,R1 Branc 0 h RTRN Move #1,EOL BitClear #2,CONTR OL MoveMultiple (SP)+,R0-R1 Return-from-in terrupt Sa e registersR0 and R1 on stac v k. Load addresspointer. Get input characterand store it in memory . Updatepointer. Chec if CarriageReturn. k Indicate end of line. Disable keyb oard interrupts. Restoreregisters R0 and R1.

RTRN

Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.

12

OSINIT

OSSER VICES SCHEDULER

Set in terrupt v ectors: Time-slice clo c k SCHEDULER Soft w are in terrupt OSSER VICES Keyb oard in terrupts IOData . . . Examine stac k to determine requested op eration. Call appropriate routine. Sa v e program state. Select a runnable pro cess. Restore sa v ed con text of new pro cess. Push new v alues for PS and PC on stac k. Return from in terrupt.
(a) OS initialization, services, and scheduler

IOINIT

Set pro cess status to Blo c ked. Initialize memory buffer address p oin ter and coun ter. Call device driv er to initialize device and enable in terrupts in the device in terface. Return from subroutine. Poll devices to determine source of in terrupt. Call appropriate driv er. If END = 1, then set pro cess status to Runnable. Return from in terrupt.
(b) I/O routines

IOD A T A

KBDINIT KBDD A T A

Enable in terrupts. Return from subroutine. Chec k device status. If ready , then transfer c haracter. If c haracter = CR, then { set END else set END = 0. Return from subroutine.
(c) Keyboard driver

= 1; Disable

in terrupts }

Figure 4.10. A few operating system routines.

13

7 I

6 F

4 M4

3 M3

2 M2

1 M1

0 M0

Figure 4.11. Low-order byte of the ARM processor status register.

14

R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15

R3 R4 R5 R6 R7 R8_f iq R9_f iq R10_f iq R11_f iq R12_f iq R13_f iq R14_f iq R15

R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15

R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13-sv c R14_sv c R15

R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15

R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15

Processor status regi ster

CPSR CPSR SPSR_f iq CPSR SPSR_irq CPSR SPSR_sv c CPSR SPSR_abt CPSR SPSR_und

Fi gure 4.12. Accessi bl e regi sters i n di fferent m odes of the ARM processor.

15

Main

program

MO V STR ADR LDRB ORR STRB MO V MSR . . .

IR Q READ In terrupt-service STMFD ADR LDRB LDR STRB STR CMPB LDMNEFD SUBNES LDRB AND STRB MO V STR LDMFD SUBS

R0,#0 R0,EOL R1,D A T AIN R0,[R1,#3] R0,R0,#4 R0,[R1,#3] R0,#&50 CPSR,R0

routine R13!, { R0 R2,R14 R1,DATAIN R0,[R1] R2,PNTR R0,[R2],#1 R2,PNTR R0,#&0D R13!, { R0 R2,R14 PC,R14 irq,#4 R0,[R1,#3] R0,R0,#&FB R0,[R1,#3] R0,#1 R0,EOL R13!, { R0-R2,R14 } PC,R14 irq,#4 irq }

Clear EOL flag. Load address of Register D A T AIN. register. Get contents of CONTROL Set bit KEN in register CONTR OL to enable k eyb oard in terrupts. Enable IR Q in terrupts in pro cessor and switc h to user mo de.

irq }

Sa v e R0, R1, and R14 irq on the stack. Load address of register D A T AIN. Get input character. Load pointer v alue. Store character and increment pointer. Up date p oin ter v alue in the memory . Chec k if Carriage Return. If not, restore registers and return. Otherwise get CONTROL register. Clear bit KEN to disable k eyb oard in terrupts. Set EOL flag. Restore registers and return.

Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

16

15 T

13 S

10

4 X

3 N

2 Z

1 V

0 C

Trace Superv isor Interrupt Priority

Condition Codes

Figure 4.14. Processor status gister in the 68000 processor re .

17

Main program MOVE.L CLR ORI.B MOVE . . . READ MOVEM.L MOVEA.L MOVE.B MOVE.B MOVE.L CMPI.B BNE MOVE ANDI.B MOVEM.L RTE #LINE,PNTR EOL #4,CONTR OL #$100,SR Initialize buffer pointer. Clear end-of-line indicator. Set bit KEN. Setprocessorpriority to 1.

In terrupt-serviceroutine A0/D0, (A7) PNTR,A0 DATAIN,D0 D0,(A0)+ A0,PNTR #$0D,D0 RTRN #1,EOL #$FB,CONTR OL (A7)+,A0/D0 Save registers D0 on stac A0, k. Load addresspointer. Get input character. Store it in memory buffer. Updatepointer. Chec if CarriageReturn. k Indicateend of line. Clear bit KEN. Restore registersD0, A0.

RTRN

Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

18

Figure 4.16. Part of the Pentium's processor status register.

19

Main program MOV MOV OR STI . . . READ PUSH PUSH MOV MOV MOV INC CMP JNE MOV X OR MOV POP POP IRET EOL,0 BL,4 CONTROL,BL

Set KEN to enable keyb oard in terrupts. Set in terruptflag in processor register.

In terrupt-serviceroutine EAX EBX EAX,PNTR BL,DATAIN [EAX],BL DWORDPTR[EAX] BL,0DH RTRN BL,4 CONTROL,BL EOL,1 EBX EAX Sa e registerEAX on stac v k. Sa e registerEBX on stac v k. Load addresspointer. Get input character. Storecharacter. Incremen PNTR. t Chec if characteris CR. k

RTRN

Clear bit KEN. Set EOL flag. Restore register EBX. Restore register EAX.

Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.

20

31 Status and control

30

IRQ IE

Done R/ W

Starting address

Word count

Figure 4.18. Registers in a DMA interf ace.

21

Disk

Disk

Netw ork Interf ce a

Figure 4.19. Use of DMA controllers in a computer system.

Figure 4.19. Use of DMA controllers in a computer system.

22

B BSY BR Processor DMA controller 1 DMA controller 2

BG1

BG2

Figure 4.20. A simple arrangement for b us arbitration using a daisy chain.

23

Time BR

BG1

BG2

B BSY Bus master

Processor

DMA controller 2

Processor

Figure 4.21. Sequence of signals during transfer of b us mastership for the deices in Figure 4.20. v

Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.

24

O.C.

1 Interf ace circuit f or dev ice A

Figure 4.22. A distributed arbitration scheme.

25

Matakuliah Tahun Versi

: T0324 / Arsitektur dan Organisasi Komputer : 2005 :1

Pertemuan 16 Organisasi I/O: II

26

Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu :

Membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )

27

Chapter 4.
Input/Output Organization: II

28

Time Bus clock

Address and command

Data

t0

t1 Bus cy cle

t2

Figure 4.23. Timing of an input transfer on a synchronous bus.

29

Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.

30

31

Data

t0

t1

t2 Bus cy cle

t3

t4

t5

Figure 4.26. Handshake control of data transfer during an input operation.

32

t0

t1

t2 Bus cy cle

t3

t4

t5

Figure 4.27. Handshake control of data transfer during an output operation.

33

Data Address R/W Master -ready Sla ve-ready Input interface DATAIN SIN Valid Data

Processor

Encoder and debouncing circuit

Key board switches

Figure 4.28. Keyboard to processor connection.

34

D0

Q0

D0

SIN Slaveready Status f lag 1 Readstatus

Valid

Readdata

R/ W Master ready A31 Address decoder A1 A0

Fi gure 4.29. Input i nterf ace ci rcui t.

35

36

DATAOUT Processor CPU R/W Masteready Slave-ready Output interface Idle SOUT Valid Printer

Figure 4.31. Printer to processor connection.

37

38

D7 D1 D0

Bus D A T AIN

P A7

P A0 SIN Input status CA PB7 D A TA OUT PB0 SOUT Handshak e control CB1 CB2

Sla v eReady

Master Ready R/ W A31 Address decoder A2 A1 A0 RS1 RS0 My-address

Figure 4.33. Combined input/output interface circuit. 39

D ATAOUT

Data Direction Re gister

My -address RS2 RS1 RS0 R/ W Ready Accept INTR Status and control C1 C2

Re gister select

Fi gure 4.34. A general 8-bi t paral l el i nterf ace.

40

D A T A OUT D7 D7 Q7 Printer data D0 D0 SOUT Read status Load data D1 D0 Q1 Q0 Handshak e control Idle V alid

R/ W Sla v eready A31 Address decoder A1 A0 Clock My-address Respond Go=1 My-address T iming Logic Go

Idle

Figure 4.35. A parallel point interface for the bus of Figure 4.25, with a state-diagram for the timing logic.

41

Time 1 2 3

Clock

Address

R/W

Data

Go

Slave-ready

Figure 4.36. Timing for the output interf in Figure 4.35. ace
42

RS1 RS0 R/W Ready Accept Status and control Recei ing clock v Transmission clock Chip and register select Output shif t re gister Serial output

I NTR

Fi gure 4.37. A seri al i nterf ace.

43

Processor

Main memory

Processor b us Bridge PCI b us

Additional memory

SCSI controller SCSI b us

Ethernet interf ace

USB controller

ISA interf ace IDE disk

V ideo
Disk controller CD-R OM controller CDR OM

Disk 1

Disk 2

K eyboard

Game

Figure 4.38. An example of a computer system using different interface standards.

44

Disk

Printer

Ethernet interface

Figure 4.39. Use of a PCI b a computer system. us in

45

46

47

Targets e xamine ID DB 2

DB 5

DB 6

BSY

SEL

Free

Arbitration

Selection

Figure 4.42. Arbitration and selection on the SCSI bus. Device 6 wins arbitration and selects device2.

48

Host computer Root hub

Hub

Hub

Hub

I/O de vice

I/O de vice

I/O de vice

I/O de vice

I/O de vice

I/O de vice

Figure 4.43. Universal Serial Bus tree structure.

49

Host computer Root Hub HS Hub A HS F/LS HS F/LS De vice C De vice D - High speed - Full/Lo w speed HS Hub B

Figure 4.44. Split bus operation

50

PID

PID

PID

PID

PID

PID

PID

PID

(a) Packet identifier field

Bits

8 PID

7 ADDR
(b) Token packet, IN or OUT

4 ENDP

5 CRC16

Bits

8 PID

0 to 8192 D A TA
(c) Data packet

16 CRC16

Figure 4.45. USB packet format.

51

ACK

Fi gure 4.46. An output transfer .

52

Bits

8 PID

11 Frame number
(a) SOF Packet

5 CRC5

1-ms frame S T3 D T7 D S T3 D

S - Start-of-frame pack et T n - T ok en pack et, address = D - Data pack et A - A CK pack et

(b) Frame example

Figure 4.47. USB frames.

53

BG1

BG2

BGn

BR1

BR2

BRn

Figure P4.1. A decentralized b assignment scheme. us

54

Table 4.1. Interrupt vector addresses for ARM processor Address Exception (hex) 0 Reset Mode entered

Sup ervisor

4
8 C 10 14 18 1C

Undefinedinstruction
Software interrupt Ab ort during prefetc h Abort during data Reserv ed IRQ FIQ

Undefined
Sup ervisor Abort Abort IRQ FIQ

55

Table 4.2. Address correction during return from exception.

Exception

Saved address* Desired return address PC+4 PC+4 PC+4 PC+8 PC+4 PC+4 PC PC

Return instruction

Undefined instruction Software interrupt Prefetc Abort h Data Abort

MOVS PC,R14und MOVS PC,R14svc SUBS PC,R14abt,#4 SUBS PC,R14abt,#8

IRQ
FIQ

PC+4
PC+4

PC
PC

SUBS PC,R14irq,#4
SUBS PC,R14fiq,#4

* PC is the addressof the instruction that causedthe exception. For IR Q and FIQ, it is the addressof the first instruction not executedb ecauseof the interrupt.

56

Table 4.3. Data transfer signals on the PCI bus.

Name
CLK FRAME# AD C/BE#

Function
A 33-MHz or 66-MHz clock. Sen by the initiator to indicate the duration of a t transaction. 32 address/data lines, which may be optionally increasedto 64. 4 command/b yte-enablelines (8 for a 64-bit bus).

IRD Y#, TRD Y#

DEVSEL#

Initiator-ready and T arget-readysignals.

A resp onse from the device indicating that it has recognizedits addressand is ready for a data transfer transaction. Initialization Device Select.

IDSEL#

57

Table 4.4 The SCSI bus signals. Category Data Name DB(0) DB(7) DB(P) BSY SEL C/D MSG Handshak e REQ A CK Direction transfer Other of I/O A TN RST F unction Data lines: Carry one b yte of information during the information transfer phase and iden tify device during arbitration, selection and reselection phases P arit y bit for the data bus Busy: Asserted when the bus is not free Selection: Asserted during selection and reselection Con trol/Data: Asserted during transfer of con trol information (command, status or message) Message: indicates that the information being transferred is a message Request: Asserted b y a target to request a data transfer cycle Ac kno wledge: Asserted b y the initiator when it has completed a data transfer op eration Input/Output: Asserted to indicate an input op eration (relativ e to the initiator) A tten tion: Asserted b y an initiator when it wishes to send a message to a target Reset: Causes all device con trols to disconnect from the bus and assume their start-up state

to

Phase

Information t yp e

58