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Unit-5 Sub-Microns CMOS circuit design: (14 Hours) Process Flow, Capacitors and Resistors, MOSFET Switch , Delay and adder Elements, Analog Circuits MOSFET Biasing

The difference between new and old process flow are: Minimum length of the channel, L min < 0.35 micro m in the case of sub micron CMOS process. The device isolation technique is Shallow Trench Isolation (STI) instead of local oxidation of Silicon (LOCOS). CVD or STI enables to define smalleropenings in the top of the wafer. n+ poly is employed for NMOS and p+ poly for PMOS formulation. p+ poly used in PMOS formulation results in surface device. Because of which, conduction between the source and drain is along the oxide / semi conductor interface. And not through buried channel.

Drains are lightly doped to reduce short channel effects. Silicided source / drain / gates are used to reduce parasitic resistances. Use of Silicide produces devices with significantly less parasitic series gate and source / drain resistances. However, Silicide complicates the process NMOS & PMOS are developed as surface devices and thus PMOS is not a buried channel device. In surface device, threshold voltage of the PMOS is easier to set precisely. There is no need to counter dope the channel for the purpose. It is also observed that short channel effect less severe. Surface device reduces mobility and increase in flicker noise.

Step 1: The Process starts with p type wafer or p+ wafer with p- epitaxial layer. Thin oxide and nitride are deposited. The purpose of deposition is for active areas patterning. Photo resist is deposited and patterned on its top. Exposed area of nitride is then removed. The step is shown in fig. 5.1 (a)

Step 2: Silicon areas that are exposed are etched. It is the part not covered by photo resist. Thus, shallow trenches are formed as shown in fig 5.1 (b)

Step 3: Shallow trenches formed in step 2 are filled with Chemical Vapor Oxide (CVD) (STI). The process is known as Chemical Mechanical Polishing (CMP). Thus, the top is now flat as in fig. 5.1 (c).

Step 4: Implants are used to make body of the PMOS (n well) transistors. Fig. 5.1 (d) shows the wafer after implant

Step 5: Patterning the polysilicon gates on the top of the wafer is carried out in this step. The effect of it is shown in fig. 5.1 (e).

Step 6: Light and shallow implants are used in lightly doped drain (LDD) MOSFET formulation as in fig. 5.1 (f)

Step 7: in this step, lateral oxide spacer adjacent to the gate poly is formed. Implants to heavily doped gates, sources and drains are formed. p+ poly is used in PMOS formulation. The result of the same is shown in fig. 5.1 (g).

Step 8: in this last step, silicide is deposited. It is combination of silicon and tungsten metal.

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