Yenpo Ho ; Huang, G.M.

; Peng Li

K Preethesh Shenoy 4DM08EC026

Seminar Guide:
Prima Rodrigues

Introduction
In mathematics Four interconnected things related in six ways. Consider q,v,I,. Fourth mystery element that joins the capacitor, resistor, and inductor. Proposed by Leon Chua in 1971.

Contd
2-terminal 2 device with memristive characteristics by S.Williams (2008). Replace transistors in Future comp, taking much smaller area. Radically different as it carries a memory of past.

Memristor Device Characteristics

Memristor- Charge/ Flux controlled.

Charge Controlled: Memristance, =

Flux Controlled: Memductance, =

Properties & Design Equations

Property 1
= , = 0
Device Resistance: () 2 Layers of 2 : Pure (Undoped) & Doped with Oxygen Vacancies. Voltage applied across device, electric field repels +ve charged Oxygen vacancies thus changing .

 Memory effect since device maintains its resistivity even if power goes off. Oxygen vacancies do not move themselves. Memristive device resistance:
= . + . 1

Polarity matters in Memristance.

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Property 2 For Charge controlled Memristance, memristor state controlled by charge through the cell & determines ().

= .
0 is the initial state is the memristor length is the average ion mobility is injected charges

2 .

Equation valid in the range:

- upper limit of effective charge injection - lower limit of effective charge injection.
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Property 3 is only a function of the integrated bias charge regardless of the waveform shape.

- current source.

Consider

Sinusoidal, - Square wave

By Property 2, w controlled by q. is integral of w.r.t time. Hence equal change for equal .
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Property 4
If charge injection exerted onto a memristor is a zero netcharge injection, memristor state will move back to its original position if .

= =

+ . +

. . .

. .

Where . & . is the charge injection by the positive & negative pulses.

2 = 0 i.e. original state zero net-charge injection inputs.

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Property 5 For Flux controlled Memristance, memristor state controlled by flux across the cell & determines ().

Property 6 is only a function of the integrated bias voltage regardless of the waveform shape
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Property 7 If the flux injection exerted onto a memristor is a zero net-flux injection, memristor state will move back to its original position if .

Similar to property 4. remains same regardless their waveform shapes as long as the flux injections is same.
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Property 8 0 using square wave vtg pulse and width

=

Similarly = 0 , width required is

=

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Property 9

In the voltage divider the node voltage response at node is given by = + ( )

is the voltage at node is the input flux injection is the flux accumulated at node is the flux across memristor .

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Memristor based Memory Circuit

Output Levels

logic zero : 0 < < 0.5 logic one :0.5 < < 1.0 Ideal output low: = 0 High level: = 1.0

To account for possible noise injections, a safety margin is specified for each logic output:
0<
<

< ,( =

< 1.0,( =

< 0.5) for logic zero

> 0.5) for logic one

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Write Operation
0 = 0 , and it is desirable to write logic one to the cell. Input voltage generates a square-wave pulse with magnitude + and width 1 . Pulse width 1 must be longer than the minimum required time 1 to insure the state rest inside the logic one region after write. Minimum required time 1
1 =
2 2

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 Similarly to write logic zero, the input voltage is a negative square-wave pulse . The minimum required time would be =

Pulse width 0 is at least greater than 0 .

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Read Operation
For a read, R/W switches to . 2 stages: convert stage & sense amplifier stage. Convert stage senses the memristor state and produces a voltage signal. Further amplified into a full-swing digital output by the sense amplifier. The output is produced by the voltage divider, which has equivalent form as

. +( )

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 needs properly designed to distinguish logic zero and one.

It is set so that the output level is at at half of its length .

=
+

when the memristor state is

is the reference voltage

2

A memristor state below

will result in a large resistance.

Accordingly, < . The comparator in the sense amplifier stage will signal Similarly, the fact that the memristor state being higher than would result a smaller resistance. > , and 0 would output .
2

are the logic one and zero voltage levels.

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Memristor Memory Array

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 Typical memory arrays - more words than bits in each word the array is often folded into fewer rows of more columns Each row of the memory contains words The array is physically organized as 2 by 2+ . Array has
row decoder sense amplifiers column decoder. pulse generator selector units.

The pulse generator generates read or write pattern signals.

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Conclusion

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References
Yenpo Ho ; Huang, G.M. ; Peng Li , Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories IEEE Circuits and Systems Society, Vol.58, Issue:4,page(s):724 736

The Mysterious MemristorIEEE Spectrum news, May 2008.

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