Combinational Logic Implementation

Two-level logic

Implementations of two-level logic NAND/NOR Factored forms And-or-invert gates Gate delays Hazards

Multi-level logic Time behavior Regular logic

Multiplexers Decoders PAL/PLAs ROMs

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Implementations of Two-level Logic

Sum-of-products
AND gates to form product terms (minterms) OR gate to form sum

Product-of-sums
OR gates to form sum terms (maxterms) AND gates to form product

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Two-level Logic using NAND Gates

Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate

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Two-level Logic using NAND Gates (contd)

OR gate with inverted inputs is a NAND gate
de Morgan's: A' + B' = (A B)'

Two-level NAND-NAND network

Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

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Two-level Logic using NOR Gates

Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate

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Two-level Logic using NOR Gates (contd)

AND gate with inverted inputs is a NOR gate
de Morgan's: A' B' = (A + B)'

Two-level NOR-NOR network

Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

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Two-level Logic using NAND and NOR Gates

NAND-NAND and NOR-NOR networks
de Morgan's law: written differently: (A + B)' = A' B' (A B)' = A' + B' A + B = (A' B') (A B) = (A' + B')'

In other words

OR is the same as NAND with complemented inputs AND is the same as NOR with complemented inputs NAND is the same as OR with complemented inputs NOR is the same as AND with complemented inputs
OR OR

AND

AND

NAND

NAND

NOR

NOR

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Conversion Between Forms

Convert from networks of ANDs and ORs to networks of NANDs and NORs
Introduce appropriate inversions ("bubbles")

Each introduced "bubble" must be matched by a corresponding "bubble"

Conservation of inversions Do not alter logic function

Example: AND/OR to NAND/NAND

A B C D Z A B C D NAND NAND NAND Z

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Conversion Between Forms (contd)

Example: verify equivalence of two forms
A B C D Z A B C D NAND NAND NAND Z

Z = [ (A B)' (C D)' ]'

= [ (A' + B') (C' + D') ]'

= [ (A' + B')' + (C' + D')' ] = (A B) + (C D)

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Conversion Between Forms (contd)

Example: map AND/OR network to NOR/NOR network
A B C D \A \B Z Z

A B C D

NOR

NOR
NOR Z

NOR

\C \D

NOR

Step 1
conserve "bubbles"

Step 2
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conserve "bubbles"

Conversion Between Forms (contd)

Example: verify equivalence of two forms
A B Z \C \D \A \B NOR NOR NOR Z

C
D

Z = { [ (A' + B')' + (C' + D')' ]' }'

={
= =

(A' + B') (C' + D')

(A' + B')' + (C' + D')' (A B) + (C D)

}'

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Multi-level Logic
x=ADF + AEF + BDF + BEF + CDF + CEF + G
Reduced sum-of-products form already simplified 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires)

x = (A + B + C) (D + E) F + G
Factored form not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)
A B C D E F G
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Conversion of Multi-level Logic to NAND Gates

F = A (B + C D) + B C'
original AND-OR network Level 1 C D B A B \C C D B A B \C C D \B A B \C Level 2 Level 3 Level 4

introduction and conservation of bubbles

redrawn in terms of conventional NAND gates

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Conversion of Multi-level Logic to NORs

F = A (B + C D) + B C'
original AND-OR network Level 1 C D B A B \C Level 2 Level 3 Level 4

C introduction and conservation of bubbles D B A B \C \C \D B \A \B C

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redrawn in terms of conventional NOR gates

Conversion Between Forms

Example
A (a) B C D X A (b)

B C D

original circuit A (c) B C \D F \X B C \D A

add double bubbles at inputs X F (d)

\X

distribute bubbles some mismatches

insert inverters to fix mismatches

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AND-OR-Invert Gates
AOI function: three stages of logicAND, OR, Invert
Multiple gates "packaged" as a single circuit block
logical concept A B C D AND OR Invert A B C D NAND NAND Invert possible implementation

2x2 AOI gate symbol

&

+
&

3x2 AOI gate symbol

&

+
&

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Conversion to AOI Forms

General procedure to place in AOI form
Compute complement of the function in sum-of-products form By grouping the 0s in the Karnaugh map

Example: XOR implementationA xor B = A' B + A B'

AOI form:
A

F = (A' B' + A B)'

A' B' A B & + & F

0
B 1

1
0

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Examples of using AOI gates

Example:
F = B C' + A C' + A B F' = A' B' + A' C + B' C Implemented by 2-input 3-stack AOI gate F = (A + B) (A + C') (B + C') F' = (B' + C) (A' + C) (A' + B') Implemented by 2-input 3-stack OAI gate
0 1 0 1 1

A
1 0

Example: 4-bit equality function

Z = (A0B0+A0'B0')(A1B1+A1'B1')(A2B2+A2'B2')(A3B3+A3'B3')

each implemented in a single 2x2 AOI gate

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Examples of Using AOI Gates (contd)

Example: AOI implementation of 4-bit equality function
A0 B0 & + high if A0 B0 low if A0 = B0

&
A1 B1 & &

+ NOR Z

conservation of bubbles

A2 B2

& &

if all inputs are low then Ai = Bi, i=0,...,3 output Z is high

A3 B3

& &

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Summary for Multi-level Logic

Advantages
Circuits may be smaller Gates have smaller fan-in Circuits may be faster

Disadvantages
More difficult to design Tools for optimization are not as good as for two-level Analysis is more complex

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Time Behavior of Combinational Networks

Waveforms
Visualization of values carried on signal wires over time Useful in explaining sequences of events (changes in value)

Simulation tools are used to create these waveforms

Input to the simulator includes gates and their connections Input stimulus, that is, input signal waveforms

Some terms
Gate delaytime for change at input to cause change at output
Min delaytypical/nominal delaymax delay Careful designers design for the worst case

Rise timetime for output to transition from low to high voltage Fall timetime for output to transition from high to low voltage Pulse widthtime an output stays high or low between changes
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Momentary Changes in Outputs

Can be usefulpulse shaping circuits Can be a problemincorrect circuit operation (glitches/hazards) Example: pulse shaping circuit
A' A = 0 delays matter in function
A

D remains high for three gate delays after A changes from low to high

F is not always 0 pulse 3 gate-delays wide

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Oscillatory Behavior
Another pulse shaping circuit
+ A open switch close switch initially undefined open switch C B

resistor

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Hazards/Glitches
Hazards/glitches: unwanted switching at the outputs
Occur when different paths through circuit have different propagation delays
As in pulse shaping circuits we just analyzed

Dangerous if logic causes an action while output is unstable

May need to guarantee absence of glitches

Usual solutions
1) Wait until signals are stable (by using a clock): preferable (easiest to design when there is a clock synchronous design) 2) Design hazard-free circuits: sometimes necessary (clock not used asynchronous design)

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Types of Hazards
Static 1-hazard
Input change causes output to go from 1 to 0 to 1
1 1

Static 0-hazard
INput change causes output to go from 0 to 1 to 0

Dynamic hazards
Input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0

1
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Static Hazards
Due to a literal and its complement momentarily taking on the same value
Thru different paths with different delays and reconverging

May cause an output that should have stayed at the same value to momentarily take on A the wrong value Example: multiplexer
A S
B F S S' B S' static-0 hazard static-1 hazard
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F hazard

Dynamic Hazards
Due to the same versions of a literal taking on opposite values
Thru different paths with different delays and reconverging

May cause an output that was to change value to change 3 times instead of once Example:
A 3 B 1 C F A C B1

B2
B3 F dynamic hazards hazard

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Making Connections
Direct point-to-point connections between gates
Wires we've seen so far

Route one of many inputs to a single output ---

multiplexer

Route a single input to one of many outputs ---

demultiplexer
control

control

multiplexer

demultiplexer
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4x4 switch

Mux and Demux

Switch implementation of multiplexers and demultiplexers
Can be composed to make arbitrary size switching networks Used to implement multiple-source/multiple-destination interconnections
A Y

B
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Mux and Demux (cont'd)

Uses of multiplexers/demultiplexers in multi-point connections
A0 A1 MUX Sa B0 B1 Sb multiple input sources

MUX

A Sum

Ss

DEMUX S0 S1

multiple output destinations

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Multiplexers/Selectors
Multiplexers/Selectors: general concept
2n data inputs, n control inputs (called "selects"), 1 output Used to connect 2n points to a single point Control signal pattern forms binary index of input connected to output
Z = A' I0 + A I1 A 0 1 Z I0 I1 I1 0 0 0 0 1 1 1 1 I0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1

functional form
logical form two alternative forms for a 2:1 Mux truth table
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Multiplexers/Selectors (cont'd)
2:1 mux: 4:1 mux: Z = A' I0 + A I1 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

8:1 mux:

Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

2 n -1

In general, Z = k=0

in minterm shorthand form for a 2n:1 Mux

(mkIk)

I0 I1

2:1 mux
A

I0 I1 I2 I3

4:1 mux A B

I0 I1 I2 I3 I4 I5 I6 I7

8:1 mux

A B C

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Gate Level Implementation of Muxes

2:1 mux

4:1 mux

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Cascading Multiplexers
Large multiplexers implemented by cascading smaller ones
I0 I1 I2 I3 I4 I5 I6 I7 4:1 mux 8:1 mux alternative implementation Z I0 I1 2:1 mux 2:1 mux 2:1 mux 2:1 mux C A B 8:1 mux

2:1 mux
4:1 mux

I2 I3
A I4 I5 I6 I7

B C

4:1 mux

control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7

control signal A chooses which of the upper or lower mux's output to gate to Z

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Multiplexers as General-purpose Logic

2n:1 multiplexer implements any function of n variables
With the variables used as control inputs and Data inputs tied to 0 or 1 In essence, a lookup table

Example:
F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B

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Multiplexers as General-purpose Logic (contd)

2n-1:1 mux can implement any function of n variables
With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement

Example:
F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 C' C' 0 1 C' C' 0 1 0 1 4:1 MUX 2 3 S1 S0 A B

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Multiplexers as General-purpose Logic (contd)

Generalization
I0 n-1 mux control variables single mux data variable I1 . . . In-1 In F

.
.

.
.

.
.

.
.

0
1

0
0 0

0
1 In

1
0 In'

1
1 1

four possible configurations of truth table rows can be expressed as a function of In

Example: F(A,B,C,D) implemented by an 8:1 MUX

A
1 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0
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choose A,B,C as control variables D multiplexer implementation

1 D 0 1 D D D D

0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B

Demultiplexers/Decoders
Decoders/demultiplexers: general concept
Single data input, n control inputs, 2n outputs Control inputs (called selects (S)) represent binary index of output to which the input is connected Data input usually called enable (G)
1:2 Decoder: O0 = G S O1 = G S 2:4 Decoder: O0 = G S1 O1 = G S1 O2 = G S1 O3 = G S1 S0 S0 S0 S0 3:8 Decoder: = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0

O0 O1 O2 O3 O4 O5 O6 O7

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Gate Level iImplementation of Demultiplexers

1:2 Decoders

active-high enable G S

O0 O1 O0 O1 O2 O3

active-low enable \G S

O0 O1

2:4 Decoders
G active-high enable

\G
active-low enable

O0 O1 O2 O3

S1 S0

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S1 S0

Demultiplexers as General-purpose Logic

n:2n decoder implements any function of n variables
With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function
0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B C
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A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals)

Demultiplexers as General-purpose Logic (contd)

F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D + A B C

F3 = (A' + B' + C' + D')

Enable

4:16 DEC

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD

F1

F2

F3

A B C D
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Cascading Decoders
5:32 decoder
1x2:4 decoder 4x3:8 decoders

0 2:4 DEC 1 2 S1 S0 3 A B

0 1 2 3:8 DEC3 4 5 6 7 S2 S1 S0

A'B'C'D'E'

0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0

A'BC'DE'

0 1 2 3:8 DEC3 4 5 6 7 S2 S1 S0 C D E

ABCDE

0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0 C D E

AB'C'D'E'

AB'CDE

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Programmable Logic Arrays

Pre-fabricated building block of many AND/OR gates
Actually NOR or NAND Personalized" by making or breaking connections among gates Programmable array block diagram for sum of products form
inputs

AND array

product terms

OR array

outputs
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Enabling Concept
Shared product terms among outputs
example:

F0 F1 F2 F3

= = = =

A + A C' B' C' B' C

B' C' + AB + AB + A
input side: 1 = uncomplemented in term 0 = complemented in term = does not participate

personality matrix
product term AB B'C AC' B'C' A inputs A B 1 1 0 1 0 1 outputs F0 F1 0 1 0 0 0 1 1 0 1 0

C 1 0 0

F2 1 0 0 1 0

F3 0 1 0 0 1

output side: 1 = term connected to output 0 = no connection to output reuse of terms

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Before Programming
All possible connections available before "programming"
In reality, all AND and OR gates are NANDs

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After Programming
Unwanted connections are "blown"
Fuse (normally connected, break unwanted ones) aAnti-fuse (normally disconnected, make wanted connections)
A

AB B'C

AC'
B'C' A

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F0

F1

F2

F3

Alternate Representation for High Fan-in Structures

Short-hand notation--don't have to draw all the wires
Signifies a connection is present and perpendicular signal is an input to gate
notation for implementing F0 = A B + A' B' F1 = C D' + C' D

A B C D AB A'B' CD' C'D

AB+A'B' CD'+C'D
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Programmable Logic Array Example

Multiple functions of A, B, C
F1 = A B C F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C F6 = A xnor B xnor C
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 0 0 0 0 0 0 0 1 F2 0 1 1 1 1 1 1 1 F3 1 0 0 0 0 0 0 0 F4 1 1 1 1 1 1 1 0 F5 0 1 1 0 1 0 0 1 F6 0 1 1 0 1 0 0 1 A B C full decoder as for memory address bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

F1 F2 F3 F4 F5 F6

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PALs and PLAs

Programmable logic array (PLA)
What we've seen so far Unconstrained fully-general AND and OR arrays

Programmable array logic (PAL)

Constrained topology of the OR array Innovation by Monolithic Memories Faster and smaller OR plane
a given column of the OR array has access to only a subset of the possible product terms

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PALs and PLAs: Design Example

BCD to Gray code converter
A 0 0 0 0 0 0 0 0 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 1 C 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 1 0 0 0 0 Y 0 0 1 1 1 1 1 1 0 0 Z 0 1 1 0 0 0 0 1 1 0
A 0 0 C 0 0 0 1 1 X X X 1 1 X D 0 0 C 0 0 1 1 0 X X X A 0 0 X D

1
B

0
B

K-map for W
A 0 0 C 1 1 1 1 1 1 B X X X X 0 0 X X D

K-map for X
A 0 1 C 0 1 0 0 1 0 B X X X X 1 0 X X D

minimized functions:
W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D'

K-map for Y

K-map for Z

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PALs and PLAs: Design Example (contd)

Code converter: programmed PLA
A B C D A BD BC BC' B C A'B'C'D BCD AD'

minimized functions: W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D'

not a particularly good candidate for PAL/PLA implementation since no terms are shared among outputs

BCD'
W X Y Z

however, much more compact and regular implementation when compared with discrete AND and OR gates

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PALs and PLAs: Design Example (contd)

A B C D A BD BC 0 BC' 0

Code converter: programmed PAL

4 product terms per each OR gate

0
B C 0 0 A'B'C'D BCD AD' B'CD'

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W X

Y Z

PALs and PLAs: Design Example (contd)

Code converter: NAND gate implementation
Loss or regularity, harder to understand Harder to make changes
A B D B C B C X W D B C D A \D \B C \D A B C

Y
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PALs and PLAs: Another Design Example

Magnitude comparator
A A

A B

C D A'B'C'D' A'BC'D

1
0 C 0 0

0
1 0 0 B

0
0 1 0

0
0 0 1 D

0 1 C 1 1

1 0 1 1 B

1 1 0 1

1 1 1 0 D

ABCD AB'CD' AC' A'C B'D BD'

K-map for EQ
A 0 1 C 1 1 0 0 1 0 0 0 0 0 1 D

K-map for NE
A 0 0 C 0 0 1 0 1 1 1 1

A'B'D
D

B'CD ABC BC'D'

0
0 B

0
1

0
0

1
B

K-map for LT

K-map for GT
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EQ NE LT GT

Read-only Memories
Two dimensional array of 1s and 0s
Entry (row) is called a "word" Width of row = word-size Index is called an "address" Address is input Selected word is output
1 1 1 1
word lines (only one is active decoder is just right for this)

n 2 -1 i word[i] = 0011 word[j] = 1010

decoder

j 0

internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor selectively connected to 0 by word line controlled switches)

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ROMs and Combinational Logic

Combinational logic implementation (two-level canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 ROM 8 words x 4 bits/word

A B C F0 F1 F2 F3 address outputs block diagram

truth table

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ROM Structure
Similar to a PLA structure but with a fully decoded AND array
Completely flexible OR array (unlike PAL)
n address lines inputs

decoder

2n word lines

memory array (2n words by m bits)

outputs m data lines

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ROM vs. PLA

ROM approach advantageous when

Design time is short (no need to minimize output functions) Most input combinations are needed (e.g., code converters) Little sharing of product terms among output functions Size doubles for each additional input Can't exploit don't cares Design tools are available for multi-output minimization There are relatively few unique minterm combinations Many minterms are shared among the output functions Constrained fan-ins on OR plane
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ROM problems

PLA approach advantageous when

PAL problems

Regular Logic Structures for Two-level Logic

ROM full AND plane, general OR plane
Cheap (high-volume component) Can implement any function of n inputs Medium speed

PAL programmable AND plane, fixed OR plane

Intermediate cost Can implement functions limited by number of terms High speed (only one programmable plane that is much smaller than ROM's decoder) Most expensive (most complex in design, need more sophisticated tools) Can implement any function up to a product term limit Slow (two programmable planes)
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PLA programmable AND and OR planes

Regular Logic Structures for Multi-level Logic

Difficult to devise a regular structure for arbitrary connections between a large set of different types of gates
Efficiency/speed concerns for such a structure Xilinx field programmable gate arrays (FPGAs) are just such programmable multi-level structures
Programmable multiplexers for wiring Lookup tables for logic functions (programming fills in the table) Multi-purpose cells (utilization is the big issue)

Use multiple levels of PALs/PLAs/ROMs

Output intermediate result Make it an input to be used in further logic

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Combinational Logic Implementation Summary

Multi-level Logic

Conversion to NAND-NAND and NOR-NOR networks Transition from simple gates to more complex gate building blocks Reduced gate count, fan-ins, potentially faster More levels, harder to design

Time Response in Combinational Networks Regular Logic

Multiplexers/decoders ROMs PLAs/PALs Advantages/disadvantages of each
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Gate delays and timing waveforms Hazards/glitches (what they are and why they happen)