CONTENTS:

INTRODUCTION DESIGN METRICS STRUCTURE OF CMOS INVERTER SWITCH MODELS OF CMOS INVERTER STATIC PROPERTIES VOLTAGE TRANSFER CHARACTERISTICS SWITCHING THRESHOLD VOLATGE NOISE MARGINS POWER DISSIPATION CONCLUSION

 INTRODUCTION:
Inverter is a fundamental logic gate that performs boolean operation on single input variable . Analysis of MOS inverters can directly applied to more complex logic circuits such as Nand, Nor etc.
A 0 1 B 1 0

B=A

In MOS Inverter circuits both input variable and output are represented by node voltages referenced to ground potential. - Logic 1 represents high voltage . - Logic 0 represents low voltage .

 Different design metrics are Cost

Complexity Area Integrity and robustness Performance Energy efficiency

 Structure of CMOS inverter :

Structure of CMOS inverter consists of NMOS transistor and PMOS transistor which acts as load.

 Gates of the two transistor are shorted at the input and drains are shorted at the output.
Source of the PMOS is connected to VDD(power supply) and of NMOS is connected to ground.
Switch models of CMOS inverter

 From the above fig when Vin is high and equal to Vdd , Nmos transistor is on and Pmos is off . Direct path exists between Vout and ground node resulting in a steady state value of 0 V.
When the input voltage is low (0 V) , NMOS and PMOS transistors are off and on. Here the path exists between VDD and Vout .

Complementary CMOS: The static CMOS gate is a combination of two networks Pull up network (PUN) and Pull down network(PDN).

Static properties of CMOS inverter characteristics:

The high and low output levels equal VDD and ground which implies that voltage swing is equal to the supply voltage resulting in high noise margins.

The logic levels are not dependent upon the relative device sizes,so that the transistors can be minimum size. Gates with this property are called ratioless.
Logic levels are determined by the relative dimensions of the composing transistors is called as ratioed logic.

 No direct path exists between the supply and ground rails under steady-state operating conditions (when the input and outputs remain constant). The absence of current flow means that the gate does not consume any static power.

Voltage-transfer characteristic (VTC) can be graphically deduced by superimposing the current characteristics of the NMOS and the PMOS devices.

 Load line curves for PMOS and NMOS are plotted as shown above. For a dc operating points to be valid, the currents through the NMOS and PMOS devices must be equal.

 The VTC of the inverter hence exhibits a very narrow transition zone. This results from the high gain during the switching transient, when both NMOS and PMOS are simultaneously on, and in saturation. In that operation region, a small change in the input voltage results in a large output variation.

VTC of static CMOS inverter, derived from the load curves as shown above (VDD = 2.5 V).

 There are 5 different regions in the VTC as shown in the fig above.

In the first region Vin<Vth which means that NMOS is not conducting and PMOS is in conducting region and hence the output voltage is going to be VDD. In the second region PMOS is in the linear region where as NMOS is in the saturation region. In the third region there is going to be sharp change in the region where both NMOS and PMOS are in saturation regions. In the fourth region as we increase the input voltage NMOS is in saturation region and PMOS is in linear region. In the fifth region when Vin<Vdd-|Vtp| NMOS is in saturation region and PMOS is off where Vout=0.

 The above characteristics also represent the input output characteristics of an ideal inverter. Switching threshold voltage of a CMOS inverter:
The switching threshold, VM, is defined as the point where Vin = Vout. Its value can be obtained graphically from the intersection of the VTC with the line given by Vin = Vout. In this region, both PMOS and NMOS are always saturated. We obtain the expression for VM ignoring the channel length modulations as follows

For larger values of VDD the above equation can be simplified as

VM=r VDD/(1+r)

Which states that the switching threshold is set by ratio r, which compares the relative driving strengths of NMOS and PMOS transistors.

The required ratio of PMOS to NMOS transistor sizes can be set to a desired value VM by the following expression.

NOISE MARGINS: Piecewise linear approximation of VTC simplifies the derivation of VIL and VIH

VIH and VIL are the operational points of the inverter where dvout/dvin=-1 where gain of the amplifier is -1

Piecewise approximation approach yields the following expressions for width of the transition region VIH-VIL, VIH, VIL and the noise margins NMH and NML are calculated as follows,

To calculate the midpoint gain of the static CMOS inverter we assume PMOS and NMOS are velocity saturated where gain is the strong function of slopes of the currents in saturation region.

Hence the channel length modulation factor cannot be ignored which would lead to infinite gain .The gain can be now derived by differentiating the below equation which is valid around the switching threshold with respect to Vin:

with ID(VM) the current flowing through the inverter for Vin = VM. The gain is almost determined by channel length modulation.

Scaling the supply voltage:

Scaling

the supply voltage means reducing the signal swing which helps to reduce the internal noise in the system (such as caused by crosstalk) and makes the design more sensitive to external noise sources that do not scale.

POWER DISSIPATION:
There will not be power dissipation in static cmos inverter but when the transistor is switching or changing its state power dissipation occurs.

Inverter has the capacitive load at the output of the CMOS which is connected to the input of the another CMOS. Because of the charging and discharging property of capacitor there will be flow of current.

 There will be 2 types of transitions during the charging and discharging of the capacitor .
Energy transfer during each transistor can be given as

 The frequency f is given as the number of transitions per second. Hence , the total power dissipation during the f number of transitions can be given as

Power dissipation of the inverter can be reduced by reducing the capacitance which is proportional to area i.e., if we reduce the dimensions capacitance will be reduced and hence the power dissipation is reduced.

Another way to reduce the power dissipation is reduce Vdd2.

CONCLUSION:
The CMOS inverter is an important circuit device that provides quick transition time, high buffer margins, and low power dissipation which are the desired qualities which makes in inverters for most circuit design.

THANK U