ASIC is a Unique Product.

An ASIC (a-sick) is an application- specific integrated circuit ASICs are the standard parts, used to design microelectronic systems ASIC is an integrated circuit customized for particular use, rather than intended for general purpose use. s-o-c System on chip

Customer
Logic Design/ Front End

Specification Fab-Less Design House

Gate Level Net List Physical layout/Masks Full Custom ASIC

Physical Design/ Back End Foundry/ Processing

FPGA ASIC

Semi -Custom ASIC

Gate Array ASIC

Transformation of a circuit design into physical representation for manufacturing The circuit design is described through a netlist. The end product from a physical design is a layout which is design rule, connectivity and timing correct. The layout data is sent to mask shop to generate masks for fabrication

PHYSICAL DESIGN

PHYSICAL DESIGN METHODOLOGY

Read in Netlist (Verilog or Edit)

Flatten the Netlit

Modify Netlist if Timing Doesnt meet

Static Timing Verification

Floorplan (Macro Placement, IO Placement, P/G routing

Insert Clock Trees (if necessary)

Back- Annotation SPEF/SDF

Place & Route

DRC/LVS

IMPLEMENTATIO N
SOC Encounter :Floor planning, placement and routing. Nano router : Optimize routing for timing, area, power and manufacturability.

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ANALYSIS
Common timing engine(CTE): Static timing analysis. Voltage Storm: Power analysis. Celtic: Crosstalk analysis.

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Today some of the most powerful microprocessor chips can dissipate 100-150Watts,for an average power density of 50-75 Watts per square centimeter. This Power density not only presents packaging and the cooling challenges; it also can pose problems for reliability, since the mean time to failure decreases exponentially with temperature. In addition, timing degrades with temperature & leakage increases with temperature.

From The International Technology Roadmap for Semiconductors (ITRS) makes the following predictions:

Today, the power consumption of ICs is considered one of the most important problems for high-performance chips, as well as for portable devices. For the latter, the problem is due to the limited cell battery lifetime, while it is the chip cooling for the first case.

For battery operated devices the distinction between power & energy is critical. Power is the instantaneous power in the device. Energy is the integral of power over time.

Power Dissipation
Kinds of power dissipation: Dynamic power is the power consumed when the device is active that is, when signals are changing values. Sources of dynamic power consumption: Switching Power: The charging and discharging of external capacitive load on output of a cell. Internal Power: Short circuit (crowbar) current that flows through Pmos - Nmos stack during a transition

Switching Power

Crowbar Current

Pdyn = Cef Vdd f clock

Static power is the power consumed when the device is powered up but no signals are changing value. In CMOS devices, static power consumption is due to leakage. Estimating leakage/static power : Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations

Power Dissipation Contd.

Power Dissipation Contd.

There are four main types of leakage currents in a CMOS gate Sub threshold Leakage (ISUB): The current which flows from drain to the source current of a transistor operating in weak inversion region. Sub threshold leakage occurs when the CMOS gate is not turned completely OFF. For a good approximation its value is given by,

I SUB = C ox Vth

W e L

VGS VT nV th

where, W & L >> dimensions of the transistor Vth >> threshold voltage kT/q (25.9 mV at room temperature) n >> function of the device fabric process & ranges from 1.0 to 2.5

Power Dissipation Contd.

Gate Leakage (IGATE): The current which flows directly from the gate through the oxide to substrate due to gate oxide tunneling and hot carrier injection. Gate leakage occurs as a result of tunneling current through the gate oxide. At future nodes, high-k dielectric materials will be required to keep gate leakage in check. This appears to be the only effective way of reducing gate leakage. Gate Induced Drain Leakage (IGIDL): The current which flows from the drain to substrate induced by a high field effect in the MOSFET drain caused by high VDG. Reverse Bias Junction Leakage (IREV): Caused by minority carrier drift and generation of electron or hole pairs in the depletion regions.

Clock Gating Gate Level Power Optimization Multi-VDD Multi-Vt

As geometries have shrunk to 130nm to 90nm and below, using libraries with multi-vt has become a common way of reducing leakage voltage. Scale down the threshold voltage for low voltage low power circuits to increase performance VT = Delay + Ileakage Low -VT : Provides high performance VT = Delay + Ileakage High -VT : Reduces subthreshold leakage

Low threshold voltage cell technique( Lvt) High threshold voltage cell technique( Hvt) Standard/Normal threshold voltage cell technique( Rvt) Mixed flow design

Use mix of different Vt cells in a single design Design Libraries Multiple libraries at different Vt options Optimization Tools Optimization tools employ different Vt cells For timing critical paths, use low Vt cells (LVT) For non timing critical paths, use high Vt cells (RVT) Meets performance target, while minimizing

What is the best way to optimize the design with multiple libraries to meet timing, area and power design goals?

Baseline
Only RVT library (Optimized for timing and area, but not leakage power) Only LVT library (Optimized for timing and area, but not leakage power)

One pass synthesis

Both RVT and LVT library in a single run (MVT synthesis) Multiple Vt optimization effort level low, medium, high

Two pass synthesis

Initial synthesis with RVT followed by both RVT and LVT libraries for timing closure (RVT/LVT synthesis) Initial synthesis with LVT followed by both RVT and LVT libraries for power recovery (LVT/RVT synthesis)

Power is the next frontier for VLSI designs Leakage power is exponentially increasing! Use of multiple libraries with different Vt is inevitable to meet the performance and area goals, while minimizing leakage power. Multiple Vt libraries are solution for minimizing leakage power Number of different Vt libraries are increasing to meet the demand