Documenti di Didattica
Documenti di Professioni
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Presented by
Nikunj Shroff 2005JCA2435
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Agenda
Objective. Project Overview. Core Block Diagram of MicroBlaze. SystemC. Block Diagram of system (PowerPC). Image Processing application. Observation. References.
2
Objective
hierarchy
for
embedded
system
Project Overview
MicroBlaze
SystemC
PowerPC
Processors
MicroBlaze
PowerPC
MicroBlaze (www.xilinx.com)
Connect to an Fast Simplex Link (FSL) interfaced memory controller via an explicitly instantiated FSL master/slave pair. Connect directly to a memory controller with integrated FSL buffers, e.g. the MCH_OPB_SDRAM), which results in less latency and fewer instantiations.
Data Cache
All cacheable data addresses are further split into two segments:
The size of the two segments can be configured by the user. The size of the cache word address can be between 11 to 14 bits. This results in a cache sizes ranging from 8 kB to 64 kB. The tag address should be sized so that it matches the complete range of cacheable memory in the design.
Operation is performed as normal but Data cache is updated with the new data,
Example
(All addresses within this range correspond to the cacheable address space segment. All other addresses are non-cacheable)
BRAM
ILMB
Microblaze
To UART
11
DLMB
DOPB IOPB
BRAM
ILMB
Microblaze
To UART
DLMB
DOPB IOPB
BRAM
ILMB
Microblaze
IXCL
MCH 0
DXCL
MCH 1
To External Memory
Memory Controller
SOPB
Timer OPB
13
DLMB
BRAM
ILMB
DOPB IOPB
Microblaze
1 2
FSL 0,1,2,3
3 4
To UART
Memory Controller
SOPB
Timer
14
OPB
SystemC
To create a system-level model. Quick simulation in order to validate and optimize the design.
Provide the hardware and software development with an executable specification of the system.
The SystemC Class Library provides the necessary constructs to model system architecture including
Internal Architecture
MicroBlaze
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Microblaze
instr From IBRAM i_ready D_ready From DBRAM Data_read Microblaze i_en i_address i_fetch i_as en Read_strobe Write_strobe i_address Byte_enable address Data_write To IBRAM
To
DBRAM
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SYSTEM VIEW
FPGA PLB OPB BRAM ILMB
DLMB PowerPC
Application BRAM Timer IP (My IP) PLB2OPB Bridge
Memory Controller Sys ACE Controller OPB2DCR Bridge DCR Video Controller
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Second Image
Third Image
Blue
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Image Processing
Normal image
Revert Color
Mirror Image
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Observation
Matrix size Both I & D cache
(clock cycles)
No cache
(clock cycles)
Instruction cache
(clock cycles)
(clock cycles)
Data cache
5x5 10x10
2003 12463
37490 265035
7469 55231
33345 230168
15x10
20x20 25x25 30x30
38915
89003 170156 289866
859133
1996113 3852207 6603814
165728
430827 840119 1444898
739001
1708599 3286614 5623507
58
103 158 228
35x35
40x40 45x45 50x50
455635
675048 955379 1687005
10427222
15498712 21994753 30091400
2278266
3402303 4836551 6620709
8864491
13162708 18660692 25875386
308
405 508 11784
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Overall Comparison
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Observation (PowerPC)
No. of Images Both Cache off I-cache ON (Clocks)
(Clocks)
1 1809998 1500337
D-Cache ON (Clocks)
1.2
1197707
1.51
836977
2.16
3729994
2834520
1.31
2391502
1.55
1669324
2.24
5594344
4249072
1.31
3584422
1.56
2501056
2.23
7213484
6175721
1.17
4778200
1.51
3333481
2.16
9016292
7718060
1.16
5971158
1.50
4165239
2.16
6 7
10820264 12623647
8928029 10804383
1.21 1.16
7165016 8358387
1.51 1.51
4997595 5829637
2.16 2.16
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Conclusion
Instructions are fetched frequently so caching of instructions gives high performance gain. In above mentioned memory models xilinx cache link is the best one which has less latency for instruction and data access. The size of Data is more so caching of data in this case gives more performance gain.
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References
Embedded Development Kit, Getting Started with EDK, 1-800-255-7778 EDK 7.1i February 15, 2005 http://www.xilinx.com. MicroBlaze Processor Reference Guide,1-800-255-7778 UG081 (v5.0) January 20, 2005 http://www.xilinx.com. FPGA Field Programmable Gate Array, http://www.andraka.com/whatisan.htm VHDL Very High Speed Integrated Circuit Hardware Description Language http://ghdl.free.fr/ghdl/index.html Fast Simplex Link FSL, DS449 December 1, 2005 www.xilinx.com MCH controllerMulti-CHannel (MCH) On-chip Peripheral Bus controller. DS496 July 1, 2005 www.xilinx.com PowerPC Processor. EDK 6.1 September 2, 2003 www.xilinx.com Relocating Data and code for embedded systems, XAAP642 (v1.0) October 21, 2002 www.xilinx.com. Platform studio User guide for EDK 6.2i UG113 (v1.0) March 12, 2004 Device Driver Programmer Guide. v1.2 - July 31, 2002 www.xilinx.com. XUP Virtex-II Pro Development System Hardware Reference Manual, Document Version: 0.00Document Date: August 2004
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