Chap.

4 Register Transfer and Microoperations

s

4-1

4-1 Register Transfer Language

Microoperation q The operations executed on data stored in registers(shift, clear, load, count) Internal H/W Organization(best defined by specifying)

1. The set of registers(register , , ) 2. The sequence of microoperations 3. The sequence control of microoperations
Register Transfer Language q The symbolic notation used to describe the microoperation transfer among registers
The use of symbols instead of a narrative explanation provides an organized and concise manner
q

A convenient tool for describing the internal organization of digital computers in concise and precise manner

4-2 Register Transfer

Registers : Fig. 4-1 q Designated by Capital Letter(sometimes followed by numerals) : MAR(Memory Address Register), PC(Program Counter), IR(Instruction Register), R1(Processor Register)
Chap. 4 Register Transfer and Microoperations

Computer System Architecture

Dept. of Info. Of Computer.

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q q

The individual F/Fs in an n-bit register : numbered in sequence from 0(rightmost position) through n-1 The numbering of bits in a 16-bit register : marked on top of the box A 16-bit register partitioned into two parts : bit 0-7(symbol L Low byte), bit 815(symbol H High byte)

Register Transfer : Information transfer from one register to another q R 2 R1 (transfer of the content of register R1 into register R2)
The content of the source register R1 does not change after the transfer

Control Function : The transfer occurs only under a predetermined control condition q The transfer operation is executed by the hardware only if P=1 : Fig. 4-2

if ( P = 1) then ( R 2 R1) P : R 2 R1
q

A comma is used to separate two or more operations(Executed at the same time)

T : R 2 R1, R1 R 2

Basic Symbols for Register Transfer : Tab. 4-1

Symbol erals) Letters(and num Parentheses ( ) Arrow < Comma ,
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Description Denotes a register Denotes a part of a register Denotes transfer of information Separates two microoperations

Examples MAR, R2 R2(0- 7), R2(L) R2 < - R1 R2 < - R1, R1 < - R2 -

Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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4-3 Bus and Memory Transfers

Common Bus q A more efficient scheme for transferring information between registers in a multiple-register configuration q A bus structure = a set of common lines q Control signals determine which register is selected
One way of constructing a common bus system is with multiplexers The multiplexers select the source register whose binary information is place on the bus
q

The construction of a bus system for four registers : Fig. 4-3

4 bit register X 4 Four 4 X 1 Multiplexers Bus Selection : S0, S1
S1 S0 0 0 0 1 1 0 1 1 Register selected A B C D
S1 S0
M 3 4 * 1 U X 2 1 0 3 3 M 4 * 1 U X 2 1 0 2 3 M 4 * 1 U X 2 1 0 1 3 M 4 * 1 U X 2 1 0 0

4-line common bus

8 Registers with 16 bit

16 X 1 mux 8
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Register D
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Register C

Register B

Register A

Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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Bus Transfer q The content of register C is placed on the bus, and the content of the bus is loaded into register R1 by activating its load control input Bus

Bus C , R1 Bus

R1 C Three-State Bus Buffers

q q q

R1 Register

C Register

A bus system can be constructed with three-state gates instead of multiplexers Tri-State : 0, 1, High-impedance(Open circuit) Buffer
A device designed to be inserted between other devices to match impedance, to prevent mixed interactions, and to supply additional drive or relay capability Buffer types are classified as inverting or noninverting

Tri-state buffer gate : Fig. 4-4

When control input =1 : The output is enabled(output Y = input A) When control input =0 : The output is disabled(output Y = high-impedance)
Normal input A Control input C If C=1, Output Y = A If C=0, Output = High-impedance

Computer System Architecture

Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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The construction of a bus system with tri-state buffer : Fig. 4-5 q The outputs of four buffer are connected together to form a single bus line(Tristate buffer ) q No more than one buffer may be in the active state at any given time(2 X 4 Decoder ) q To construct a common bus for 4 register with 4 bit : Fig. 4.5 4 (register decoder buffer )
A0 B0 C0 D0 Select input Enable input
S S E
1

Bus line for bit 0

0 2 * 4 1 d e c o d e r 2 3

AR: Address Reg. DR: Data Reg. M : Memory Word(Data)

READ : WRITE : DR M [ AR ] M [ AR ] R1

Memory Transfer q Memory read : A transfer information into DR from the memory word M selected by the address in AR q Memory Write : A transfer information from R1 into the memory word M selected by the address in AR
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Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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The 4 types of microoperation in digital computers

Register transfer microoperation : Sec 2-4 Sec 4-2 Arithmetic microoperation Logic microoperation Shift microoperation
Sec 4-4, 4-5, 4-6 Sec 4-7 3

4-4 Arithmetic Microoperation

Arithmetic Microoperation : Tab. 4-3 q Negate : 2s complement R 2 R 2 + 1 q Subtraction : R1 + 2s complement of R2 R 3 R1 R 2 = R1 + ( R 2 + 1) q Multiplication(shift left), Division(shift right) 4-bit Binary Adder : Fig. 4-6
q q

Full adder = 2-bits sum + previous carry c0(input carry), c4(output carry)
B3 A3
F A

B2

A2
F A

B1

A1
F A

B0

A0
F A

C0

C4
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S3

S2

S1

S0 Dept. of Info. Of Computer.

Chap. 4 Register Transfer and Microoperations

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4-bit Binary Adder-Subtractor : Fig. 4-7 q M =0 : Adder B M + C = B 0 + 0 = B, A + B q M =1 : Subtractor B M + C = B 1 + 1 = B + 1= -B(2s comp), A - B

B3 A3 B2 A2 B1 A1 B0 A0

F A

F A

F A

F A

C4 S3 S2 S1 S0

C0

4-bit Binary Incrementer q Sequential circuit implementation by using binary counter : Fig. 2-10 q Combinational circuit implementation by using Half Adder : Fig. 4-8
B3
x

B2
x

B1
x

B0
x

H A
C S C

H A
S C

H A
S C

H A
S

Always added to 1

C4
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S3

S2

S1

S0 Dept. of Info. Of Computer.

Chap. 4 Register Transfer and Microoperations

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Arithmetic Circuit q One composite arithmetic circuit in Tab. 4-3 : Fig. 4-9 q D= A0(X0) + B0(Y0) + Cin
B0 : S0, S1 B, B, 0, 1 Tab. 4-4 Input Y = B
Select Input S1 S0 Cin Y 0 0 0 B 0 0 1 B 0 1 0 B' 0 1 1 B' 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Output D= Y+ in A+ C D= B A+ D= B+ A+ 1 D= B' A+ D= B'+ A+ 1 D= A D= 1 A+ D= 1 AD= A M icrooperat Add Add wit Subtract with borrow Subtract Transfer A In c Decrem en Transfer A

Cin S0 S1 A0
S0 S1 0 1 2 3 4 * 1 M U X Y X0 C
0

F A
0

D0
C
1

B0

X1

A1

S0 S1 0 1 2 3 4 * 1 M U X Y

F A
1

D1
C
2

B1

X2 S0 S1

F A
4 * 1 M U X Y
2

A2

0 1 2 3

D2
X3 C
3

B2
S0 S1 0 4 * 1 M U X Y

A+1111=A-1

A+B=A+B+1-1 = A-B-1 A-1+1=A

F A
3

A3

1 2 3

D3 Cout

B3
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0 Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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4-5 Logic Microoperation

Logic microoperation q Logic microoperations consider each bit of the register separately and treat them as binary variables
exam) P : R1 R1 R 2 1010 Content of R1 + 1100 Content of R2 0110 Content of R1 after P=1

Special Symbols
Special symbols will be adopted for the logic microoperations OR(/), AND(), and complement(a bar on top), to distinguish them from the corresponding symbols used to express Boolean functions exam) P + Q : R1 R 2 + R 3, R 4 R5 R 6 Logic OR Arithmetic ADD
Ai Bi
1 E
i

Arithmetic 1s Complement

S0 S1

S S

4*1 M UX 0

List of Logic Microoperation q Truth Table for 16 functions for 2 variables : Tab. 4-5 q 16 Logic Microoperation : Tab. 4-6 All other Operation can be derived Hardware Implementation
q q

16 microoperation Use only 4(AND, OR, XOR, Complement) One stage of logic circuit : Fig. 4-10
Chap. 4 Register Transfer and Microoperations

Computer System Architecture

Dept. of Info. Of Computer.

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Some Applications q Logic microoperations are very useful for manipulating individual bits or a portion of a word stored in a register q Used to change bit values, delete a group of bits, or insert new bit values q Selective-set A A B
The selective-set operation sets to 1 the bits in register A where there are corresponding 1s in register B. It does not effect bit positions that have 0s in B
q

Selective-complement A A B
The selective-complement operation complements bits in A where there are corresponding 1s in B. It does not effect bit positions that have 0s in B

0
q

Selective-clear A A B
The selective-clear operation clears to 0 the bits in A only where there are corresponding 1s in B

0
q

Selective-mask A A B
The mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0s in B

1010 A before 1100 B(Logic Operand) 1110 A After Selective-set

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1010 A before 1100 B(Logic Operand) 0110 A After Selective-complement

1010 A before 1100 B(Logic Operand) 0010 A After Selective-clear

1010 A before 1100 B(Logic Operand) 0010 A After Selective-mask

Dept. of Info. Of Computer.

Chap. 4 Register Transfer and Microoperations

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Insert
The insert operation inserts a new value into a group of bits This is done by first masking the bits and then ORing them with the required value

1) Mask 0110 1010 A before 0000 1111 B mask 0000 1010 A after mask
q

2) OR 0000 1010 A before 1001 0000 B insert 1001 1010 A after insert

Clear 0110 0110 0000

A B A after clear

Clear A A B
The clear operation compares the words in A and B and produces an all 0s result if the two numbers are equal

4-6 Shift Microoperations

Shift Microoperations : Tab. 4-7 q Shift microoperations are used for serial transfer of data q Three types of shift microoperation : Logical, Circular, and Arithmetic Logical Shift

=q

A logical shift transfers 0 through the serial input The bit transferred to the end position through the serial input is assumed to be 0 during a logical shift(Zero inserted)
R1 shl R1 R 2 shr R 2 0 Chap. 4 Register Transfer and Microoperations 0 Dept. of Info. Of Computer.

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Circular Shift(Rotate) q The circular shift circulates the bits of the register around the two ends without loss of information
R1 cil R1 R 2 cir R 2

Arithmetic Shift q An arithmetic shift shifts a signed binary number to the left or right q An arithmetic shift-left multiplies a signed binary number by 2 q An arithmetic shift-right divides the number by 2 q Arithmetic shifts must leave the sign bit unchanged because the sign of the number remains the same q Shift left : R 2 ashl R 2 q Shift right : R 2 ashr R 2
LSB lost Carry out Sign bit 0 insert

MSB

LSB

Rn-1 Rn-2
MSB

....

R1 R0

LSB

Sign reversal occur : Overflow F/F Vs=1

= Rn 1 Rn 2

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Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.

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Hardware Implementation(Shifter) : Fig. 4-12

s

Serial input(IR)

Select(S)

4-7 Arithmetic Logic Shift Unit

One stage of arithmetic logic shift unit : Fig. 4-13
S3 S2 S1 S0

S 0 1 M U X

H0

Ci

A0 A1 A2 A3

S 0 1 M U X

H1

n a r c ( F

e s ta te o f it h m e t ic ir c u it ig . 4 . 9 )

S 0 M U X

S e le c t

H2

Ci+1

0 1 2 3

4 * 1 M U X

Fi

S 0 1 M U X

Bi Ai Ai-1 Ai+1

O n e s ta te o f lo g ic c ir c u it ( F ig . 4 . 1 0 )

H3

Serial input(IL)

Computer System Architecture

Chap. 4 Register Transfer and Microoperations

Dept. of Info. Of Computer.