PolyFuse OTP Cell

A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG 08.04.2005

A leap ahead in mixed signal

Purpose
Design an OTP Element in a Standard 0.35um CMOS Process
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PolyFuse element defined Programming within process specification High lifetime & reliability
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Implementation of the OTP Element into an IPBlock

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Infield programming option High programming yield

Outlook

Introduction into PolyFuse OTP Programming Characteristics Cross Sections Reliability and Yield WAT Implementation Design Issues for IP Block Summary
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Introduction
PolyFuse used as an OTP base element
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Poly Silicon with Tungsten Silizide Low ohmic standard resistance (<100W) High ohmic after programming (>10kW)
Contacts

Contact Barrier Poly Silicon Tungsten Silicide

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PolyFuse Element

Poly Fuse Area

Programming Features

Programming in standard CMOS process

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Tungsten Plug (Contact) Tungsten Silicide Poly Silicon

Current programming Infield programming possible

Programming Characteristic
Iprog mA Imelt

Imax

Ilinear: Linear resistor characteristics

Imin Ialloy Iosc

Iheat: Temp. is raising Imelt: Tungsten Silicide is melting

3s
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Ilinear tprog 0s 1s

Iheat

Vprog V

2s

Imax: Maximum current of minimum resistance Imin: Local current min. Ialloy: No autonomous Iosc: Oscillation because of current break off pinch

Cross Section
Typical Current Programmed Poly Fuse

Active PolyFuse region no longer has Tungsten included High ohmic stable alloy

Local break of a few nm Minimal lifetime drift of the resistance value

Tungsten Plug Tungsten Silicide Poly Silicon approx. 40nm

Field Oxide

Poly Silicon

Field Oxide Substrate

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Cross Section
Low Current Programmed Poly Fuse

Inhomogenious temperature gradient during programming

Low ohmic resistor Lifetime drift to higher resistor values

Tungsten Plug Tungsten Silicide Poly Silicon

Field Oxide

Tungsten Plug Tungsten Silicide Poly Silicon

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Field Oxide Substrate

Substrate
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Cross Section
Low Current Programmed Poly Fuse

High energy is forcing the Tungsten seperation Break before Tungsten completely removed
Tungsten Plug

Relatively high ohmic resistor Lifetime drift to lower resistor values possible
Tungsten Plug Tungsten Silicide Poly Silicon
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Tungsten Silicide Poly Silicon

Tungsten HALO

Field Oxide

Tungsten

Field Oxide Substrate

Substrate
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Reliability Investigations
Lifetime Drift over Time
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2000h BurnIn@125 C HTOL Test JESD22-108

Lifetime Drift Investigated for

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typical current programmed PolyFuses low current programmed PolyFuses high current programmed PolyFuses

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Yield Analysis
Testchip with Geometrical Variations
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Variation of size of programming transistor Variation of PolyFuse length and width

Design Of Experiment (DOE) Run

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With of Stack: Tungsten Silicide - Poly Silicon Tungsten Silicide thickness variation Poly Silicon thickness variation
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Analysis
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Programming within specified limits Variable temperature and supply specifications

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Process Control
WAT Structure
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PolyFuse Element Burning NMOS Transistor

Measurements
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Resistor of unprogrammed PolyFuse Resistor of programmed PolyFuse Current of Burning Transistor

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Design Issues
IP Blocks with PolyFuses Designed
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32 bit 128bit

Optimized Programming Path

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PolyFuse
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Related programming transistor

Special Test Function

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to guarantee lifetime stability for infield programming

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Design Requirement
Requirements For Lifetime Stability
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A programmed PolyFuse resistance must be larger than 10k after programming The resistance of a programmed PolyFuse is checked at 1k during lifetime operation This margin ensures proper operation of programmed PolyFuses over lifetime

Requirement for Infield Programming

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Testmode to measure the

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Base Cell
Principle Schematic
Supply

Poly Fuse

Testmodes
Programming Part

Different Bias Currents

Reading Part

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PolyFuse Element Programming Transistor Current Mirror

Control Voltage NMOS Current Mirror Level Detector
Digital Level

Base Cell
Principle Layout
LOGIC

PROGramming Mode Optional Parallel Out

PROM

RAM
WRITE READ

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PROM Storage RAM Access LOADing Mode

PROG LOAD
Parallel Out

OTP Block
Principle Layout of OTP Block
Parallel Dataout: Bits m0 (m 0 - )0

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32bit and 128bit Version 32bit Parallel Out Address Decoder Autoloader at Startup

AD Address DRE BUS SS

Enable

m m m m m 0000 0 0 0 00 0 00 0 0 0 00 0 00 0 0 0 00 0 00 0 0 0 00 0 00 0
Base Cells

de co d er

Base Line

0 0 0 0 0 0 0 0

M ode BUS

Mode

DATA Transfer
Parallel Dataout: Bits 0000

Combination up to 2kbit

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0 bit DATA BUS

Conclusion

- Reliable Programming Conditions - Programmable over whole Process Range - Lifetime Stability - Process Control - Infield Programming Option
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- High Programming Yield