Suresh Kumar K B

Lecturer in Electronics

UNIT - II

SKB's

FEATURES
8-bit CPU optimized for control applications Extensive Boolean processing (Single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator
SKB's 3

PIN DETAILS

P1 P0
RESET

+ _
P3

P2

XTAL

SKB's

BLOCK DIAGRAM
Interrupt Control

4K ROM

128 RAM

Timer 0 Timer 1

CPU
OSC
Bus Control

4 I/O Ports

Serial Port
TXD RXD

P0

P1

P2

P3

ARCHITECURE

All

SKB's

ARCHITECURE

SKB's

ARCHITECURE

SKB's

ARCHITECURE

SKB's

MEMORY STRUCTURE
External

60K

64K

External
SFR

64K

EXT
EA = 0

INT
EA = 1

4K

128 Data Memory

SKB's 10

Program Memory

INTERNAL RAM STRUCTURE

Inirect Direct Addressing Addressing Only Only

SFR

Direct & Indirect Addressing

128 Byte Internal RAM

SKB's

11

128 BYTE RAM

General Purpose Area

BIT Addressable Area 128 BYTE INTERNAL RAM Reg Bank 3 Reg Bank 2 Register Banks Reg Bank 1 Reg Bank 0
SKB's 12

REGISTER BANK STRUCTURE

Bank 3 Bank 2

R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7

Bank 1
Bank 0

R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 R7

Program Status Word - PSW

CY

AC

F0
SKB's

RS1 RS0 OV

P
13

SFR
F8 F0 E8 E0 D8 D0 C8 PSW Acc B FF F7 EF E7 DF D7 CF

C0
B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH
SKB's

C7
BF B7 AF A7 SBUF TH0 TH1 PCON 9F 97 8F 87
14

UNIT - III

SKB's

15

TIMERS SERIAL PORT INTERRUPTS

SKB's 16

TIMERS SERIAL PORT INTERRUPTS

SKB's 17

TIMERS Timer 0
Mode 0 Mode 1 Mode 2 Mode 3
SKB's 18

Timer 1
Mode 0 Mode 1 Mode 2

TIMER / COUNTER
OSC 12
C /T 0

TL

TH

TF
(1 Bit)

C /T 1

(8 Bit) (8 Bit)

T PIN

TR
Gate
INT PIN
SKB's

INTERRUPT

19

TIMER 0
OSC 12
C /T 0

TL0 TH0

TF0

C /T 1

T 0PIN

TR0
Gate
INT 0 PIN
SKB's

INTERRUPT

x
20

TIMER 0 Mode 0
13 Bit Timer / Counter
OSC 12
T 0PIN

TR0
Gate
INT 0 PIN

C /T 0
C /T 1

TL0 TH0 (5 Bit) (8 Bit)

TF0

INTERRUPT

Maximum Count = 1FFFh (1111111111111)

SKB's 21

TIMER 0 Mode 1
16 Bit Timer / Counter
OSC 12
T 0PIN

TR0
Gate
INT 0 PIN

C /T 0
C /T 1

TL0 TH0 (8 Bit) (8 Bit)

TF0

INTERRUPT

Maximum Count = FFFFh (1111111111111111)

SKB's 22

TIMER 0 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC 12
T 0PIN

TR0
Gate
INT 0 PIN

C /T 0
C /T 1

TL0 (8 Bit)
Reload

TF0

INTERRUPT

TH0 (8 Bit)

Maximum Count = FFh (11111111)

SKB's 23

TIMER 0 Mode 3
Two - 8 Bit Timer / Counter
OSC 12
T 0PIN

TR0
Gate
INT 0 PIN

C /T 0
C /T 1

TL0 (8 Bit)

TF0

INTERRUPT

OSC

12

TH0 (8 Bit)
SKB's

TF1

INTERRUPT

TR1

24

TIMER 1
OSC 12
C /T 0

TL1 TH1

TF1

C /T 1

T1PIN

TR1
Gate
INT 1 PIN
SKB's

INTERRUPT

25

TIMER 1
OSC 12
C /T 0

TL1 TH1

TF1

C /T 1

T1PIN

TR1
Gate
INT 1 PIN
SKB's

INTERRUPT

Y
26

TIMER 1 Mode 0
13 Bit Timer / Counter
OSC 12
T1PIN

TR1
Gate
INT 1 PIN

C /T 0
C /T 1

TL1 TH1 (5 Bit) (8 Bit)

TF1

INTERRUPT

Maximum Count = 1FFFh (1111111111111)

SKB's 27

TIMER 1 Mode 1
16 Bit Timer / Counter
OSC 12
T1PIN

TR1
Gate
INT 1 PIN

C /T 0
C /T 1

TL1 TH1 (8 Bit) (8 Bit)

TF1

INTERRUPT

Maximum Count = FFFFh (1111111111111111)

SKB's 28

TIMER 1 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC 12
T1PIN

TR1
Gate
INT 1 PIN

C /T 0
C /T 1

TL1 (8 Bit)
Reload

TF1

INTERRUPT

TH1 (8 Bit)

Maximum Count = FFh (11111111)

SKB's 29

SFRs Related to TIMER

TMOD
Gate C/ M1 M0 Gate C/ M1 M0

Timer 1

Timer 0

TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timers
SKB's

Interrupt
30

TIMERS SERIAL PORT INTERRUPTS

SKB's 31

Write to BUFFER
S
Q D CL

SBUFF
Zero Detector

RXD O/P

Start

Shift

TX Control
CLK
TX Clock TI Send

Serial Port Interrupt

RX Clock

RI

Receive Shift

TXD
Shift Clock

RI REN

RX Control
Start 1 1 1 1 1 1 1 0

RXD I/P

Input Shift Register

Load to BUFFER

SBUFF
Read From BUFFER
SKB's 32

SERIAL PORT Mode 0

The Serial Port in Mode-0 has the following features: Serial data enters and exits through RXD TXD outputs the shifl clock 8 bits are transmitted / received The baud rate is fixed at (1/12) of the oscillator frequency

SKB's

33

SERIAL PORT Mode 0

SKB's

34

SERIAL PORT Mode 0

SKB's

35

SERIAL PORT Mode 1

The Serial Port in Mode-1 has the following features: Serial data enters RXD Serial data exits through TXD On receive, the stop bit goes into RB8 in SCON 10 bits are transmitted / received Start bit (0) Data bits (8) Stop Bit (1) Baud rate is determined by the Timer 1 over flow rate.

SKB's

36

SERIAL PORT Mode 1

SKB's

37

SERIAL PORT Mode 1

SKB's

38

SERIAL PORT Mode 2

The Serial Port in Mode-2 has the following features: Serial data enters RXD Serial data exits through TXD 9th data bit (TB8) can be assign value 0 or 1 On receive, the 9th data bit goes into RB8 in SCON 11 bits are transmitted / received Start bit (0) Data bits (9) Stop Bit (1) Baud rate is programmable (1/32) or (1/64) of the oscillator frequency

SKB's

39

SERIAL PORT Mode 2

SKB's

40

SERIAL PORT Mode 2

SKB's

41

SERIAL PORT Mode 3

The Serial Port in Mode-3 has the following features:
Serial data enters RXD Serial data exits through TXD 9th data bit (TB8) can be assign value 0 or 1 On receive, the 9th data bit goes into RB8 in SCON 11 bits are transmitted / received Start bit (0) Data bits (9) Stop Bit (1) Baud rate is determined by the Timer 1 over flow rate.

SKB's

42

SERIAL PORT Mode 3

SKB's

43

SERIAL PORT Mode 3

SKB's

44

SFRs Related to SERIAL PORT

SCON
SM0 SM1 SM2 REN TB8 RB8 TI RI

PCON
SMOD

GF1

GF0

PD

IDL

SKB's

45

TIMERS SERIAL PORT INTERRUPTS

SKB's 46

INTERRUPTS
The Interrupt structure has the following features: 6 sources / 5 vectored interrupts Each interrupts can be individually programmable Each interrupts can have two priority levels Priority levels can be programmed All interrupts can be masked by a single bit - EA External interrupt type can be programmed Edge triggered Level Triggered

SKB's

47

TIMER / COUNTER
INT 0
IE0

TF 0
INT 1
IE1 INTERRUPT SOURCES

TF1
TI RI

SKB's

48

TIMER / COUNTER
IE Reg IP Reg

High Priority Interrupt

INT 0

0 IT 0 1

IE0

TF 0
0

INT 1

IT1

IE1

Interrupt Polling Sequence

TF1
TI RI
Individual Enable
SKB's

Global Disable Low Priority Interrupt

49

SFRs Related to INTERRUPTS

IE IP
-

EA

ES

ET1

EX1

ET0

EX0

PS

PT1

PX1

PT0

PX0

Priority Within Level

RI / TI LOW TF1 TR1 TF0 TF1 IE1 TF0 IE0 HIGH

TCON
TR0
SKB's

IE1

IT1

IE0

IT0

50

SKB's

51

MEMORY INTERFACING
External RAM Interfacing :-

P1

P0

Data

EXT RAM

MCS 51
P3 ALE P2

ALE

Address

WR

RD

RD WR

SKB's

52

MEMORY INTERFACING
External RAM Interfacing :D0

AD0

D CLK

A0 D1

AD1

D
CLK

A1 D2

AD2

D CLK

A2 D3

AD3

D CLK

A3

SKB's

53

MEMORY INTERFACING
External ROM Interfacing :-

P1

P0

Instr

EA

EXT ROM
ALE

MCS 51
P3 ALE P2

EEPROM
Address

PSEN

CE

SKB's

54

SKB's

55

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 56

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 57

Arithmetic Operation Group

ADD ADD ADD ADD A,Direct A,Rn A,@Ri A,#Data

SKB's

58

Arithmetic Operation Group

ADDC ADDC ADDC ADDC A,Direct A,Rn A,@Ri A,#Data

SKB's

59

Arithmetic Operation Group

SUBB SUBB SUBB SUBB A,Direct A,Rn A,@Ri A,#Data

SKB's

60

Arithmetic Operation Group

INC INC INC INC A Direct Rn @Ri

SKB's

61

Arithmetic Operation Group

DEC DEC DEC DEC A Direct Rn @Ri

SKB's

62

Arithmetic Operation Group

INC MUL DIV DA DPTR AB AB A

SKB's

63

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 64

Logical Operation Group

ANL ANL ANL ANL ANL ANL A,Direct A,Rn A,@Ri A,#Data Direct,A Direct,#Data
SKB's 65

Logical Operation Group

ORL ORL ORL ORL ORL ORL A,Direct A,Rn A,@Ri A,#Data Direct,A Direct,#Data
SKB's 66

Logical Operation Group

XRL XRL XRL XRL XRL XRL A,Direct A,Rn A,@Ri A,#Data Direct,A Direct,#Data
SKB's 67

Logical Operation Group

CLR A CPL A RL A RLC A RR A RRC A SWAP A

SKB's

68

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 69

Data Transfer Group

MOV MOV MOV MOV MOV MOV MOV A,Direct A,Rn A,@Ri A,#Data Rn,Direct Rn,@Ri Rn,#Data
SKB's 70

Data Transfer Group

MOV MOV MOV MOV MOV MOV MOV Direct,Direct Direct,Rn Direct,@Ri Direct,#Data Direct,A @Ri,A @Ri,#Data
SKB's 71

Data Transfer Group

MOV @Ri,Direct MOV DPTR,#DATA16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX @Ri,A MOVX @DPTR,A
SKB's 72

Data Transfer Group

PUSH Direct POP Direct XCH A,Rn XCH A,Direct XCH A,@Ri XCHD A,@Ri
SKB's 73

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 74

Boolean Variable Manipulation Group CLR C CLR bit SETB C SETB bit CPL C CPL bit
SKB's 75

Boolean Variable Manipulation Group ANL ANL ORL ORL MOV MOV C,bit C,/bit C,bit C,/bit C,bit bit,C
SKB's 76

Boolean Variable Manipulation Group JC JNC JB JNB JBC rel rel bit,rel bit,rel bit,rel

SKB's

77

Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
SKB's 78

Program Branching Group

ACALL LCALL RET RETI AJMP LJMP SJMP addr11 addr16

SKB's

addr11 addr16 rel

79

Program Branching Group

JMP JZ JNZ CJNE CJNE CJNE CJNE @A+DPTR rel rel A,Direct,rel A,#Data,rel Rn,#Data,rel @Ri,#Data,rel
SKB's

80

Program Branching Group

DJNZ Rn,rel DJNZ Direct,rel NOP

SKB's

81

UNIT - IV

SKB's

82

UNIT - IV

SKB's

83

8255
Programmable Peripheral Interface

24 Programmable I/O pins Three Configurable Ports - A,B & C BSR Mode TTL Compatible

SKB's

84

8255
Programmable Peripheral Interface

SKB's

85

8255
Programmable Peripheral Interface

SKB's

86

8255
Programmable Peripheral Interface

A1 0 0 1 1

A0 0 1 0 1

Select PA PB PC Control reg.

SKB's

87

8255
Programmable Peripheral Interface
Control Word General

D7 D6 D5 D4 D3 D2 D1 D0

Group A
Mode Selection 00 = Mode 0 01 = Mode 1 1x = Mode 2 PortA 1 = Input 0 = Output PortC (Upper) 1 = Input 0 = Output BSR Mode Select 0 = BSR Mode Enabled 1 = BSR Mode Enabled SKB's

Group B
PortC (Lower) 1 = Input 0 = Output PortB 1 = Input 0 = Output Mode Selection 0 = Mode 0 1 = Mode 1

88

8255
Programmable Peripheral Interface
Control Word
BSR Mode

D7 D6 D5 D4 D3 D2 D1 D0

Bit Set/Reset X X X
Not Used 1 = Set 0 = Reset

Bit Select
000 = Bit 0 001 = Bit 1 010 = Bit 2 011 = Bit 3 100 = Bit 4 101 = Bit 5 110 = Bit 6 111 = Bit 7

0
BSR Mode Selected

SKB's

89

8255
Programmable Peripheral Interface
Mode 0 :-

SKB's

90

8255
Programmable Peripheral Interface
Mode 1 :-

SKB's

91

8255
Programmable Peripheral Interface
Mode 2 :-

SKB's

92

8253
Programmable Interval Timer

3 Independent 16bit Counters DC - 2.6MHz BCD or Binary Counting Programmable Counting Modes Single Supply Operations

SKB's

93

8253
Programmable Interval Timer
Pin Diagram :-

SKB's

94

8253
Programmable Interval Timer
Block Diagram :-

SKB's

95

8253
Programmable Interval Timer
System Interface :-

SKB's

96

8253
Programmable Interval Timer
Control Word
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

Read / Load
00 = Counter Latching 01 = Read/Load MSB only 10 = Read/Load LSB only 11 = Read/Load LSB first then MSB

Binary / BCD
1 = BCD 0 = Binary

Mode Select
000 = Mode 0 001 = Mode 1 X10 = Mode 2 X11 = Mode 3 100 = Mode 4 101 = Mode 5

Select Counter
00 = Select Counter 0 01 = Select Counter 1 10 = Select Counter 2 11 = Illegal SKB's

97

8253
Programmable Interval Timer
Mode 0 :-

SKB's

98

8253
Programmable Interval Timer
Mode 1 :-

SKB's

99

8253
Programmable Interval Timer
Mode 2 :-

SKB's

100

8253
Programmable Interval Timer
Mode 3 :-

SKB's

101

8253
Programmable Interval Timer
Mode 4 :-

SKB's

102

8253
Programmable Interval Timer
Mode 5 :-

SKB's

103

8279
Programmable Keyboard / Display Interface

Simultaneous Keyboard & Display Drive Scanned Keyboard Mode Scanned Sensor Mode 8-Character Keyboard FIFO Duel 8 / 16 Numerical Display R / L Entry 16 bit Display RAM Mode Programmable From CPU Programmable Scan Timing Interrupt Output on Key Entry
SKB's 104

8279
Programmable Keyboard / Display Interface
Pin Diagram :-

SKB's

105

8279
Programmable Keyboard / Display Interface
Signal Diagram :-

SKB's

106

8279
Programmable Keyboard / Display Interface
Block Diagram :-

SKB's

107

8279
Programmable Keyboard / Display Interface
System Interface :-

SKB's

108

8251
Programmable Communication Interface
Pin Diagram :-

SKB's

109

8251
Programmable Communication Interface
Block Diagram :-

SKB's

110

8251
Programmable Communication Interface
System Interface :-

SKB's

111

8251
Programmable Communication Interface

Mode Instruction Format

SKB's 112

8251
Programmable Communication Interface

Command Instruction Format SKB's

113

UNIT - V

SKB's

114

1) Stepper Motor Control 2) Matrix Keyboard 3) Dynamic 7 Segment Display 4) Analog to Digital converter 5) DC Motor Control 6) LCD Display 7) Serial Data Transfer
SKB's 115

STEPPER MOTOR CONTROL

Stepper Motor Winding Diagram Specifications Rotation / Excitation methods Clockwise / Anti Clockwise Sequence Single & Multi Winding Excitation Driving unit Digital & Analog

STEPPER MOTOR CONTROL

W1 1 0d 0 1 1 0 0 1 W2 1 1 0 0 1 1 0 0 W3 0 1 1 0 0 1 1 0 W4 0 0 1 1 0 0 1 1

STEPPER MOTOR CONTROL

MATRIX KEYBOARD
General Keyboard Structure Adv & Disadv of General Keyboard Layout of Matrix Keyboard Scanning and Sense Lines Scan Sequence Key De-bounce Methods

MATRIX KEYBOARD DRIVER

Scan Lines Sense Lines

7 8 9 5 6

MATRIX KEYBOARD

0 #

2 3

MATRIX KEYBOARD
Sense Lines RL2 RL1 RL0 SL0 Scan Lines

1 4 7

2 5 8 0

3 6 9 #

SL1

SL2 SL3

MATRIX KEYBOARD
SL3 SL2 SL1 SL0 RL2 RL1 RL0
0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0

1 2 3 4 5
RL2 RL1 RL0 SL0 SL1

0 0 0 01

0 0 1 0

0 1 0 0

1 0 0 0

0 1 0 0 1 0 0

1 4 7

2 5 8 0

3 6 9 #

1
0 0

0
0 1

0
1 0

6 7 8 9
0

SL2 SL3

MATRIX KEYBOARD

MATRIX KEYBOARD

DYNAMIC 7 SEGMENT DISPLAY

Seven Segment Display Eight LEDs Two types Common Anode & Common Cathode Dynamic Seven Segment Display Scan Sequence

DYNAMIC 7 SEGMENT DISPLAY

Seven Segment Display
a f b

gV
e d dp c

dp

Common

DYNAMIC 7 SEGMENT DISPLAY

DYNAMIC 7 SEGMENT DISPLAY

DYNAMIC 7 SEGMENT DISPLAY

ANALOG TO DIGITAL CONVERTER

ADC Working Types Applications Specifications No of Bits, i/p, o/p etc

ANALOG TO DIGITAL CONVERTER

DIGITAL TO ANALOG CONVERTER

DC MOTOR CONTROL
DC Motor Speed Control Methods Advantage of PWM Method Driving Circuit

DC MOTOR CONTROL

LCD DISPLAY
Principle of LCD 16x2 LCD LCD Module Driver & Screen RAM Character Molding Display Type Cursor, L/R Entry etc

LCD DISPLAY

LCD DISPLAY

LCD DISPLAY

Pin number
1 2 3 4

Symbol
Vss Vcc Vee RS

Level
0/1

I/O
I

Function
Power supply (GND) Power supply (+5V) Contrast adjust 0 = Instruction input, 1 = Data input 0 = Write to LCD module, 1 = Read from LCD module Enable signal Data bus line 0 (LSB)

5 6 7

R/W E DB0

0/1 1, 1->0 0/1

I I I/O

8
9 10 11 12 13 14

DB1
DB2 DB3 DB4 DB5 DB6 DB7

0/1
0/1 0/1 0/1 0/1 0/1 0/1
SKB's

I/O
I/O I/O I/O I/O I/O I/O

Data bus line 1

Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 (MSB)
139

Code Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Executi on time

Clear display Cursor home Entry mode set Display On/Off control Cursor/disp lay shift Function set Set CGRAM address Set DDRAM address Read busyflag and address counter Write to CGRAM or DDRAM Read from CGRAM or DDRAM

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 1

1 *

Clears display and returns cursor to the home position (address 0). Returns cursor to home position (address 0). Also returns display being shifted to the original position. DDRAM contents remains unchanged. Sets cursor move direction (I/D), specifies to shift the display (S). These operations are performed during data read/write. Sets On/Off of all display (D), cursor On/Off (C) and blink of cursor position character (B). Sets cursor-move or display-shift (S/C), shift direction (R/L). DDRAM contents remains unchanged. Sets interface data length (DL), number of display line (N) and character font(F). Sets the CGRAM address. CGRAM data is sent and received after this setting. Sets the DDRAM address. DDRAM data is sent and received after this setting.

1.64mS

1.64mS

I/D

40uS

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 1

0 1 DL

1
S/C

D
R/L

C * *

B * *

40uS

40uS 40uS

CGRAM address

40uS

DDRAM address

40uS

BF

CGRAM / DDRAM address

Reads Busy-flag (BF) indicating internal operation is being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction).

0uS

write data

Writes data to CGRAM or DDRAM.

40uS

read data

SKB's

Reads data from CGRAM or DDRAM.

140

40uS

LCD DISPLAY