Under the guidance of

R. Sabari Banu, M.Tech,(Ph.D) Associate Professor

By kl(08F41A0431)

CONTENTS

Objective Introduction Existing system Disadvantages of existing system Proposed system Block diagram of proposed system DMA controller Internal configuration of DMA controller Modification of CPU to work with DMA AMBA structure 3 buses of AMBA Software requirements Xilinx procedure Advantages conclution

OBJECTIVE
To implement DMA controller of AMBA.
To reduce the load on the processor while transferring

data from memory to peripheral or memory.

Save power in a system by putting CPU in low power

state.
Proposed architecture provides bus access to any one

master at a time for improved speed and performance.

INTRODUCTION
Microprocessor is able to access peripherals via a special bus called AMBA (Advanced Microprocessor Bus Architecture). AMBA has large market share is simpler in architecture than any other buses

EXISTING SYSTEM

Data transfer in a personal computer

DISADVANTAGES OF EXISTING SYSTEM

System may hang or its speed is reduced while transferring of large amount data from memory to peripheral or peripheral to memory

PROPOSED SYSTEM
To overcome the problem of existing system, we are

interfacing a DMA controller that enables transfer of data

The DMA controller for AHB of AMBA is designed in

VHDL (Verilog)

BLOCK DIAGRAM OF PROPOSED SYSTEM

DMA CONTROLLER
DMA connects directly to the I/O device at one end and to

the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections.
It is sometimes referred to as a channel. In an alternate

configuration, the DMA controller may be incorporated directly into the I/O device

INTERNAL CONFIGURATION OF DMA CONTROLLER

Modification of the CPU to work with DMA

Addition of control input BR and control output BG, along

with the logic to generate BG. The logic depends on when the designer wants the CPU to be able to grant control of the system buses to the DMA controller. Most CPUs allow DMA requests to be granted after the instruction has been fetched; after it has been decoded, after its operations have been fetched ; after the instruction has been executed, and after its results have been stored.

AMBA STUCTURE

3 BUSES OF AMBA
AHB: AHB is introduced to support high performance,

synthesis and timely verification

APB: APB is local secondary bus which appears as a

single slave module on AHB

ASB: ASB is the older form of system bus

SOFTWARE REQUIREMENTS
Language: VHDL (Verilog) Simulation tool: Xilinx

XILINX PROCEDURE
Creating a project Family Package speed Adding source to the project
Simulation Design utilities

Check syntax simulation

ADVANTAGES
Computer system performance is improved by direct

transfer of data between memory and I/O devices, bypassing the CPU.
CPU is free to perform operations that do not use

system bus

CONCLUSION
VHDL design of DMA controller AMBA Bus with multiple masters (Direct memory Access (DMA) as one of the master and another master is Host). Only one bus master either DMA or Host is allowed to actively use the bus at any one time. The DMA controller modules are implemented using VHDL, simulation and synthesis is done by Xilinx.

REFERENCES
J. Liang, Swaminathan, S, ASOC: a Scalable, Single chip

Communications Architecture, Tessier, R . Parallel Architectures and Compilation Techniques, 2000, Proceedings. International Conference, pp.37-46, 2000. [2] F. Po l mi , D . Bntazzi, L.Bmini , and A . Bogliolo. , Psrformancc Aoalysirr of Arbibation Policies for sd: Communication Architecfurcs, Kluwa Jolnnal on Design Automation for Embedded Systmu, 8, np. 2, pp. 189210,2003. [3] Flynn, D., AMBA: Enabling Reusable On-Chip Designs, IEEE Micro, 17(4), July/August 1997, pp 20-27. [4] AMBA Specification (rev2.0) and Multi Layer AHB Specification, Arm: http://www.arm.com, 2001.

THANK YOU