HDL AND ITS APPLICATIONS

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INTRODUCTION
HDL is any language from a class of computer languages and/or programmed languages for formal description of electronic circuits ,and more specially digital logic circuits It can describe the circuit operation, design and organization and tests to verify its operation by means of simulation. The first hardware description languages were ISP developed at Carnegie Mellon University, and KARL, developed at University of Kaiserslautern, both around 1977.

 ABEL HDL is developed by telecommunication research center CSELT at Torino , Italy, around 1980. VERILOG HDL was introduced by gateway design automation in 1985. In 1987, a request from the U.S. Department of Defense led to the development of VHDL.

INTERPRETATION OF HDLS
ISP
ISP (Instruction Set Processor) was, however, more like a software programming language used to describe relations between the inputs and the outputs of the design. Therefore, it could be used to simulate the design, but not to synthesize it.

KARL
KARL included design calculus language features supporting VLSI chip floor planning and structured hardware design.

ABEL
ABEL stands for Advanced Boolean Equation Logic. The ABEL HDL was made for PLD circuit design by DATA I/O and with other hardware descriptor languages come to easy the PLD design. ABEL hardware description language allows to one to describe digital designs with equations, truth tables, state diagrams, or any combinations of the three, optimize and simulate the design without specifying a device or assigning pins.

ABEL Program Structure

The complete functional description of the design it is included in the so called module. An ABEL program can have more than one module, but the environment will translate only the first module, the other modules will be checked syntactically. In one module can be specified only one PLD device.

ABEL MODULE
HEADER (module name, options, titlestring) DECLARATIONS (keyword, device, pin, node, constant, macro, library) LOGIC DESCRIPTION (equations, truth tables, state diagrams, fuses, XOR factors) TEST VECTORS (TEST_VECTOR,TRACE) END STATEMENT

VERILOG HDL
Verilog is a hardware description language (HDL), similar to VHDL that was originally written by Phil Moorby in 1984 who needed a simple, intuitive and effective way of describing digital circuit for modeling, simulation and analysis purpose. It supports the design verification as well as implementation of analog, digital and mixed signal circuits at various levels of abstraction. It is similar to C programming language, verilog is a fairly language to learn. Verilog is a case sensitive language.

 Verilog can be used to describe design at four levels of abstraction: Switch level (the switches are MOS transistor inside gates) Gate level (interconnected AND, NOR etc) Register transfer level (RTL uses registers connected by Boolean equations) Algorithmic level (much like code c with case and loop statements)

VHDL
In June 2006, VHDL Technical Committee of Accellera approved so called Draft 3.0 of VHDL2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types.

entity but_not_gate is port (X, Y: in bit; Z: out bit); end entity but_not_gate

concurrent processes signal sensitivity list

architecture behavioral of but_not_gate is begin work_cycle: process (X, Y) is begin if X = 1 and Y = 0 then Z <= 1 after 5 ns; else Z <= 0 after 5 ns; end if; end process work_cycle; end architecture behave;

entity declaration establishes external interface signal names, modes, types architecture details implementation types signals constants variables functions procedures components begin concurrent statements (processes) end

Examples:
architecture behavioral of but_not_gate is begin work_cycle: process (X, Y) is begin if X = 1 and Y = 0 then Z <= 1 after 5 ns; else Z <= 0 after 5 ns; end if; end process work_cycle; end architecture behavioral;

architecture behavioral3 of but_not_gate is begin work_cycle: process is begin loop wait on X, Y; case X = 1 and Y = 0 is when true => Z <= 1 after 5 ns; when others => Z <= 0 after 5 ns; end case; end loop; end process work_cycle; end architecture behavioral3;

Phases in a HDL design project

Timing Diagram

VERILOG VS VHDL
The language syntax is the main factor since VHDL is based on ADA and Verilog is based on C. Verilog is easier to learn since C is a far simpler language. It also produces more compact code; easier both to write and read. VHDL is very strongly typed, and allow programmer to define their own types although, in practice, the main types used are either the basic types of the language itself or those define by the IEEE. The benefit is that type checking is performed by the compiler which can reduce errors; the disadvantage is that changing types must be done explicitly.

ADVANTAGES OF VHDL OVER VERILOG

It provides a simple mechanism (the configure statement) that allows the designer to switch painless between different description of a particular module. It allows the conditional instancing of modules (if/for generate). This is one of those features that you do not miss until you have used it once and then you need it all the time. Many Verilog users recognize this lack and create personal preprocessing routine it implement it (which negates some of the advantages of a language standard).

ADVANTAGES OF VERILOG HDL OVER VHDL

It ensures that all signals are initialized to unknown which ensures that all designers will produce the necessary logic to initialize their design the base type in VHDL initialize to zero and the hasty designer may omit the global reset.

It allows switchlevel modeling which some designers find useful for exploring new circuits.

CONCLUSION
With the help of HDLs we can perform many operations. As we know that HDLs are used to operate or design digital circuits, so by using HDLs we can design and describe the digital hardware.