Microprocessor

Dr. S. A. Shinde

Microprocessors
Microprocessors come in all kinds of varieties from the very simple to the very complex Depend on data bus and register and ALU width P could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit We will discuss two sample of it
8085 as an 8-bit P and 8086/88 as an 16-bit P

All Ps have
Address bus Data bus Control Signals: RD, WR, CLK , RST, INT, . . .

History
Bus width

4 bit

8 bit

16 bit

32 bit

64 bit

Company 8008 8080 8085 Z80 6800 6802 6809 8086/8 80186 80286 Z8000 Z8001 Z8002 68006 68008 68010

intel

4004 4040

80386 80486

80860 pentium

zilog

Motorola

68020 68030 68040

Internal and External Bus

Internal bus is a pathway for data transfer between registers and ALU in the Ps External bus is available externally to connect to RAM, ROM and I/O Int. and Ext. Bus width may be different For example
In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit

Microprocessor Architecture
The microprocessor can be programmed to perform functions on given data by writing specific instructions into its memory.
The microprocessor reads one instruction at a time, matches it with its instruction set, and performs the data manipulation specified. The result is either stored back into memory or displayed on an output device.

Functional Block Diagram 8085

Input/Output Signals of 8085

The 8085 Architecture

All signals can be classified in to 6 groups: Address bus Data bus Control and Status signals Power supply & Frequency signals Externally initiated signals Serial I/O ports

The 8085 Architecture

The 8085 microprocessor has 2 differentiators
The low order address bus of 8085 is multiplexed with the data bus. The bus need to be Demultiplexed Appropriate control signals need to be generated to interface memory and I/O with the 8085

The 8085 Architecture

Multiplexed Address/Data bus The signal lines AD7 AD0 are bidirectional, they are used as low order address bus as well as the data bus During the execution an instruction - In Early Cycle, it will be Address bus - Later Cycle(s), it will be Data bus

The 8085 Architecture

Control & Status signals 2 control signals - RD & WR 3 status signals - IO/M, S1 & S0 to identify the nature of the operation 1 special signal - ALE to indicate the operation ALE - This positive pulse is generated every time the 8085 begins an operation. It indicates that the bits on AD7 AD0 are address bits. This signal latches the low order address from the multiplexed bus and generates a separate set of eight address lines A7 A0. RD - This is active low control signal, this signal indicates a read data from I/O or memory WR - This is active low control signal, this signal indicate that the data on the data bus will be written onto the I/O or memory IO/M - This status signal is used to differentiate between the IO and memory. When it is high IO will be selected. If low, then memory is selected. This signal is combined with RD & WR for read or write operation S1 & S0 - status signals, used for identifying various operations

The Internal Architecture

The Program Counter (PC) (16 bit)
This is a register that is used to control the sequencing of the execution of instructions. This register always holds the address of the next instruction. Since it holds an address, it must be 16 bits wide.

The Internal Architecture

The Stack pointer
The stack pointer is also a 16-bit register that is used to point into memory. The memory this register points to is a special area called the stack. The stack is an area of memory used to hold data that will be retreived soon. The stack is usually accessed in a Last In First Out (LIFO) fashion.

Externally Initiated Operations

External devices can initiate (start) one of the 4 following operations:
Reset
All operations are stopped and the program counter is reset to 0000.

Interrupt
The microprocessors operations are interrupted and the microprocessor executes what is called a service routine. This routine handles the interrupt, (perform the necessary operations). Then the microprocessor returns to its previous operations and continues.

Externally Initiated Operations

Ready
The 8085 has a pin called RDY. This pin is used by external devices to stop the 8085 until they catch up. As long as the RDY pin is low, the 8085 will be in a wait state.

Hold
The 8085 has a pin called HOLD. This pin is used by external devices to gain control of the busses. When the HOLD signal is activated by an external device, the 8085 stops executing instructions and stops using the busses. This would allow external devices to control the information on the busses. Example DMA.

The 8085 Architecture

Power supply and Clock frequency:Vcc = + 5v Vss = Ground/Gnd/0 Volts X1, X2: with RC/LC network to operate system - 3MHz to 6MHz CLK - Clock output, used as system clock for other devices

8085 Notes - Externally initiated Signals including Interrupts

INTR (input) - INTerrupt Request, used as a general purpose interrupt. INTA (output) - INTerrupt Acknowledge - used to acknowledge an interrupt RST 7.5, RST 6.5, RST 5.5 (inputs) - ReSTart interrupts - have higher priorities than the INTR interrupt TRAP (input) Non Maskable interrupt & has highest priority HOLD (input) - indicates that a peripherals like DMA controller is requesting for the use of address bus and data bus

8085 Notes other signals

HLDA (output) - HoLD Acknowledge - signal to acknowledge the assertion of HOLD signal READY (input) - this signal is used to delay the mP read or write cycles. When this signal goes low , the mP waits for an integral number of clock cycles until it goes high RESET IN - When this signal goes low, the PC is set to zero, the buses are tri-stated & mP is reset RESET OUT - signal indicates that the mP is being reset, more importantly used to reset all other devices Serial I/O ports SID (serial input data ) & SOD( serial output data) - data bits are sent over a single line (one bit at a time)

Pin Diagram/ Pinout of 8085

8085 Bus Architecture

8085 programmable Registers

Memory Read Operation

Demultiplexing the Bus AD7 AD0

Timing :Transfer of byte from memory to MPU

 It is important to note that the microprocessor treats memory and I/O devices the same way. Input and output devices simply look like memory locations to the microprocessor. For example, the keyboard may look like memory address A3F2H. To get what key is being pressed, the microprocessor simply reads the data at location A3F2H. The communication process between the microprocessor and peripheral devices consist of the following three steps: Identify the address. Transfer the binary information. Provide the right timing signals.

Microprocessor Initiated Operations

The Read Operation

To read the contents of a memory location, the following steps take place:
The microprocessor places the 16-bit address of the memory location on the address bus. The microprocessor activates a control signal called memory read which enables the memory chip. The memory decodes the address and identifies the right location. The memory places the contents on the data bus. The microprocessor reads the value of the data bus after a certain amount of time.

Internal Data Operations

The 8085 can perform a number of internal operations. Such as: storing data, Arithmetic & Logic operations, Testing for condition, etc.
To perform these operations, the microprocessor needs an internal architecture similar to the following:
Accumulator Flags B C D E 8 H L Program Counter Stack Pointer

Address

16

Data

The Design and Operation of Memory

Memory in a microprocessor system is where information (data and instructions) is kept. It can be classified into two main types: Main memory (RAM and ROM) Storage memory (Disks , CD ROMs, etc.) The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements). The number of flip-flops in a memory register determines the size of the memory word. ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information.

Accessing Information in Memory

For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following:
Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus).

The steps of writing into Memory

What happens when the programmer issues the STA instruction?
The microprocessor would turn on the WR control (WR = 0) and turn off the RD control (RD = 1). The address is applied to the address decoder which generates a single Enable signal to turn on only one of the memory registers. The data is then applied on the data lines and it is stored into the enabled register.

The 8085 and Memory

The 8085 has 16 address lines. That means it can address 216 = 64K memory locations.
Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.

how would we use these address lines to control the multiple chips?

Chip Select
Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of chip selection.
These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used.

Chip Selection Example

Assume that we need to build a memory system made up of 4 of the 4 X 4 memory chips we designed earlier. We will need to use 2 inputs and a decoder to identify which chip will be used at what time. The resulting design would now look like the one on the following slide.

Microcomputer Hardware
Address Bus

MAIN MEMORY MPU

Data Bus

I/O DEVICES (Ports)

Control Lines (Bus)

The 8085 and Address Ranges

The 8085 has 16 address lines. So, it can address a total of 64K memory locations.
If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations. (log21024 = 10) That leaves 6 address lines which is the exact number needed for selecting between the 64 different chips (log264 = 6).

The 8085 and Address Ranges

Now, we can break up the 16-bit address of the 8085 into two pieces: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Chip Selection Location Selection within the Chip

Depending on the combination on the address lines A15 - A10 , the address range of the specified chip is determined.

Chip Select Example

A chip that uses the combination A15 - A10 = 001000 would have addresses that range from 2000H to 23FFH.
Keep in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input:
A 10 A 11 A 12 A 13 A 14 A 15 CS

 If we change the above combination to the following:

A 10 A 11 A 12 A 13 A 14 A 15 CS

Chip Select Example

Now the chip would have addresses ranging from: 2400 to 27FF. Changing the combination of the address bits connected to the chip select changes the address range for the memory chip.

Chip Select Example

To illustrate this with a picture:
in the first case, the memory chip occupies the piece of the memory map identified as before. In the secondBefore it occupies the piece identified case, After 0000 as after. 0000
2000 23FF 2400 27FF

FFFF

FFFF

High-Order vs. Low-Order Address Lines

The address lines from a microprocessor can be classified into two types:
High-Order
Used for memory chip selection

Low-Order
Used for location selection within a memory chip.

This classification is highly dependent on the memory system design.

 All of the above discussion has been regarding memory length. Lets look at memory width. We said that the width is the number of bits in each memory word.
We have been assuming so far that our memory chips have the right width. What if they dont? It is very common to find memory chips that have only 4 bits per location. How would you design a byte wide memory system using these chips? We use two chips for the same address range. One chip will supply 4 of the data bits per address and the other chip supply the other 4 data bits for the same address.

Data Lines

8085 Interrupts

 Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device The process is asynchronous.

Interrupts

Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into:

Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)

Interrupts
An interrupt is considered to be an emergency signal that may be serviced.
The Microprocessor may respond to it as soon as possible.

What happens when MP is interrupted ?

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR.

Responding to Interrupts
Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored. Vectored: The address of the subroutine is already known to the Microprocessor Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor

The 8085 Interrupts

When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The EI instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The DI instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt. The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.

The 8085 Interrupts

The 8085 has 5 interrupt inputs.
The INTR input.
The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored

The 8085 Interrupts

Interrupt name INTR RST 5.5 RST 6.5 RST 7.5 TRAP Maskable Yes Yes Yes Yes No Vectored No Yes Yes Yes Yes

8085 Interrupts
TRAP RST7.5 RST6.5 RST 5.5 INTR INTA

8085

Interrupt Vectors and the Vector Table

An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).
The IVT is usually located in memory page 00 (0000H - 00FFH). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.

 Example: Let , a device interrupts the Microprocessor using the RST 7.5 interrupt line.
Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location The process is illustrated in the next slide..

The 8085 Non-Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4. INTA allows the I/O device to send a RST instruction through data bus. 5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction

The 8085 Non-Vectored Interrupt Process

6. Microprocessor Performs the ISR. 7. ISR must include the EI instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.

Restart Sequence
The restart sequence is made up of three machine cycles
In the 1st machine cycle:
The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction.

In the 2nd and 3rd machine cycles:

the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction.

Hardware Generation of RST Opcode

How does the external device produce the opcode for the appropriate RST instruction?
The opcode is simply a collection of bits. So, the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal.

Multiple Interrupts & Priorities

How do we allow multiple devices to interrupt using the INTR line?
The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.

The Priority Encoder

The solution is to use a circuit called the priority encoder (74LS148).
This circuit has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to the increasing index of the input.
Input 7 has highest priority and input 0 has the lowest.

The 3 outputs carry the index of the highest priority active input. Figure 12.4 in the book shows how this circuit can be used with a Tri-state buffer to implement an interrupt priority scheme.

 The 8085 has 4 Masked/Vectored interrupt inputs.

RST 5.5, RST 6.5, RST 7.5
They are all maskable. They are automatically vectored according to the following table:
Interrupt RST 5.5 RST 6.5 RST 7.5 Vector 002CH 0034H 003CH

The 8085 Maskable/Vectored Interrupts

The vectors for these interrupt fall in between the vectors for the RST instructions. Thats why they have names like RST 5.5 (RST 5 and a half).

Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:
Through the Interrupt Enable flip flop and the EI/DI instructions.
The Interrupt Enable flip flop controls the whole maskable interrupt process.

Through individual mask flip flops that control the availability of the individual interrupts.
These flip flops control the interrupts individually.

Maskable Interrupts and vector locations

RST7.5 Memory RST 7.5
M 7.5

RST 6.5
M 6.5

RST 5.5
M 5.5

INTR
Interrupt Enable Flip Flop

The 8085 Maskable/Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. 4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.

The 8085 Maskable/Vectored Interrupt Process

5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. 6. The microprocessor jumps to the specific service routine. 7. The service routine must include the instruction EI to re-enable the interrupt process. 8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

Manipulating the Masks

The Interrupt Enable flip flop is manipulated using the EI/DI instructions. The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts.

SIM and the Interrupt Mask

The RST 7.5 interrupt is the only 8085 interrupt that has memory.
If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed the interrupt signal. This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt.

Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction

Triggering Levels
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a logic 1 is stored in the flip-flop as a pending interrupt. Since the value has been stored in the flip flop, the line does not have to be high when the microprocessor checks for the interrupt to be recognized. The line must go to zero and back to one before a new interrupt is recognized.

RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the microprocessor checks for interrupts.

Determining the Current Mask Settings

RIM instruction: Read Interrupt Mask
Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.

How RIM sets the Accumulators different bits

7 6 5 4 3 2 1 0

SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 RST5.5 Mask RST6.5 Mask RST7.5 Mask

Serial Data In RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending

0 - Available 1 - Masked

Interrupt Enable Value of the Interrupt Enable Flip Flop

The RIM Instruction and the Masks

Bits 0-2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5 They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in order to modify only the right mask. Bit 3 shows whether the maskable interrupt process is enabled or not. It returns the contents of the Interrupt Enable Flip Flop. It can be used by a program to determine whether or not interrupts are enabled.

The RIM Instruction and the Masks

Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5
Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins. Bit 6 returns the current value of the RST7.5 memory flip flop.

Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.

TRAP
TRAP is the only non-maskable interrupt.
It does not need to be enabled because it cannot be disabled.

It has the highest priority amongst interrupts. It is edge and level sensitive.
It needs to be high and stay high to be recognized. Once it is recognized, it wont be recognized again until it goes low, then high again.

The 8085 Interrupts

Interrupt Name INTR RST 5.5 / RST 6.5 RST 7.5 Maskable Yes Yes Yes Masking Vectored Method DI / EI DI / EI SIM DI / EI SIM None No Yes Yes Memory No No Yes Triggerin g Method Level Sensitive Level Sensitive Edge Sensitive Level & Edge Sensitive

TRAP

No

Yes

No

8255 PPI

82C55 Programmable Peripheral Interface (PPI)

Low-cost, popular component for parallel I/O in 8086/8088. Can interface any TTL device to the CPU directly. 24 pins for I/O in two groups of 12. Three distinct modes of operation

82C55 Programmable Peripheral Interface (PPI)

Three I/O ports: A, B, C
- Selected via
A1 0 0 1 1 A0 0 1 0 1 Function Port A Port B Port C Command Register

To read / write, drop CS and either RD or WR low. Select port.

82C55 Programmable Peripheral Interface (PPI)

Here:
Low bank only

A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 0 0 X X 0

Port A = C0h Port B = C2h Port C = C4h CR = C6h PCs use 60h-63h
- Speaker, timer, KB

8255 Control
Two groups
Group A = A0-A7 + C4-C7 Group B = B0-B7 + C0-C3

Three modes Mode 0, 1, 2

8255 Control
If A0=A1=1, Data becomes control byte (write only to CR) MSB=1 : Mode control D0-D2: Group B control D3-D6: Group A control (2 mode select bits) MSB=0: Allows you to set or reset any port C bit.
7 0 6 X 5 X 4 X 3 BS 2 BS 1 BS 0 S/R

Selects bit 0-7

sets/resets

8255 Control
MODE 0:
- Simple I/O operation - Port pins are assigned to be level-sensitive inputs or latched outputs. CR = 1 0 0 x x 0 x x Where the x would define the directionality of each port via the last slide.

Mode 0 control words and corresponding I/O configuration

Example

What is the mode and I/O configuration for ports A, B, and C of an 8255 after its control register is loaded with
90h? 81h? 82h?

Standard bank of eight, 7-segment displays (Figure 11-20)

Ports A & B are in mode 0 - simple latched outputs. (CR = 80h) Port A = 7 segment data inputs Port B selects which segment of the bank will display. I/O ports 0700h-0703h (via the PAL) WR pin is strobed by the PAL output as well (not shown)

15 1

14 1

13 1

12 1

11 1

10 1

9 1

8 1

7 0

6 0

5 0

4 0

3 0

2 0

1 x

0 x

 Addresses align as 8255 ports

FF00h = A FF01h = B FF02h = C FF03h = Control Reg.

Without the NAND gate here, these become:

0300h = A 0301h = B 0302h = C 0303h = Control Reg.

Other examples
Please analyze the other Mode 0 examples in the book:
- LCD interface - Stepper motor interface - Key matrix interface

Chapter 11, section 11-3

8279 Programmable keyboard/display interface

8279 Programmable keyboard/display interface

Scans and encodes up to a 64key keyboard and controls up to a 16-digit numeric display. KB Built-in FIFO (first-in, first-out) buffer (stores up to 8 keystrokes) Display - 16 x 8 RAM that stores coded display info.

8279 Functionality

8279 Programmable keyboard/display interface

A0: (INPUT) Selects data (=0) or control/status (=1) for WR/RD between CPU & 8279 BD: (OUTPUT) Blank - clears the displays CLK: (INPUT) Clock generates internal timing for the 8279. - Max frequency=3.125 MHz (8279-5) CN/ST: (INPUT) Control/strobe is an input connected to CONTROL key on KB CS: (INPUT) Chip select enables 8279 for programming, reading KB and status, and writing control and display data.

8279 Programmable keyboard/display interface

DB7-DB0: (BI) Connects to data bus of CPU IRQ: (OUTPUT) =1 whenever a key is pressed - indicates to CPU that KB data is available OUTA3-OUTA0: (OUTPUT) Sends data to the displays (MSBs) OUTB3-OUTB0: (OUTPUT) Sends data to the dislays (LSBs) RD: (INPUT) Connects directly to the IORC or RD lineswhen CS=0, causes data to be read from data registers or status register.

8279 Programmable keyboard/display interface

RESET: (INPUT) Connects to the RESET line of the system RL7-RL0: (INPUT) senses any key depression in the KB SHIFT: (INPUT) Connects to the SHIFT key on KB SL3-SL0: (OUTPUT) Scans both KB and displays WR: (INPUT) Connects write strobe logic. Causes data to be written to the data or control registers Vcc/Vss: +5V/GND

Keyboard Interface
KB matrix range: 2x2 (4 keys) - 8x8 (64 keys) A pressed key connects one row with one column RL0-7 and SL0-2 are continuously and sequentially queried internally - looking for a closed switch Pull-up resistors are internal to the 8279

Programming the KB interface

Prior to run mode, the 8279 must be programmed to operate as described Eight control words must be programmed - the control word is chosen based on the 3 MSBs of number sent to control port (11h).

000DDMMM - Mode Set

DD - selects mode of operation of a display
- Left/right entry means data is scrolled in from the left/right

MMM - selects mode of operation for the KB

-2-key lockout prevents 2 keys to be pressed together - N-key rollover will accept all keys pressed simultaneously, from first to last. - Decoded means SL outputs are active low and only one is low at a time (1110, 1101, ) - Strobed means CN/ST can be strobed to queue RL inputs.

Other Control Words

001PPPPP - Divides the clock input (CLK) by the value PPPPP to obtain internal clock rate
- Input clock of 1MHz / 01010b = 100kHz internal

010Z0AAA - Read FIFO control: selects address of keystroke (000-111) from internal FIFP buffer; Z selects auto-increment. 011ZAAAA - Display read control: selects read address from one of the display RAM positions; Z selects auto-increment used is info in display RAM must be read. 100ZAAAA - Display write control: AAAA addresses the position in RAM to be written 1010WWBB - Display write inhibit: inhibits writing to either half of the display RAM location. 1100CCFA - Clear control. 111E000 - Clear IRQ pin.

8086MP
U? 33 22 19 21 18 MN READY CLK RESET INTR 16 AD0 15 AD1 14 AD2 13 AD3 12 AD4 11 AD5 10 AD6 9 AD7 8 AD8 7 AD9 6 AD10 5 AD11 4 AD12 3 AD13 2 AD14 39 AD15 38 A16/S3 37 A17/S4 36 A18/S5 35 A19/S6 34 BHE/S7 26 DEN 27 DT/R 28 M/IO HLDA HOLD NMI TEST 8086MIN 32 RD 29 WR 25 ALE 24 INTA

16_bit Data Bus 20_bit Address

30 31 17 23

PROGRAMING MODEL As a programmer of the 8086 or 8088 you must become familiar with the various registers in the EU and BIU.

8086 Pin Assignment

Vcc (pin 40) : Power

8086 Pin Description

Gnd (pin 1 and 20) : Ground AD0..AD7 , AD8..AD15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX (input) : Indicates Operating mode READY (input , Active High) : take P to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the P immediately terminate its present activity. TEST (input , Active Low) : Connect this to HIGH HOLD (input , Active High) : Connect this to LOW (BR) HLDA (output , Active High) : Hold Ack (BG) INTR (input , Active High) : Interrupt request INTA (output , Active Low) : Interrupt Acknowledge NMI (input , Active High) : Non-maskable interrupt

8086 Pin Description

DEN (output) : Data Enable. It is LOW when processor wants to receive data or processor is giving out data (to74245) DT/R (output) : Data Transmit/Receive. When High, data from P to memory When Low, data is from memory to P (to74245 dir) IO/M (output) : If High P access I/O Device. If Low P access memory RD (output) : When Low, P is performing a read operation WR (output) : When Low, P is performing a write operation ALE (output) : Address Latch Enable , Active High Provided by P to latch address When HIGH, P is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines

Register Set
A : Accumulator Register F : Flag register Two sets of six general-purpose registers
may be used as 8-bit A F B C D E H L (A F B C D E H L)

or in pairs as 16-bit AF BC DE HL (AF BC DE HL)

The Alternative registers (A F B C D E H L) not visible to the programmer but can access via:
EXX EX AF, AF (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL') (AF)<->(AF')

Register Set(cont)
4 (16-bit) registers hold memory address (pointers)
index registers (IX) and (IY) are 16-bit memory pointers 16 bit stack pointer (SP) Program counter (PC)

Program counter (PC)

PC points to the next opcode to be fetched from ROM when the P places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location

Special purpose registers

I : Interrupt vector register. R : memory Refresh register

Flag Register
S Sign Flag (1:negativ)* Z Zero Flag (1:Zero) P Parity Flag (1: Even) V Overflow Flag (1:Overflow)* N Operation Flag (1:previous Operation was subtraction)** C Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand) *: 2-complement number representation **: used in DAA-operation for BCD-arithmetic
7 6 5 4 3 2 1 0

S Z X H X

P V

N C

H Half Carry Flag (1: Carry from Bit 3 to Bit 4)**

Instruction cycles, machine cycles and T-states

Instruction cycle is the time taken to complete the execution of an instruction Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency) f= 4MHZ T-state=0.25 uS

Basic CPU Timing Example

Opcode Fetch Bus Timings (M1 Cycle)

The R register
Is increased at every first machine cycle (M1). Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same Bit 7 can be changed using the LD R,A instruction. LD A,R a nd LD R,A access the R register after it is increased R is often used in programs for a random value, which is good but of course not truly random.

Memory read/write cycle

Adding One Wait State to an M1 Cycle

Adding One Wait State to Any Memory Cycle

IO read/write cycle

During I/O operations a single wait state is automatically inserted

Bus Request/Acknowledge Cycle

Interrupt Request/Acknowledge Cycle

Two wait states are automatically added to this cycle

Non-Maskable Interrupt Request Operation

Interrupts
There are two types of interrupts: non mask-able (NMI)
Could not be masked Jump to 0066H of memory

mask-able(INT)
Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2

 Mode 0:

Interrupt Modes

An 8 bit opcode is Fetched from Data BUS and executed The source interrupt device must put 8 bit opcode at data bus 8 bit opcode usually is RST p instructions

Mode 1:
A jump is made to address 0038h No value is required at data bus

Mode 2:
A jump is made to address (register I 256 + value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vector

Addressing Modes
Immediate Immediate Extended Modified Page Zero Addressing (rst p) Relative Addressing
Jump Relative (2 byte)
One Byte Op Code 8-Bit Twos Complement Displacement (A+2)

Extended Addressing
Absolute jump
One byte opcode 2 byte address

Indexed Addressing
(Index Register + Displacement) (IX+d) 2 byte opcode 1 byte displacement

Addressing Modes(cont.)
Register Addressing
LD C,B

Implied Addressing
Op Code implies other operand(s) ADD E

Register Indirect Addressing

16-bit CPU register pair as pointer (such as HL) ADD (HL)

Bit Addressing
set, reset, and test instructions. SET 3,A RES 7,B

Introduction to MICROCONTROLLERS
Dr. Y .Narasimha Murthy Ph.D Sri Saibaba National College (Autonomous) ANANTAPUR-515001(A.P)

Overview
Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 I/O Port Programming Timer Interrupt

Microprocessors
General-purpose microprocessor
CPU for Computers No RAM, ROM, I/O on CPU chip itself Example Intels Data Bus x86, Motorolas CPU 680x0
GeneralPurpose Microprocessor RAM ROM I/O Port Timer Serial COM Port

Address Bus

Microcontrollers
A smaller computer On-chip RAM, ROM, I/O ports... Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU RAM ROM Serial Timer COM Port

I/O Port

A single chip Microcontroller

Many ICs in to One IC !!!

Microprocessor vs. Microcontroller

Microprocessor


Microcontroller
CPU, RAM, ROM, I/O and timer are all on a single chip Fixed amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical Dedicated -purpose

  

CPU is stand-alone, RAM, ROM, I/O, timer are separate designer can decide on the amount of ROM, RAM and I/O ports. expansive versatility general-purpose

HOW MANY MICROCONTROLLERS !!???

Who are ???

Atmel ARM Intel 8-bit 8XC42 MCS48 MCS51 8xC251 16-bit MCS96 MXS296 National Semiconductor COP8 Microchip 12-bit instruction PIC 14-bit instruction PIC PIC16F84 16-bit instruction PIC NEC Motorola 8-bit 68HC05 68HC08 68HC11 16-bit 68HC12 68HC16 32-bit 683xx Texas Instruments TMS370 MSP430 Zilog Z8 Z86E02

MCS-51 Family of Microcontollers

Feature 8751
ROM Eprom RAM TIMERS I/O PINS
SERIAL PORTS INTERRUPT SOURCES

8031
NO

8051
4kB

8052
8kB 256 3 32 1
8

4kB UV 128 2 32 1
6

128 Bytes 128 2 2 32 32 1 1

6 6

 In 1983 INTEL Introduced 16-bit microcontroller namely 8096 Later INTEL introduced 80c196 series of 16-bit microcontrollers for mainly industrial applications 32-bit microcontrollers have been developed by IBM and Motorola-MPC 505 is a 32-bit RISC controller of Motorola The 403 GA is a 32 -bit RISC embedded controller of IBM

Block Diagram of Microcontroller-8051 MicrocontrollerExternal interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU

OSC

Bus Control

4 I/O Ports

Serial Port

P0 P1 P2 P3

TxD RxD

Address/Data

Block Diagram-8051

Pin Description of the 8051

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

8051

Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL

Memory mapping in 8051

ROM memory map in 8051 family

4k
0000H 0000H

8k
0000H

32k

0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

RAM memory space allocation in the 8051

7FH
Scratch pad RAM

30H 2FH
Bit-Addressable RAM

20H
1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0

TMOD Register:

   

Gate : When set, timer only runs while INT(0,1) is C/T : Counter/Timer select bit. M1 : Mode bit 1. M0 : Mode bit 0.

high.

TCON Register:

       

TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag.

Interrupts

Interrupt Enable Register :

       

EA : Global enable/disable. --: Undefined. ET2 :Enable Timer 2 interrupt. ES :Enable Serial port interrupt. ET1 :Enable Timer 1 interrupt. EX1 :Enable External 1 interrupt. ET0 : Enable Timer 0 interrupt. EX0 : Enable External 0 interrupt. .

Books that have helped me to understand the embedded systems :

1) Barr, Michael, Programming embedded sytems in C and C++ - OReilly Publ. 2) Raj Kamal, Embedded systems, TMG 3) Valvano, Introduction to Embedded microcomputer systems, Thomson Publ.

4) Mazidi and Mazidi, The 8051 microcontroller and embedded sytems Pearson education. 5) Peatman,J.B. Design with microcontrollers and microcomputers, McGraw Hill 6) Sewart. J.W. The 8051 Microcontroller Hardware, Software and Interfacing Prentice Hall 7) Ayala Kenneth, The 8051 Microntroller Architecture, Programming and Applications Delmar Publ. 8) Ajay Deshmukh, Microcontrollers TATA McGraw Hill

Rajkamal, Microcontrollers - Architecture, Programming Pearson Publ. 10) Myke Predko, Programming the 8051 Microcontroller McGraw Hill 11) Michael J. Pont, Embedded C - Addison Wesely Publ. 12) Steve Heath, Embedded system design Heinemann Publ. 13) Frank Vahid, Embedded systems a unified hardware/software Introduction John Wiley and sons Publ. 14) Barnett Cox & Ocull, Embedded C Programming & the Microchip PIC, Thomson Delmar Learning.
9)

Website References
1. 2. 3. 4. 5. 6.

7. 8.

http://www.eg3 http://www.eg3.com http://www.ARM.MCU.com http://www.mcjournal.com http://www.iar.com http://www.keil.com http://www.semiconductors.philips.com/ microcontrollers http://www.embedded.com http://www.powersoftsystems.com

Epilogue
The woods are lovely, dark and deep, But I have promises to keep, And miles to go before I sleep, And miles to go before I sleep. ---- Robert Frost GOOD LUCK!