COE305 Chapter 9

WK 3
Chapter 9
8086/8088 Hardware Specifications
Brey: The Intel Microprocessors, 7e
2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Objectives
Describe the functions of all 8086/8088 pins Understand DC characteristics and fan out Using the clock generator 8284A chip Connect buffers and latches to the buses Interpret timing diagrams Describe wait states and design their circuits Explain difference between minimum and maximum modes of using the 8086/8088 Introduce the 8087 floating point processor
The 8086/8088
Fairly old microprocessors, but still considered a good way to introduce the Intel family Both microprocessors use 16-bit registers and 20-bit address bus (supporting 1 MB memory), but: - The 8086 (1978): 16-bit external data bus - The 8088 (1979): 8-bit external data bus Still used in embedded systems (cost is less than $1)
Brey: The Intel Microprocessors, 7e 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Maximum mode Minimum mode 2 Modes: Operation with a 8/9 pins have Math Coprocessor Different Basic Functions Operation Depending On the mode Pin budget: 8086, Min mode: 20 16 20 3 Address Data Control & Status Power
I/P Selects Min/Max Mode
59 Total > 40 pins available Use multiplexing
8086
8088
DC Pin Characteristics: Voltages

Standard TTL Output and Input Voltage Levels
Vcc
1 Logic Level 1 Logic Level
5.0 V
1-Level Noise Margin Guaranteed Output Levels Forbidden Forbidden Region Accepted Input Levels 0-Level Noise Margin
0 Logic Level
DC Pin Characteristics: Currents

Fan out for a standard TTL output How many inputs can an output support?
For the 0 logic Level: (output sinks current) Standard TTL Gate
OFF O/P can sink up to 16 mA max I/P An I/P sources up to 1.6 mA
0
ON
0-level Fanout = Maximum number of inputs that the output can support = 16 mA/1.6 mA = 10 For the 1 logic Level: (output sources current) If different, take the smallest of the two numbers
ON
O/P can source up to 400 QA max
1
OFF
I/P sinks up to 40 QA Education, 1-Level fan out = 10 Rights Reserved. 2006 Pearson Upper Saddle River, NJ 07458. All also
8088/86 Pin Characteristics: DC

Output pins
Guaranteed Output levels Accepted Input pins Input levels
* # * = 1.6 mA for standard 74 TTL # = 40 QA for standard 74 TTL QP

0 level noise margin = 0.8 0.45 = 0.35 V (QP) but = 0.8 0.40 = 0.40 V (for standard 74 TTL O/P) Standard 74 TTL
Gate
* = 16 mA for standard 74 TTL # = 0.40 V for standard 74 TTL 8086/88 Qp does not strictly comply with the DC characteristics of the TTL family
A processor output can drive: One Standard 74XX input, or One 74SXX input, or Five 74LSXX inputs, or +: Current into pin (sink) Ten 74ALSXX inputs, or - : Current out of pin (source) Ten 74HCXX inputs
0 level fan-out to TTL gate = 2 z 1.6 } 1 (8086/88 QP) but = 16 z 1.6 = 10 (for standard 74 TTL O/P)
Two problems: - Lower fanout - Lower noise margin
8088/86 Pin Characteristics: DC

Input pins are TTL compatible and source(0)/sink(1) only 10 A of current (actually better than TTL!) Output pins are TTL fully compatible at logic 1, but have problems at logic 0: - A higher maximum logic 0 voltage of 0.45 V (instead of the TTL standard of 0.4 V) This reduces logic 0 noise margin from 400 mV to 350 mV be careful with long wiring from output pins - A lower logic 0 sink current of 2.0 mA (instead of the 16 mA for the standard 74 TTL) This reduces fan out capability for standard TTL loads better use 74LS, AL, or HC circuits for interfacing, or use buffers
The Buses: Address & Data

Address, A (for memory & I/O) y Control lines y Status, S
Address
y Data, D
Some functions are multiplexed on the same pins to reduce chip pin count
AD15-0 Pins - 86
Data
Write Cycle
LatchLatch address o/ps to a buffer ALE: address to a buffer
For both QPs: Address bus signals are A0-A19 (20 lines) for 1M byte of addressing space Data bus signals are - D0-D7 for the 8088 - D0-D15 for the 8086 The address & data pins are multiplexed as: - AD0-AD7 (8088) - or AD0-AD15 (8086) Address/Status pins are MUXed - A/S for A16-19 (both QPs) The ALE O/P signal is used to demultiplex the address/data (AD) bus and the address/status (A/S) bus.
86
88
The Status (S) Bus

Status bits ALE: Latch address, #BHE o/ps to a buffer
86: #S0-S2, S3-S7 88: #S0-S2, S3-S6, #SS0
86: Address bits A16-A19 & #BHE: muxed with the status bits S3-S7.
Indicates status of processor and bus cycle
S3 & S4 indicate which segment register is used with the current instruction:
S5 = the IF (Interrupt flag) bit in FLAGS S6: 0 Spare #S0,1,2 are not MUXed. They encode bus status (current bus cycle) S7: 1 Available only in the MAX mode for use by a bus controller chip
Brey: The Intel Microprocessors, 7e 2006 #SS0: Not Muxed, Min mode Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Main Control Signals

1. Signals that are common to both MIN and MAX modes:
The read output (#RD) (i.e. RD): indicates a read operation Note: The write (#WR) output: indicates a write (a MIN/MAX output) The READY input: when low (= not ready), forces the processor to enter a wait state. Facilitates interfacing the processor to slow memory chips
# or
= Active low signal
Main Control Signals, Contd.

Two hardware interrupt inputs: INTR input: Hardware interrupt request. Honored only if the IF flag is set. The Qp enters an interrupt ACK cycle by lowering the #INTA output The IF flag bit is set (to enable interrupts) by the STI instruction, and cleared by CLI NMI input: Hardware nonmaskable interrupt request. Honored regardless of the status of the IF flag. Uses interrupt vector 2
Test for low
#TEST input: Example: interfacing the QP with the 8087 math coprocessor. Checked by the WAIT instruction that precedes each floating point instruction. If high, the instruction waits till input signal goes low and then gives FP Brey: Theinstruction to 7e Intel Microprocessors, the math processor
8086 processor
#TEST
Busy O/P
8087 Math Coprocessor
Synchronizes processor execution to external events

Main Control Signals, Contd.

CLK input: Basic timing clock for the processor. 1:3 duty cycle (Get from clock generator chip) MN/#MX input: Selects either Minimum (+ 5V directly) or Maximum mode (GND) #BHE/S7 output (MUXed): #BHE: (Bus High Enable) Enables writing to the high byte of the 16-bit data bus on the 8086 Not on 8088 (it has an 8-bit data busno high byte!) RESET input: resets the microprocessor (to reboot the computer). Causes the processor to start executing at address FFFF0H (Start of last 16 bytes of ROM at the top of the 1MB memory) after disabling the INTR input interrupts (CLR IF flag). Input must be kept high for at least 50 Qs. Sampled by the processor at the + ive clock edge (Get from clock generator chip)
2. The 8/9 Signals that depend on mode: Their Min Mode States
For the processor to operate in the minimum mode, connect MN/#MX input directly to +5V. Their min mode states: M/#IO or IO/#M output: indicates whether the address on the address bus is a memory address (IO/#M = 0) or an I/O address (IO/#M = 1) #WR output: indicates a write operation. #INTA output: interrupt acknowledgement. Goes low in response to a hardware interrupt request applied to the INTR input. Interrupting device uses it to put the interrupt vector number on the data bus. The Qp reads the number and identifies the ISR* Note: Address on the bus can be either for ALE (address latch enable) output: Indicates that the muxed memory or I/O devices. M/#IO signal indicates which one is intended by the current instruction AD bus now carries address (memory or I/O). Use to latch that address to an external circuit *ISR = Interrupt Service Routine before the processor removes it!.
Minimum Mode Signals, Contd.

For the processor to operate in the minimum mode, connect MN/#MX input directly to +5V.
DT/#R output: indicates if the data bus is transmitting (outputing) data (=1) or receiving (inputting) data (=0). Use to control external bidirectional buffers connected to the data bus. #DEN output: (data bus enable). Active when AD bus carries data not address Use to activate external data buffers. HOLD input: Requests a direct memory access (DMA) from the QP. In response, the QP stops execution and places the data, address, and control buses at High Z state (floats them). HLDA output: Acknowledges that the processor has entered a hold state in response to HOLD. #SS0 output (8088) : Equivalent QP Bidirectional to the S0 status output of the Data Buffer maximum mode. Use with IO/#M Enable Direction and DT/#R to decode the current bus cycle (Table 9-5)
#DEN DT/#R
Multiprocessor System
Clock Generator Sync

Xtal
Clock Generator
2. The 8/9 Signals that depend on mode: Their Max Mode States
For the processor to operate in the minimum mode, connect MN/#MX input to ground.
#S0,#S1,#S2 outputs: Status bits that encode the type of the current bus cycle, Used by the 8288 bus controller and the 8087 coprocessor (Table 9-6) #RQ/GT0, #RQ/GT1: Bidirectional lines for requesting and granting access to a shared bus (Request/Get). For use in multiprocessor systems. The RG/GT0 line has higher priority #LOCK output: Activated for the duration of QP instructions having the LOCK prefix. Can be used to prevent other microprocessors from using the system buses and accessing shared memory or I/O for the duration of such instructions, e.g. LOCK:MOV AL,[SI] Table 9-6 QS0, QS1 (Queue Status) outputs: indicate the status of the internal instruction queue (Table 9-7). For use by the 8087 coprocessor to keep in step with the QP. Table 9-7 Brey: The Intel Microprocessors, 7e 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Clock Generator (8284A)

Provides the following functions: Generates Clock signals:
- Generates a CLK signal for the 8086/8088 - Provides a CLK sync signal (OSC) for use by slave processors on a multiprocessor 8086/8088 systems - Provides a TTL-level peripheral clock signal (PCLK)
Provides synchronization for external input signals to the processor:

The RESET input The READY input for wait state generation
Clock Generator (8284A): Signals

Clocks & Clock Synchronization Signals
X1 and X2: Crystal Oscillator pins. Connect a crystal of the correct frequency between these two terminals to generate the clock signal. EFI: External frequency input. Signal can be used as the clocking source to the 8284A instead of the crystal oscillator. F/#C input: Selects external EFI input (1) or the crystal oscillator (0) as the clocking source for the 8284A CLK output: The clock signal produced for connecting to the CLK input on the 8086/8088. At 1/3 rd of the crystal or EFI input frequency with 1:3 duty cycle: fclock = fxtal/3 = fEFI/3 OSC: Oscillator output. Same frequency as crystal or EFI. Connect to EFIs on other 8284As in multiprocessor systems (synchronized clocks) fosc = fxtal= fEFI PCLK output: peripheral clock signal at 1/6 th of the crystal or EFI input frequency (1/2 clock freq) with 1:2 duty cycle. Use to drive peripheral equipment in the XTAL system fpclk = fxtal/6 = fEFI/6 or EFI CSYNC input: Clock synchronization input. Should be used if EFI is used, otherwise must be grounded.
Crystal
OSC: EFI To other QPs
z3
z2
PCLK to Per CLK to QP
Clock Generator (8284A): Signals

RESET Signals #RES Reset input: Active low. Usually connected to an RC circuit to provide automatic reset at power on. RESET output: Synchronized to Clk. Connect to the 8086/8088 RESET input. READY Signals #AEN1 and #AEN2 address enable inputs: Used with RDY1 and RDY2 inputs to generate the READY output. The READY output is connected to the READY input on the 8086/8088 QP to control memory wait states. #ASYNC input: for READY output synchronization. Selects 1 or 2 stages of synchronization for the RDY1 and RDY2 inputs.
To QP
Clock Generator (8284A): Block Diagram

RESET
Switch/RC circuit Hysteresis to avoid jitter due to slowly varying inputs Starts 4 clock pulses max after power up Must be kept High for at least 50 Qs Schmitt trigger Active High, to QP Inverting buffer Use as EFI in Multiprocessor systems
CLOCK & Sync
Crystal Select clocking source
Synchronize with ive clock edge
Select Crystal Osc or EFI External Frequency I/P Synchronize clock if EFI is used with multiprocessor systems
z3
z2
Peripheral Clock. f = 1/6th of crystal or EFI Frequency, 1:2 duty cycle
READY
To processor CLK input. f = 1/3rd of crystal or EFI Frequency, 1:3 duty cycle
0 = 2 stages, 1 = 1 stage of synchronization

Typical Application of the 8284A for clock and Reset signal generation
frequency, f
f/3
2.5 MHz
Grounded when Xtal Osc is used
PCLK
OSC
f/6 f
15 MHz
R
Synced To CLK
RESET
Manual 50 Qs Effective Reset Digital Minimum RC time constant large enough #RES Input push button for 50 Qs min Reset pulse Switch at Brey: The Intel Microprocessors, 7e worst trigger conditions (1.05 V Threshold) 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
RC circuit for automatic Reset on power up
Bus Demultiplexing and Buffering

Demultiplexing: The address/data and address/status buses are multiplexed to reduce the device pin count. These buses must be demultiplexed (separated) to obtain the signals required for interfacing other circuits to the QP
Use the ALE output from the microprocessor to latch the address/status information that appear briefly on the multiplexed bus This makes the latched address information available for long enough time for correct interfacing, e.g. to memory
Buffering: Fan out is limited, so output signals should be buffered in large systems
Demultiplexing the 8088 Processor

Using the ALE signal to Demultiplex: -The Address lines A0-7 from the AD0-7 muxed bus -The A16-19 lines from the A16/S3-A19/S6 muxed bus
20-bit Not Muxed Data Latch (Transparent) Delay Demuxed A0-A7 Latch I/P Output Enable
Octal D-type Transparent Latch (not edge triggered)
Memory write cycle for the 8088 (non-muxed line are not shown) Data and address lines must remain valid and stable for the duration of the cycle 74373 is an Octal D-type transparent Latch with 3-state outputs
Feature Not utilized!
Use as data bus, with #DEN active
Demultiplexing the 8086 Processor Address/Data bus
20-bit
16-bit
with #DEN active
D O/P Transparency
Last O/P Maintained (latched)

Buffering
Since the microprocessor output pins provide minimum drive current at the 0 logic level, buffering is often needed if more TTL loads are connected to any bus signal: Consider 3 types of signals For demuxed signals: Latches used for demuxing, e.g. 373, can also provide the buffering for the demuxed lines:So, Fan out = ?
0-level output can sink up to 32 mA (20 x 1.6 mA loads) 1-Level output can source up to 5.2 mA (1 load = 40 QA)
Which case sets the limit?
For non-demuxed unidirectional (always output) address and control signals (e.g. A8-15 on the 8088), buffering is requiredoften using the 74ALS244 (unidirectional) buffer. For non-demuxed bidirectional data signals (pin used for both in and out), buffering is often accomplished with the 74ALS245 bidirectional bus buffer Caution: Buffering introduces a small delay in the buffered signals. This is acceptable unless memory or I/O devices operate close to the maximum bus speed
Fully DeMuxed and buffered 8088

Non-DeMuxed Address Lines (unidirectionalAlways O/Ps)
244 Buffer 74244 is an Octal Buffer with 3-state outputs

Feature Not utilized!
DeMuxed Address Lines (unidirectionalAlways O/Ps) Latch provides the buffering
A B isolation with G = 1
74245 is an Octal Bus Transceiver with 3-state outputs

Feature utilized!
Non-Demuxed Bidirectional Data Lines
245 Buffer
DIR Direction 1: A B 0: A B 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Enable external buffers
Fully DeMuxed and buffered 8086
(Not Transceivers)
Use to determine Fanout
A-B: Open circuit, No connection 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Bus Timing Timing in General

A data transfer operation to/from the QP occupies at least one bus cycle Each bus cycle consists of 4 clock cycles, T1, T2, T3, T4, each of period T With 5 MHz processor clock: - T = 1/5 MHz = 0.2 Qs - Bus cycle = 4 T = 0.8 Qs
- Max rate for memory and I/O transactions = 1/0.8 = 1.25 M operations per sec (Fetch speed). - Processor executes 2.5 Million Instructions per sec (MIPS) (Execute speed) Fetch is slower than execute. Effect on pipelining?
Clock Cycle
Bus Timing in General, Contd.

T1: Note: #RD,#WR,#INTA - Address is emitted from the Processor are all inactive high during T1 - Control signals such as ALE, DT/#R, IO/#M, etc. are also initiated T2 - Used primarily for changing Clock Cycle the direction of the AD bus TW T3 T4 during read operations ( then ) - Read or write controls are setup, Read Data Read Data Check READY e.g. #DEN, #RD (#INTA) or #WR (Normal) (with Wait) * If a Write operation, Data to be written is put on the bus for the external device to take * If a Read operation, AD bus is floated, so external device can put the read data on it T3 & T4: Actual Data transfers occur during T3 & T4. - In Read operations, Data In on the data bus is normally strobed into the processor at the start of T4 - In Write operations, Data out on the bus is strobed into the external device at the trailing edge of the #WR signal Wait States: If addressed device is too slow to allow normal data transfer, it sets READY input low (NOT READY) * The processor samples the READY input at the end of T2. If found low, T3 is considered a Wait'' state (TW). Ready is checked again at the middle of that wait state. If high, it is followed by proper T3 and T4. If low (not ready), the next clock cycle is considered an additional wait state, and so on Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Brey: The Intel Microprocessors, 7e 2006
Timing in General: Read & Write with waits

WK 5 Read Cycle with 1 TW
X TW
Write Cycle with 1 TW

X TW
Latch Sample the READY I/P Address
Latch Address
Muxed Lines
QP strobes data in HiZ
, #INTA
Data Buffer Direction Enable Data Buffers

WR
IN
OUT Address O/P Data
Address O/P
Data
Device strobes data in Note: #RD,#WR,#INTA are all inactive high during T1 Education, Upper Saddle River, NJ 07458. All Rights Reserved. Brey: The Intel Microprocessors, 7e 2006 Pearson
Bus Timing, Contd. Basic Data Read Timing

Timing for a basic Read cycle Can be for either memory or I/O On the 8088: - For memory, IO/#M = 0 - For I/O: IO/#M = 1
Also DT/#R = 0
QP strobes data in
To Device
Bus
Or I/O Device
QP floats bus (HiZ)
Detailed Memory READ Timing for the 8088

t=0
Standard Bus Cycle = 4T, No Wait States

Start of T4
Valid Address A15-A8 Not Muxed A19-A16 Muxed
2. Latch/Buffer Delay Time 1. Valid Address Delay Time 3T for the processor To get data from memory Maximum allowed memory access time A7-A0 Muxed Read
Latch MUXed Address Lines 3. Setup Time QP strobes data in
READY Timing Assume No Waits Required Hold Time
Max Memory Access Time
Data Bus Direction: In Enable Data bus

SeeFig.Pearson Education, Upper SaddleTiming07458. All Rights Reserved. 2006 9-12 for Detailed River, NJ Specifications
READ Timing Budget: 8088, 5MHz Clock

It takes the processor about 3 clock cycles (3T = 3 x 200 = 600 ns with a 5 MHz clock) to take-in the memory data Not all this time is available for the memory device to retrieve the data and put it on the bus, there is: (See Fig. 9-12) Incurred 1. Address Valid Delay, TCLAV = 110 ns max Delays 2. Delay in address latch/buffer and decoders } 40 ns Required 3. Data-in Setup time (required), TDVCL = 30 ns Maximum allowed memory access time to operate without waits = 3 x 200 (110+40+30) = 420 ns If memory has a larger access time, it needs to request wait states from the processor using the READY input #RD signal should be wide enough, TRLRH = 325 ns, as there may be hold time requirements for the Data-In. #RD signal is extended with the insertion of wait states
INTA Read Timing, 8088

Similar to a memory or I/O read cycle, with #INTA replacing #RD
1. Interrupting device Raises INTR
3. Interrupting device sees this and puts a byte-long pointer to Interrupt Vector on the data bus
4. Processor latches in vector pointer from the data bus
2. Processor floats the AD7-AD0 bus and Acknowledges the Interrupt by lowering #INTA
Pointer to Interrupt Vector. Supplied by the interrupting device
Controls for a READ operation
Upon accepting a hardware interrupt request from a device (on INTR), the processor acknowledges this to the device and initiates an #INTA read cycle for the 1-byte interrupt number which the processor reads and uses as a pointer to the interrupt service routine to be executed SeeFig.Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Brey: The Intel Microprocessors, 7e 2006 9-12 for Detailed Timing Specifications
Bus Timing Basic Data Write Timing

Timing for a basic write cycle Can be for either memory or I/O On the 8088: - For memory, IO/#M = 0 - For I/O: IO/#M = 1
Also DT/#R = 1
Device strobes data in
Detailed Write Timing for the 8088
Also DT/#R = 1
3 parts of the address
1. Address established
2. Processor puts data on data bus
Data should remain valid for 88 ns after #WR rise
Enable Data bus

Hold Time
READY and Wait States: 5 MHz Clock

If the memory or I/O device is too slow to use the standard 4T read cycle (access time > 420 ns) , wait states must be inserted into the cycle by using the READY input to the processor Wait states are additional clock cycles that increase the length of access time allowed for memory or I/O devices Wait states are inserted between the standard T2 and T3 cycles Wait time is inserted as whole clock cycles: i.e. if access time = 430 ns insert 1 complete wait state of 200 ns! Inserting n wait states increase the maximum allowed access time from the normal typical value of 420 ns (with no waits) to 420 + n 200 ns The READY signal is sampled by the microprocessor at the start of T3 and again at the middle of each wait state.
Detailed Ready Timing

Ready Sampling
Sample at end of T2 35 ns
(Tw)
Then Sample at middle of each TW
RDY Input to 8284A Inactive (Not Ready)
0 ns
8 ns
READY Output from 8284A 30 ns (Input to 8086) Active (Ready) 118 ns Internal Sync circuits In the 8284A ensure that READY output to processor meets the above timing requirements
0: 2 stages, 1: 1 stage of sync

Generation of 0-7 wait states Using one of the two RDY inputs to the 8284A 1st bus cycle state
RD
#RD gated by the for the memory device Requiring wait states
(Gated)
RDY1
Jumper Selects # of Wait States
QA QB QC
0W 1W 2W
Serial I/P
Synchronous Shift rights
1
OR
8-bit Shift Register
RD
(Gated)
CLR Shift Register During T1 Processor
CLR shift Register: No Shifting
Effectively, RDY1 = (Selected Q + RD) (when the slow memory device is accessed) Note: #RD,#WR,#INTA Note: #RD is extended with are all inactive high during T1 the addition of wait states
Minimum and Maximum Modes

MN/#MX input on 8088/8086 selects min (0V) or max (+V) mode
Minimum mode is the least expensive way to configure a 8086/8088 system: Bus control signals are generated directly by processor Good backward compatibility with earlier 8085A 8 bit processor - Same control signals - Support same peripherals Maximum mode provides greater versatility at higher cost.
New control signals introduced to support 8087 coprocessor (e.g. QS0 &QS1) and multiprocessor operation (e.g. #RQ/GT0 & RQ/GT1)
Control signals omitted must be externally generated using an external bus controller, e.g. 8288. The controller decodes those control signals from the now compressed form of 3 control bits (#S0,#S1,#S2) Can be used with the 8087 math coprocessor Can be used with multiprocessor systems Maximum mode no longer supported since 80286
Use of 8086 in the Minimum Mode

Microprocessor-based System
Basic control signals are directly available from processor
Address Demultiplexing
Address Decoding Direction
AD Bus Prevents Transceiver from driving the AD bus when interrupt controller Is using it
Bidirectional Data Buffering
RAM
ROM
I/O
Here the Interrupt controller accesses the AD bus before demultiplexing - careful! Brey: The Intel Microprocessors, 7e
Interrupt Handling
Several Interrupt Requests

8086 Maximum Mode

8288 Bus Controller chip: Necessary in this mode. Generates essential control signals not provided directly by QP form the S0-S2 O/Ps Control signals are more specific, e.g. separate lines for M and I/O operations
8086 Chipset
8288 Bus Controller

bus 20-Pin Chip
Familiar 8088/8086 Outputs

Selects Mode: 1. I/O Bus 2. System Bus
More specific Outputs, Replace #RD, #WR, M/#IO
8288 Bus Controller: Pin Functions

S0, S1, S2 inputs: Status bus bits from processor. Decoded by the 8288 to produce the normal control signals CLK input: From the 8284A clock generator ALE output: Address latch enable output for demuxing address/data DEN output: Data bus enable output to enable data bus buffer. Note opposite polarity to #DEN output in minimum mode. DT/#R output: Data transmit/Receive output to control direction of the bi directional data bus. #INTA output: Acknowledge a hardware interrupt applied to the INTR input of the processor. IOB input: I/O bus mode input. Selects operation in either I/O bus mode or system bus mode. #AEN input: Address Enable input. Used by the 8288 to enable memory control signals. Supplied by a bus arbiter in a multiprocessor system CEN input: Control Enable input. Enables the generation of command outputs from the 8288. #IORC output: Input/Output read control signal. #IOWC output: Input/Output write control signal. #AIOWC output: Advanced Input/Output control signal. #MRDC output: Memory read control signal. #MWTC output: Memory write control signal. #AMWT output: Advanced Memory write control signal. MCE/#PDEN output: Master cascade/Peripheral data output. Selects cascade operation if IOB=0 or enables I/O bus transceivers if IOB=5V
Effective only in the system bus mode
The Math Coprocessor: Chapter 14 (Numeric Data Processor (NDP))

The 8086 performs integer math operations Floating point operations are needed, e.g. for Sqrt (X), sin (x), etc. These are complex math operations that require large registers, complex circuits, and large areas on the chip A general data processor avoids this much burden and delegates such operations to a processor designed specifically for this purpose e.g. math coprocessor (8087) for the 8086 The 8086 and the 8087 coprocessors operate in parallel and share the busses and memory resources The 8086 marks floating point operations as ESC instructions, will ignore them and 8087 will pick them up and execute them
The 8087 Coprocessor: Organization

CU and NEU units Eight 80-bit FP Registers Supports 68 FP (ESC) instructions Speeds up 8086 performance on FP operations by a factor of 50-100 time 8087 Tracks activities of the 8086 by monitrng: 8086 - Bus status (S0-S2 bits) - Queue status (QS0,1) #Test - Instruction being fetched (to check if its an ESC instruction) Synchronize with WAIT using the BUSY-#TEST signals
Top of the data Stack ST(0)
Busy
A stack of 8 x 80-bit FP Registers
ST(7)
8086 Maximum mode outputs for NDP Connection

Bus Status Outputs S0-S2: Status bits that encode the type of the current bus cycle
Table 9-7
Bus Request/Grant Outputs RQ0/GT0: Allow 8087 to request use of the bus, e.g. for DMA memory access Queue Status Outputs QS1,QS0: - For use by coprocessors that receive their instructions via ESC prefix. - Allow the coprocessor to track the progress of an instruction through the 8086 queue and help it determine when to access the bus for the escape op-code and operand. - Indicate the status of the internal instruction queue as given in the table: QS1 0 0 1 1
QS0 0 1 0 1
Queue is idle First byte of opcode from queue Queue is empty Subsequent byte of opcode from queue
Inputs common with the 8086
AD Before Demuxing
Can interrupt the 8086
The 8086 with an 8087 Coprocessor 8086 Brey: The Intel Microprocessors, 7e is operating in the MAX2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. mode
Synchronization between 8086 & the 8087 Coprocessor

The assembler marks all FP instructions as ESC instructions having a special range of opcodes. The Coprocessor monitors the 8086 bus activities and Intercepts such instructions, captures them for execution
WAIT instructions can be used to halt the 8086 to ensure that the 8087 has finished a crucial step, e.g. storing a result in memory.
Programming the 8087

Sequence of FP operations: 1. Operand data is loaded from memory into 8087 registers 2. Do the FP operation in the 8087 3. Store FP results from the 8087 to memory
FP Instructions use the top of the 80-bit register data stack as the default operand (needs not be mentioned), e.g. FLDPI ; loads PI (= T) into the top of the stack ; i.e. into register ST(0) When something is put on top of the stack, a stack PUSH occurs automatically When something is removed from the top of the stack, an automatic stack POP occurs
Define Double Word
Programming the 80387: Example

Two 5 x 4-byte array RAD (radii) AREA
;ECX, also used as loop counter
Instructions Starting with F are FP Instructions For the 80387
. ST = Stack top which is also ST(0)
80386 Program Note: 8087 automatically converts Data from integer to FP when moving it from memory to its data stack
Results in stack after Instruction Execution
Push
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COE305 Chapter 9

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WK 3

Brey: The Intel Microprocessors, 7e

Brey: The Intel Microprocessors, 7e

I/P Selects Min/Max Mode

59 Total > 40 pins available Use multiplexing

DC Pin Characteristics: Voltages

Brey: The Intel Microprocessors, 7e

DC Pin Characteristics: Currents

O/P can source up to 400 QA max

8088/86 Pin Characteristics: DC

* # * = 1.6 mA for standard 74 TTL # = 40 QA for standard 74 TTL QP

Two problems: - Lower fanout - Lower noise margin

8088/86 Pin Characteristics: DC

The Buses: Address & Data

The Status (S) Bus

86: #S0-S2, S3-S7 88: #S0-S2, S3-S6, #SS0

Main Control Signals

= Active low signal

Main Control Signals, Contd.

8087 Math Coprocessor

Synchronizes processor execution to external events

Main Control Signals, Contd.

Brey: The Intel Microprocessors, 7e

Brey: The Intel Microprocessors, 7e

Minimum Mode Signals, Contd.

Brey: The Intel Microprocessors, 7e

Clock Generator Sync

Brey: The Intel Microprocessors, 7e

Clock Generator (8284A)

Provides synchronization for external input signals to the processor:

Brey: The Intel Microprocessors, 7e

Clock Generator (8284A): Signals

OSC: EFI To other QPs

PCLK to Per CLK to QP

Brey: The Intel Microprocessors, 7e

Clock Generator (8284A): Signals

Clock Generator (8284A): Block Diagram

CLOCK & Sync

Crystal Select clocking source

Synchronize with ive clock edge

0 = 2 stages, 1 = 1 stage of synchronization

Grounded when Xtal Osc is used

RC circuit for automatic Reset on power up

Bus Demultiplexing and Buffering

Demultiplexing the 8088 Processor

Octal D-type Transparent Latch (not edge triggered)

Feature Not utilized!

Use as data bus, with #DEN active

Demultiplexing the 8086 Processor Address/Data bus

with #DEN active

Brey: The Intel Microprocessors, 7e

Last O/P Maintained (latched)

Fully DeMuxed and buffered 8088

244 Buffer 74244 is an Octal Buffer with 3-state outputs

DeMuxed Address Lines (unidirectionalAlways O/Ps) Latch provides the buffering

74245 is an Octal Bus Transceiver with 3-state outputs

Non-Demuxed Bidirectional Data Lines

Fully DeMuxed and buffered 8086

Brey: The Intel Microprocessors, 7e

Use to determine Fanout

Brey: The Intel Microprocessors, 7e

Brey: The Intel Microprocessors, 7e

Bus Timing Timing in General