EED 4403 Microprocessor-Based Systems

Fundamentals of Digital Logic and Binary Number Representation

Hasrulnizam Hashim, Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901
2-1

Digital Signals and Basic Logic Gates

Digital signal values
True False 1 0 High Voltage (e.g. 5V)12 Low Voltage (e.g. 0V)

Basic logic gates

1. Inverter
X X Y=X 1 0 X Y 0 1 0 1 Y 0 1 Z 0 0 0 1 Truth Table of an AND gate Truth Table of an inverter

2. AND

X Y

Z=XyY

3. NAND

X Y

0 0 1 1

Z=XyY
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Basic Logic Gates

X Y 0 1 0 1 Z 0 1 1 1

4. OR

X Y

Z=X+Y

5. NOR

X Y

0 0 1 1

Truth Table of an OR gate

Z=X+Y

Y 0 1 0 1

Z 0 1 1 0

4. XOR

X Y

Z = XyY +XyY Z=X+Y

0 0 1 1

Truth Table of an XOR gate

5. XNOR

X Y

Z = XyY +XyY Z=X+Y

2-3

Basic Logic Gates

Tri-state Buffer
C I C O 1 0 0 I X 0 1 O Z 0 1
Truth table of a tri-state buffer

I1 O I2 S Mux C X Y

2-to-1 multiplexer

Bi-direction circuit
2-4

Decoder Circuits
A decoder circuit uniquely selects one of its outputs according to its input signals
yyy

N inputs

yyy

Decoder

2N outputs

2-to-4 decoder implementation

X X Y 0 0 1 1 0 1 0 1 Z1 Z2 Z3 Z4 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 Z1 (00) Z2 (01) Y Z3 (10) Z4 (11)
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Decoder Circuit
3-to-8 decoder implementation
 Assume that we have 2-to-4 decoders available as standard components  When CS is low (0), all the outputs of the decoder are low (0)
X Y Z
X Y CS X Y CS X Y CS

2-to-4 decoder

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Sequential Logic Circuits

D latch
D CLK Q Q D CLK Q  When CLK=1, Q always reflects the signal value at input D  If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0

D Flip-flop
D CLK Q Q D CLK Q  D flip-flop will not change its output values unless there is a negative edge event at CLK input (CLK switches from logic 1 to 0).  When a negative edge appears at CLK input , D Flip-flop updates Q to the current D value
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Sequential Logic Circuits

Counter
 Basic binary counter
A
DFF Q D Q DFF Q D Q

Clk
B
DFF Q D Q

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Init.

CLK

 Synchronous counter
A B C

DFF Q D Q

DFF Q D Q

Q Q

CLK 2-8

Sequential Logic Circuits

frequency divider
 Divide clock frequency by 4
DFF Q D Q DFF Q D Q

CLK CLK_4 CLK_4

CLK

 Divide clock frequency by 3

DFF Q D Q

DFF Q D Q

CLK CLK_3 CLK_3

CLK

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Sequential Logic Circuits

Register
 A row of storage elements (e.g. D flip-flops)
Q3
DFF Q D Q DFF Q D Q

Q2
DFF Q D Q

Q1
DFF Q D Q

Q0

Q[3:0]

Data CLK

Shift register
Q3 0 CLK
DFF Q D Q DFF Q D Q

Q2
DFF Q D Q

Q1
DFF Q D Q

Q0

CLK Init.

Q3 1 0 0 0 0

Q2 0 1 0 0 0

Q1 1 0 1 0 0

Q0 0 1 0 1 0

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Memories Circuits
Memories are storage devices containing a large number of storage locations
 Addressing space: total number of memory locations  If a memory device has N bit addresses, it has 2N memory locations

N/2 bit address

Row decoder

Memory location

yyy

yyyyy

yyyyy Column decoder yyy N/2 bit address

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Memory Types
ROM v.s. RAM
 ROM: Read-Only Memory  RAM: Random Access Memory (allow both read and write operations)

Volatile v.s. Non-volatile

 Volatile: memory loses data after power is off  Non-volatile: memory keep stored data even after power is off

Non-volatile Mask ROM PROM EPROM EEPROM Flash memory MRAM

Volatile SRAM DRAM

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Memory Addressing
Example
 Use memory chips with the capacity of 1K (1024 bit) to construct a 2K memory system

1K W/R CS Addr[9:0] Addr[10] W/R

1K W/R CS

2-13

Binary Number System

Converting binary numbers to decimal numbers
Binary 1011 0111 Decimal 1*2^3 + 0*2^2 + 1*2^1 + 1*2^0 = 11 0*2^3 + 1*2^2 + 1*2^1 + 1*2^0 = 7

Converting binary numbers to hexadecimal numbers

1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 F 5 A 3

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Binary Addition
 Example
0 1 0 1 + 1 0 0 1 1 1 1 0
C_in

 A single-bit full adder

A B

Full adder

C_out

 4-bit adder
A[0] B[0] C_in
Full adder

A[1] B[1]
Full adder

A[2] B[2]
Full adder

A[3] B[3]
Full adder

C_0

C_1

C_2

C_out

S[0]

S[1]

S[2]

S[3]
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Handling Negative numbers

Signed magnitude
 The left-most bit is a sign bit 0 indicates positive a number and 1 indicates negative a number
Signed magnitude Decimal

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 2 3 0 -1 -2 -3
Decimal

Ones complement
 For positive number A, it is
represented as usual binary number

1s complement

 For negative number -A, its

representation is obtained by flipping the bits of the binary representation of A

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 0 1 1 0 1 0

0 1 2 3 0 -1 -2 -3
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Handling Negative numbers

Twos complement
 For positive number A, it is the
same as the ones complement
2s complement Decimal

 For negative number A, add one

to the ones complement representation

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 0 1 1 0 1 0

0 1 2 3 -1 -2 -3 -4

By using twos complement number representation, minus operations can be performed by adders
3 1 2
Overflow Ignore

0 1 1 1 1 1

2 3 -1

0 1 0 1 0 1 1 1 1 -1
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1 0 1 0 2