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Manufacturing Processes

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Introduction
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s s s s s

FPGA-Based System Design: Chapter 1

IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. The key figure of merit for fabrication process is the size of the smallest transistor. - fabrication technologies are usually identified by their min: transistor length. - a process which can produce a transistor with a 0.13 m min: channel length is called a 0.13 m process. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped). Wires made of polycrystalline silicon (poly) or metals insulated from the substrate by Silicon dioxide (SiO2), which is an insulator. The n-type and p-type regions and the polysilicon can be used to make wires as well as transistors. But metal (either copper or a aluminum) is the primary material for wiring together transistors because of its superior electrical properties. There may be multiple layers of aluminum/copper wires to create all necessary connections. Copyright 2004 Prentice Hall PTR

CMOS Fabrication
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s s s

Now that we can design logic gates and latches from transistors, let us consider how the transistors are built. Transistors are fabricated on thin silicon wafers that serve as both a mechanical support and an electrical common point called the substrate. Lithography process similar to printing press is used. On each step, different materials are deposited or etched. We can understand the physical layout of transistors from two perspectives. Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process.
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FPGA-Based System Design: Chapter 1

Inverter Cross-section Diagram


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As shown in this diagram, the inverter is built on a p-type substrate. The pMOS transistor requires an n-type body region, so an n-well is diffused into the substrate in its vicinity. It is also possible to design a CMOS process with an n-type substrate and p-wells to contain the nMOS transistors. The nMOS transistor has n-type source and drain regions and a polysilicon gate over a thin layer of silicon dioxide . The pMOS transistor is a similar structure with p-type source and drain regions. The polysilicon gates of the two transistors are tied together somewhere off the page and form the input A. The source of the nMOS transistor is connected to a metal ground line and the source of the pMOS transistor is connected to a metal VDD line. The drains of the two transistors are connected with metal to form the output Y. A thicker layer of Si02 prevents metal from shorting to other layers except where contacts are explicitly etched.

GN D

VD D

n+
FPGA-Based System Design: Chapter 1

n+ p substrate

p+

p+ n w ell

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Well and Substrate Taps


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The substrate must be tied to a low potential to avoid forward-biasing the p-n junction between the p-type substrate and the n+ nMOS source or drain. Likewise, the n-well must be tied to a high potential. This is generally done by adding heavily doped substrate and well contacts, or taps, to connect GND and VDD to the substrate and n-well, respectively, as shown in Figure.

A GND Y

p+
FPGA-Based System Design: Chapter 1

n+

n+ p substrate

p+
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n well

Inverter Mask Set


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The fabrication sequence consists of a series of steps in which layers of the chip are defined through a process called photolithography. Transistors and wires are defined by masks. Masks specify where the components will be manufactured on the chip. Figure shows a top view of the six masks. Cross-section taken along dashed line.

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Y
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FPGA-Based System Design: Chapter 1

G ND

Detailed Mask Views


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Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Fabrication
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Chips are built in huge factories called fabs. Contain clean rooms as large as football fields.

Courtesy of International Business Machines Corporation. Unauthorized use not permitted.

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Fabrication Steps
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Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

Figure illustrates the bare substrate before processing.


p substrate

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Oxidation
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The wafer is first oxidized in a high-temperature (typically 900-1200C) furnace that causes the Si and 02 to react and become Si02 on the wafer surface. The oxide must be patterned to define the n-well.
SiO2

p substrate

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Photoresist
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Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light The photoresist is exposed through the n-well mask that allows light to pass through only where the well should be.
Photoresist SiO2

p substrate
FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR

Lithography
Expose photoresist through n-well mask. s The softened photoresist is removed to expose the oxide.
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Photoresist SiO2

p substrate

FPGA-Based System Design: Chapter 1

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Etch
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The oxide is etched with hydrofluoric acid (HF) where it is not protected by the photoresist.
Photoresist SiO2

p substrate

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Strip Photoresist
Then the remaining photoresist is stripped away using a mixture of acids called piranha etch. s Necessary so resist doesnt melt in next step
s
SiO2

p substrate

FPGA-Based System Design: Chapter 1

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n-well
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n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si In either method, the oxide layer prevents dopant atoms from entering the substrate where no well is intended.
SiO2 n well
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FPGA-Based System Design: Chapter 1

Strip Oxide
Strip off the remaining oxide using HF. s Back to bare wafer with n-well. s Subsequent steps involve similar series of steps.
s

n well p substrate

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Polysilicon
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s s

The transistor gates are formed next. These consist of polycrystalline silicon, generally called polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then the wafer is placed in a reactor with silane gas (SiH4) and heated again to grow the polysilicon layer through a process called chemical vapor deposition.

p substrate

n well

FPGA-Based System Design: Chapter 1

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Polysilicon Patterning
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Use same lithography process to pattern polysilicon

p substrate
FPGA-Based System Design: Chapter 1

n well
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Self-Aligned Process
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s s

Polysilicon gate over the nMOS transistor blocks the diffusion so the source and drain are separated by a channel under the gate. This is called a self-aligned process because the source and drain of the transistor are automatically formed adjacent to the gate without the need to precisely align the masks. Use oxide and masking to expose where n+ dopants should be diffused or implanted. N-diffusion forms nMOS source, drain, and n-well contact.

FPGA-Based System Design: Chapter 1

p substrate

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n well

N-diffusion
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Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

FPGA-Based System Design: Chapter 1

p substrate

n well
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N-diffusion cont.
Historically dopants were diffused s Usually ion implantation today s But regions are still called diffusion
s

n+

n+ p substrate n well

n+

FPGA-Based System Design: Chapter 1

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N-diffusion cont.
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Strip off oxide to complete patterning step

n+

n+ p substrate n well

n+

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

P-Diffusion
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Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+

n+

n+ p substrate

p+ n well

p+

n+

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Contacts
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Now we need to wire together the devices. Cover chip with thick field oxide. Etch oxide where contact cuts are needed.

Contact

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n+

n+ p substrate

p+ n well

p+

n+

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Metalization
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Sputter on aluminum over whole wafer. Pattern to remove excess metal, leaving wires. The metal is patterned with the metal mask and plasma etched to remove metal everywhere except where wires should remain. This completes the simple fabrication process.

M etal

p+

n+

n+

p+ n well

p+

n+

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR