ARM7TDMI-S CPU

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BL Standard ICs - Microcontrollers February 2004

ARM Architecture
Thumb state
Instruction set

Processor Modes
Register usage

Interrupt Handling
3-stage Pipeline
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ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core
3 stage pipeline
Von Neumann architecture CPI ~1.9 T: D: M: I: S: Thumb instruction set includes debug extensions enhanced multiplier (32x8) with instructions for 64-bit results core has EmbeddedICE logic extensions fully synthesisable (soft IP)

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Thumb State

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Thumb state
ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit data and registers. Set of instructions re-coded into 16 bits
Improved code density by ~ 30% saving program memory space

In Thumb state only the program code is 16-bit wide

after fetching the 16-bit instructions from memory, they are decompressed to 32 bit instructions before they are decoded and executed all operations are still 32-bit operations

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ARM and Thumb Interworking

Switch between ARM state and Thumb state using BX instruction
In ARM state: BX<condition> Rn In Thumb state: BX Rn Rn
n: 0-15
31 1 0

BX
31 1 0

Destination address
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ARM / Thumb selection 0: ARM state 1: Thumb state

Instruction Set

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ARM Instruction Set

All instructions are 32-bits long

Many instructions execute in a single cycle

Most of the ARM Instructions can be conditionally executed Could be divided into six broad classes of instruction
Branch instructions Data Processing instructions Status register transfer instructions

Load and Store instructions

Coprocessor instructions Exception-generating instructions
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Thumb Instruction Set

All instructions are 16-bits long Most of the Thumb Instructions cannot be conditionally executed Thumb instruction set is subset of ARM instruction set It takes more instructions in Thumb to do the same job in ARM resulting in a performance penalty

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Processor Modes

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Processor Modes(1)
ARM has seven operating modes
User
FIQ IRQ Supervisor System Abort Undefined

unprivileged mode under which most applications run

entered, when a high priority (fast) interrupt is raised general purpose interrupt handling protected mode for the operating system
entered on reset or software interrupt instruction

privileged mode using same registers as user mode used to handle memory access violations used to handle undefined instructions

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Processor Modes(2)
User System

FIQ
IRQ

Supervisor
Abort Undefined
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Privileged Modes

Exception Modes

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Privileged and Exception Modes

FIQ IRQ Supervisor Abort Undefined

Entered when a specific exception occurs Each mode has additional registers to prevent corruption On Reset ARM core is in Supervisor mode Have access to system resources Can change modes freely using ARM instructions

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User Mode & System Mode

User Mode:
User mode has access to limited system resources Cannot change modes freely within User mode User program can make a supervisor call using the SWI instruction(SWI- Software Interrupt but is usually called Supervisor call)

System Mode:
System mode is similar to User mode but used by OS which needs access to system resources (Privileged) System mode also used during nested interrupt handling

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ARM Registers

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Registers (1)
An ARM core has 37 registers (32-bits wide)

General purpose registers

1 program counter 30 general purpose registers

Status registers
1 current program status register(CPSR) 5 saved program status registers(SPSR)

These registers are not all accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

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Registers (II)
Depending on processor mode one of several banks is accessible. Each mode can access
the program counter r15 (PC) a particular r13 (stack pointer SP) and r14 (subroutine link register, LR)

a particular set of r0-r12 registers

the current program status register (CPSR)

Privileged modes (except System mode) can also access

a particular SPSR (saved program status register)

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User and System

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (SP) r14 (LR) r15 (PC) CPSR

Register Banking

Banked registers
FIQ
r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP)

IRQ

Supervisor

Abort

Undefined

r14_fiq (LR)

r14_irq (LR)

r14_svc (LR)

r14_abt (LR)

r14_und (LR)

SPSR_fiq

SPSR_irq

SPSR_svc

SPSR_abt

SPSR_und

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Registers in Thumb State

The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:
eight general registers the program counter a Stack pointer a Link register the current program status register r0 - r7 PC SP LR CPSR

In Thumb state, the high registers (r8 - r12) are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage
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Thumb vs. ARM

r0 r1 r0 r1 r2 r3 r4 r5 r6 r7

r2

Thumb state Low registers

r3 r4 r5 r6

r7

Thumb State
Thumb state

ARM State

r8 r9 r10 r11 r12

High registers

r13 (SP) r14 (LR) r15 (PC) CPSR SPSR

r13 (SP) r14 (LR) r15 (PC) CPSR

SPSR

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Register Overview
User and System
r0 r1

FIQ
r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq (SP)

IRQ
r0 r1

Supervisor
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc (SP)

Abort
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt (SP)

Undefined
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_und (SP)

Thumb state Low registers

r2 r3 r4 r5 r6 r7 r8 r9

r2
r3 r4 r5 r6

r7
r8 r9 r10 r11 r12 r13_irq (SP)

Thumb state High registers

r10 r11 r12 r13 (SP) r14 (LR) r15 (PC) CPSR

r14_fiq (LR)
r15 (PC) CPSR SPSR_fiq

r14_irq (LR)
r15 (PC) CPSR SPSR_irq

r14_svc (LR)
r15 (PC) CPSR SPSR_svc

r14_abt (LR)
r15 (PC) CPSR SPSR_abt

r14_und (LR)
r15 (PC) CPSR SPSR_und

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Program Status Register (1)

31 30 29 28 27 24 23 16 15 8 7 6 5 4 mode 0

Condition code flags

Reserved

Control bits

Condition Code Flags

N: Negative or less than
Z: Zero C: Carry or borrow or extend

V: Overflow
To not corrupt reserved bits, a read-modify-write strategy should be applied to change PSR bits.
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Program Status Register (2)

31 30 29 28 27 24 23 16 15 8 7 6 5 4 mode 0

Condition code flags

Reserved

Control bits

Interrupt Disable Bits

I: IRQ interrupts disable
F: FIQ interrupts disable

Mode Bits
10000 10001 10010 10011 User FIQ IRQ Supervisor

T Bit
Thumb mode (when set)
ARM mode (when cleared)

10111
11011 11111

Abort
Undefined System

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Program Counter (r15)

When the processor is executing in ARM state
all instructions are 32 bits wide
all instructions must be word aligned bits [31:2] contain the PC, bits [1:0] are zero
(instructions cannot be halfword or byte aligned)

When the processor is executing in Thumb state

all instructions are 16 bits wide all instructions must be halfword aligned bits [31:1] contain the PC, bit [0] is zero
(instructions cannot be byte aligned)
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Interrupt Handling

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ARM Exception Vectors and processor mode

Reset Undefined Instruction Software Interrupt(SWI) Prefetch Abort Data Abort Interrupt(IRQ) Fast Interrupt(FIQ)
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Supervisor Undefined Supervisor Abort Abort IRQ FIQ

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Exception Vectors table

. . . FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset
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0x1C 0x18 0x14 0x10 0x0C 0x08 0x04

0x00

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Exception Handling
Entering an exception the ARM core
saves the address of the next instruction in the appropriate LR
r15 (PC) r14_<mode> (LR)

copies the CPSR into the appropriate SPSR

CPSR SPSR_<mode>

sets appropriate CPSR bits

interrupt disable bits mode field bits
CPSR:
8 7 I 6 F 5 T 4 mode 0

if running in Thumb state, enter ARM state*

Control bits

forces PC to fetch next instruction from relevant exception vector

*: all exceptions switch to ARM state!

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Leaving Exception(1)
To leave an exception, the exception handler must
copy SPSR back into CPSR
SPSR_<mode> CPSR

(automatically restoring also I, F and T)

8 7 I 6 F 5 T 4 mode 0

CPSR:

Control bits

move contents of current LR minus offset* to PC

r14_<mode> (LR) PC - offset r15 (PC)

*: varies according to type of exception: 2, 4

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Leaving Exception-Example(2)
After servicing IRQ execute the following instruction

SUBS PC,R14_irq,#4
This restores both PC and CPSR
SPSR_irq> CPSR

r14_<irq> (LR)

PC - offset

r15 (PC)

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Multiple Exceptions
Exception priorities
When multiple exceptions arise at the same time, a fixed priority sytem determines the order in which they are handled
1. 2. 3. 4. 5. 6. 7. Reset highest priority Data Abort (data memory access cannot be completed) FIQ IRQ Prefetch Abort (instruction memory access cannot be completed) Undefined Instruction SWI - Software Interrupt (to enter supervisor mode) lowest priority

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FIQ-Why is it called so ?
This mode has its own set of banked registers from R8-R12. Hence no or minimal stack operations are required
FIQ is the last interrupt vector in the vector table. Hence jump is not needed to reach ISR

ARM recommends only one interrupt source to be classified as FIQ

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Interrupt Latency
Latency could be between 5 to 27 processor clocks Ask customers to refer to ARM7TDMI-S Technical Reference Manual for details

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Instruction Pipeline

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Instruction Pipeline
The ARM7TDMI-S core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously The Program Counter (PC) points to the instruction being fetched rather than to the instruction being executed During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory

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3-Stage Instruction Pipeline

ARM Thumb

PC

PC

Fetch

Instruction Fetched from Memory

PC - 4

PC - 2

Decode

Thumb only: Thumb instruction decompressed to ARM instruction

Instruction decoded

PC - 8

PC - 4

Execute

Registers read from Register Bank, Shift and ALU operations performed, Registers written back to Register Bank

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Optimal Pipelining
In this example it takes 6 clock cycles to execute 6 instructions All operations are on registers (single cycle instructions) Clock cycles per instruction (CPI) = 1
ADD SUB Fetch Decode Fetch Execute Decode Execute

MOV
AND ORR

Fetch

Decode
Fetch

Execute
Decode Fetch Execute Decode Execute

EOR
CMP RSB

Fetch

Decode
Fetch

Execute
Decode Fetch

1 Cycle
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Branch Pipeline Example

Branches break the pipeline Example in ARM state

BL X

0x8000 0x8004

Fetch

Decode Fetch

Execute Decode

Linkret

Adjust

X
ADD SUB

0x8008
0x8FEC 0x8FF0

Fetch
Fetch Decode Fetch Execute Decode Execute Decode Fetch

MOV
AND

0x8FF4
0x8FF8

Fetch

1 Cycle
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Reference
ARM Architecture Reference Manual
Available with ARM tools

Also available on PDF

ARM System-on-Chip Architecture

By Steve Furber

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