8051 Architecture

8051 Features:

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40- pin DI package Harvard Architecture 8-bit Arithmetic Logic Unit 8-bit data bus multiplexed with address bus On-chip oscillator:116MHz operating frequency(fxtal) 16-bit address bus :216 = 65,536 = 64K bytes of Locations. 4K ROM, 128 bytes RAM, 32 REGs, 16 bytes Bit addressable RAM, 80 bytes user RAM. Two 16 bit timers/counters with interrupts Four 8 bit parallel ports 1 serial port with interrupt facility 2 external Interrupts( total - 6 Interrupts)

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Block Diagram

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MCS-51 family
MC
8031

Features
Intel's: 0KROM, 128-Bytes RAM, 32I/O pins, 32-Regs, 2-Timers, 1port, 6-Interrupts. Intel's: 4KROM, 128-Bytes RAM, 32I/O pins, 32-Regs, 2-Timers, 1port, 6-Interrupts. Intel's: 8KROM, 256-Bytes RAM, 32I/O pins, 32-Regs, 3-Timers, 1port, 8Interrupts.

Serial
8051

Serial
8052

Serial
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MCS-51 family
AT89C51

Atmel's: 4KROM, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-Timers, 1-Serial port, 6-Interrupts, Vcc =5V. (Flash ROM) Atmel's: 4KROM, 128-Bytes RAM, 32- I/O pins,32-Regs, 2-Timers, 1-Serial port, 6Interrupts, Vcc =3V. (Flash ROM) Dallas's: 8KROM, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-Timers, 1- Serial port, 6-Interrupts, Vcc =5V. (Non volatile RAM)

AT89LV51

DS5000

MGR,RJ, ECE,RVCE

MCS-51 family
8751

OTP 8051

4 K bytes of on chip of UV-EPROM PROM burner and UV-EPROM for erase the contents Takes 20 mins to erase One-Time- Programmable Cheaper(price/unit) Long life time

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AT89C51ED2
80C52 Architecture Compatible

8051 Instruction Compatible Four 8-bit I/O Ports Three 16-bit Timer/Counters 256 Bytes Scratch Pad RAM 9 Interrupt Sources with 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply 2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a default Serial Loader 64K Bytes On-chip Flash Program Memory On-chip 1792 bytes Expanded RAM (XRAM) On-chip 2048 Bytes EEPROM Block for Data Storage SPI(Serial Peripheral ) Interface (Master/Slave Mode) Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator MGR,RJ, ECE,RVCE Hardware Watchdog Timer (One-time Enabled with Reset-

P I N D I A G R A M

40 30 pF 19 12 MHz 30 pF 18 XLAT1 XLAT2 VCC

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30 31 9

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

32 33 34 35 36 37 38 39 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

/PSEN ALE /EA RST

8051

/RD /WR T1 T0 /INT1 /INT0 TxD RxD

17 16 15 14 13 12 11 10

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 20

VSS

A15 A14 A13 A12 A11 A10 A9 A8

MGR,RJ, ECE,RVCE

128 bytes of Internal RAM structure(lower address space)

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Working registers
32 bytes form address 00h-1Fh make up 32 working registers. Organized into 4 register banks numbered from Bank 0 to

Bank 3 and are made up of eight registers named R0 to R7. At any time one bank is active, based on status of RS0 and RS1 bits of PSW(program status word). Default is Bank0 (RS0=RS1=0) Registers can be accessed either by RAM address or name(when its bank is selected). E.g. R0 of bank 3 is R0(if bank 3 is currently selected RS1=1,RS0=0) or address 18h( whether bank 3 is selected or not)

Mov R0, #20h (Immediate, R0 of current bank) Mov 13h,#20h(Direct, RAM address 13h)
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Working registers

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Bit addressable locations

A bit addressable area of 16 bytes occupies RAM

byte address 20h to 2Fh, forming a total of 128 addressable bits. An addressable bit may be specified by its bit address of 00h to 7Fh or 8 bits may be form any byte address from 20h to 2Fh. Addressable bits are useful when the program need only remember a binary event (switch on, light of, etc)

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MGR,RJ, ECE,RVCE

Bit addressable locations

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128 bytes of Internal RAM structure(Upper address space)

The RAM locations above are mapped into

special function registers

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SFR register space

Internal Data RAM

MOV A, 5FH
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MOV Ri, #9FH (i=0 or 1) MOV A, @Ri

MOV A, FFH

Stack & Stack Pointer SP (81H)

RAM locations are used of stack operations SP points to the data item currently on the top of stack. Push data onto stack: PUSH : (SP) <- (SP) + 1 ((SP)) <- (direct) Pop data from the stack: POP : (direct) < ((SP)) (SP) <- (SP) 1 The stack pointer in the 8051 is only 8 bits wide, which means

that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07. The upper limit 08 to 1Fh means 24 bytes after is bit addressable and so if necessary the SP should be changed to RAM location 30 -7Fh MOV SP, #XXh
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Stack
7FH Scratch pad RAM

30H 2FH Bit-Addressable RAM

20H
1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3

Register Bank 2
(Stack) Register Bank 1

Register Bank 0

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Example: MOV MOV MOV PUSH PUSH PUSH POP R6,#25H R1,#12H R4,#0F3H 6 1 4 4

0BH 0AH 09H 08H Start SP=07H

0BH 0AH 09H 08H 25

0BH 0AH 09H 08H 12 25

0BH 0AH 09H 08H F3 12 25

0BH 0AH 09H 12 25

08H

SP=08H

SP=09H

SP=0AH

SP=09H

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Stack .
The stack is accessed explicitly by PUSH

and POP, or implicitly by the subroutine call (ACALL, LCALL) and return (RET, RETI) to save and restore PC.

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Accumulator(A) & B CPU registers

8 bit registers, hold results of many arithmetic and

logical instructions. Both are bit addressable

Accumulator bits can also be addressed as

follows. ACC.7 for MSB..acc.0 for LSB

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Program status word(PSW)

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Details of PSW
status register of 8 bit wide at address 0D0h CY =1 when Addition>0 or subtraction<0 AC =1 when low nibble affects high nibble F0 = User flag RS1 = Register bank select bit 1 RS0 = Register bank select bit 0 OV = 1 after Addition or subtraction F1 = User flag P = 1 when ACC has odd no. of ones.

Bit addressable(D7/PSW.7 D0/PSW.0)

Only zero flag is not there in PSW but it is in Jump

instructions as JZ(Jump is zero).

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How to switch Register Bank?

RS1 (PSW.4) Bank 0 Bank 1 Bank 2 Bank 3 0 0 1 1 RS0(PSW.3) 0 1 0 1

Each bank has 8-registers(R0 R8) but by default Bank 0 is selected and accessed.
Cleared after reset and changed by software. E.g.

SETB SETB MOV

RS1 RS0 A, R7

;use bank3

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Program Counter(PC)
PC is 16 bit register points to next instruction to

be executed. The PC is automatically incremented after every instruction byte is fetched and may also be altered by curtain instructions. The PC in only register that does not have an internal address.

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Data Pointer( DPTR)

The DPTR is made up of two 8-bit registers,

named DPH and DPL.

DPH DPL

RAM address

The DPTR can be used as single 16 bit register

or two separate 8 bit registers.

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Program Memory
EA=1 EA=0

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Program memory contd

After reset, the CPU begins execution from location

0000H. if the EA pin is strapped to Vcc, then program fetches to addresses 0000H through 0FFFH are directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are directed to external ROM. If the EA pin is strapped to Vss, then all program fetches are directed to external ROM. The ROM less parts must have this pin externally strapped to Vss to enable them to execute properly.
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External ROM interfacing

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External ROM interfacing.

Port 0 serves as a multiplexed address/data bus. It

emits the low byte of the Program Counter as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 emits the high byte of the Program Counter Then PSEN strobes the EPROM and the code byte is read into the microcontroller.
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External 2k RAM interfacing

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External 2k RAM interfacing..

Port 0 serves as a multiplexed address/data bus

to the RAM, 3 lines of Port 2 are being used to address the RAM. The CPU generates RD and WR signals as needed during external RAM access. There can be up to 64K byte of external Data Memory.

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External Memory Accessing

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On-Chip Oscillator Inputs

Pin 18, 19 (XTAL2, XTAL1) Clock frequency:1 to 16MHz)

Typically driven by a crystal. Normal crystal

frequency is 11.0592 MHz to generate standard baud rates. Minimum frequencies imply that some internal memories are dynamic and must always operate above a minimum frequency or data will be lost.

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Crystal Connection

C1, C2 = 30 pF 10 pF for Crystals

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XTAL connection to an external clock source

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Clock cycle, Machine cycle, Instruction cycle

Clock cycle = time of one cycle of clock

(oscillator) Machine cycle =12 clock cycles for 8051 Instruction cycle = period for executing one instruction. Most instructions need only one machine cycle to complete. Some need 2, while some need 4 machine cycles to complete.

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Instruction Vs Clock cycle ?

Clock cycles 1 Machine Cycle

12 clock cycles is equal to 1 instruction cycle in 805

12

12 clock cycles are called One machine cycle and One or more machine cycle gives Instruction Cycle. Instruction cycle depends on how many machine cycle an instruction is taking for execution.
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Reset
The reset input is the RST pin, which is the input to

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a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles(24 oscillator periods), while the oscillator is running. The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, MGR,RJ, ECE,RVCE and SBUF

I/O Port Structure

Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats (tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.
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PORT 0 Pin Structure Port -0 has 8 pins (P0.0-P0.7). The structure of a Port-0 pin as shown below

O/P Buffer

LATCH

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0
Port-0 can be configured as a normal

bidirectional I/O port or it can be used for address/data interfacing for accessing external memory. When control is '1', the port is used for address/data interfacing. When the control is '0', the port can be used as a normal bidirectional I/O port.

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Port0

Address/ Data Bus

1.

2.
3.

4.

5.
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Control=1, port 0 = Address/Data Interfacing When Ctrl =1, address/data bus controls the output driver MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'. Port-0 latch is written to with 1's when used for external memory access.

MGR,RJ, ECE,RVCE

I/O Operation

Port0

Let us assume that control is '0'. When the port is

used as an input port, '1' is written to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be pulled up by an external source. Vcc 10 K
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

Port 0

8051
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Port0
When the port is used as an output port, a '1'

written to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero. Output port does not require configuration.

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Port-1 Pin Structure

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Port1..
Port-1 does not have any alternate function i.e. it is

dedicated solely for I/O interfacing. For output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the external device then it read fine. But when '0' is written to the pin by the external device then the external source must sink current due to internal pull-up. If the external device is not able to sink the current the pin voltage may rise, leading to a possible wrong reading.
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Port-2 Pin Structure

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Port2..
Port-2 is used for higher external address byte or

a normal input/output port. The I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability.

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Port-3 Pin Structure

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Port3..
Each pin of Port-3 can be individually

programmed for I/O operation or for alternate function. The alternate function can be activated only if the corresponding latch has been written to '1'. To use the port as input port, '1' should be written to the latch. This port also has internal pull-up and limited current driving capability. Alternate functions of Port-3 pins are When used as IO pin the alternate output pin is held high by control circuit.
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Reading a port (port-pins) Vs reading a latch

Reading a latch: Usually the instructions that read

the latch, read a value, possibly change it, and then rewrite it to the latch. These are called "read-modifywrite" instructions. Examples of a few instructions areORL P2, A; P2 <-- of or A Reading a Pin: ExamplesP2 a few instructions that read port pin, areMOV A, P0 ; Move port-0 pin values to A MOV A, P1; Move port-1 pin values to A

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Exam Questions
a. Differentiate between a microprocessor and

microcontroller. b. List the salient features of 8051. c. Explain memory organization in 8051 d. Mention the difference between
Assembly coded program and high level language program. Directive and Instructions

e.

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Mention differences between i. Harvard and Von Neumann Architecture ii. CISC and RISC Draw a block diagram that represents 8051 Microcontroller and brief on the Functionalities of some important blocks MGR,RJ, ECE,RVCE