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80SJ Core Specification 80SJ Core Specification

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vtroavctiov vtroavctiov
Architecture Architecture
Operation Operation
Registers Registers
Introd:ction Introd:ction
MCS MCS--51 amily, originally designed by Intel in 51 amily, originally designed by Intel in
the 1980 the 1980 ss
&sed in a large percentage o embedded systems &sed in a large percentage o embedded systems
Includes seeral on Includes seeral on--chip peripherals, like timers chip peripherals, like timers
and counters and counters
128 bytes o on 128 bytes o on--chip data memory and up to 4K chip data memory and up to 4K
bytes o on bytes o on--chip program memory chip program memory
Ieat:res (J/2) Ieat:res (J/2)
88--bit CP& optimized or control applications bit CP& optimized or control applications
Lxtensie Boolean processing ,single Lxtensie Boolean processing ,single--bit logic, capabilities bit logic, capabilities
64K Program Memory address space 64K Program Memory address space
64K Data Memory address space 64K Data Memory address space
&p to 4K bytes o on &p to 4K bytes o on--chip Program Memory chip Program Memory
128 bytes o on 128 bytes o on--chip Data RAM chip Data RAM
32 bi 32 bi--directional and indiidually addressable I,O lines directional and indiidually addressable I,O lines
1wo 16 1wo 16--bit timer,counters bit timer,counters
66--source,5 source,5--ector interrupt structure with two priority leels ector interrupt structure with two priority leels
Ieat:res (2/2) Ieat:res (2/2)
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Introduction Introduction
rcbitectvre rcbitectvre
Operation Operation
Registers Registers
Architect:re Architect:re
Memory Organization Memory Organization
CP& Clock CP& Clock
Interrupt Structure Interrupt Structure
Port Structures Port Structures
1imer,Counters 1imer,Counters
Reset Reset
Memory rganization (J/3) Memory rganization (J/3)
ogical separation o program and data memory ogical separation o program and data memory
Separate address spaces or Program ,ROM, and Data ,RAM, Separate address spaces or Program ,ROM, and Data ,RAM,
Memory Memory
Allow Data Memory to be accessed by 8 Allow Data Memory to be accessed by 8--bit addresses quickly bit addresses quickly
and manipulated by 8 and manipulated by 8--bit CP& bit CP&
Program Memory Program Memory
Only be read, not written to Only be read, not written to
1he address space is 16 1he address space is 16--bit, so maximum o 64K bytes bit, so maximum o 64K bytes
&p to 4K bytes can be on &p to 4K bytes can be on--chip ,internal, o 8051 core chip ,internal, o 8051 core
PSLN ,Program Store Lnable, is used or access to external PSLN ,Program Store Lnable, is used or access to external
Program Memory Program Memory
Memory rganization (2/3) Memory rganization (2/3)
Data Memory Data Memory
Includes 128 bytes o on Includes 128 bytes o on--chip Data Memory which chip Data Memory which
are more easily accessible directly by its instructions are more easily accessible directly by its instructions
1here is also a number o Special lunction Registers 1here is also a number o Special lunction Registers
,SlRs, ,SlRs,
Internal Data Memory contains our banks o eight Internal Data Memory contains our banks o eight
registers and a special 32 registers and a special 32--byte long segment which is byte long segment which is
bit addressable by 8051 bit bit addressable by 8051 bit--instructions instructions
Lxternal memory o maximum 64K bytes is Lxternal memory o maximum 64K bytes is
accessible by accessible by mox mox
Memory rganization (3/3) Memory rganization (3/3)
Internal Data Memory, 128 bytes Internal Data Memory, 128 bytes
CPU Clock CPU Clock
8051 microcontroller has a clock input pin 8051 microcontroller has a clock input pin
Interr:pt Str:ct:re Interr:pt Str:ct:re
1he 8051 proides 4 interrupt sources 1he 8051 proides 4 interrupt sources
1wo external interrupts 1wo external interrupts
1wo timer interrupts 1wo timer interrupts
Additional description ollows in Operations Additional description ollows in Operations
chapter chapter
Port Str:ct:res (J/3) Port Str:ct:res (J/3)
1he 8051 contains our I,O ports 1he 8051 contains our I,O ports
All our ports are bidirectional All our ports are bidirectional
Lach port has SlR ,Special lunction Registers Lach port has SlR ,Special lunction Registers
P0 through P3, which works like a latch, an P0 through P3, which works like a latch, an
output drier and an input buer output drier and an input buer
Both output drier and input buer o Port 0 Both output drier and input buer o Port 0
and output drier o Port 2 are used or and output drier o Port 2 are used or
accessing external memory accessing external memory
Port Str:ct:res (2/3) Port Str:ct:res (2/3)
Accessing external memory works like this Accessing external memory works like this
Port 0 outputs the low byte o external memory Port 0 outputs the low byte o external memory
address ,which is time address ,which is time--multiplexed with the byte multiplexed with the byte
being written or read, being written or read,
Port 2 outputs the high byte ,only needed when the Port 2 outputs the high byte ,only needed when the
address is 16 bits wide, address is 16 bits wide,
Port Str:ct:res (3/3) Port Str:ct:res (3/3)
Port 3 pins are multiunctional Port 3 pins are multiunctional
1he alternate unctions are actiated with the 1 1he alternate unctions are actiated with the 1
written in the corresponding bit in the port SlR written in the corresponding bit in the port SlR
Read Read- -Modify Modify- -Write Ieat:re (J/2) Write Ieat:re (J/2)
hen reading a port some instructions read the hen reading a port some instructions read the
latch and others read the pin latch and others read the pin
1he instructions that read the latch rather than 1he instructions that read the latch rather than
the pin are the ones that read a alue ,possibly the pin are the ones that read a alue ,possibly
change it,, an then rewrite it to the latch are change it,, an then rewrite it to the latch are
called called read read--modiy modiy--write write instructions instructions
Read Read- -Modify Modify- -Write Ieat:re (2/2) Write Ieat:re (2/2)
1imer/Co:nters 1imer/Co:nters
1he 8051 has two 16 1he 8051 has two 16--bit 1imer,Counter bit 1imer,Counter
registers registers
1imer 0 1imer 0
1imer 1 1imer 1
Both can work either as timers or eent counters Both can work either as timers or eent counters
Both hae our dierent operating modes rom Both hae our dierent operating modes rom
which to select ,all modes are described in which to select ,all modes are described in
Operations chapter, Operations chapter,
Reset Reset
1he reset input is the RS1 pin 1he reset input is the RS1 pin
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Introduction Introduction
Architecture Architecture
5eratiov 5eratiov
Registers Registers
Instr:ction Set Instr:ction Set
Optimized or 8 Optimized or 8--bit control applications bit control applications
last addressing modes or accessing internal last addressing modes or accessing internal
RAM in order to acilitate byte operations on RAM in order to acilitate byte operations on
small data structures small data structures
Good or systems that require a lot o Boolean Good or systems that require a lot o Boolean
processing because o its extensie support or processing because o its extensie support or
one one--bit ariables as a separate data type bit ariables as a separate data type
Addressing Modes (J/3) Addressing Modes (J/3)
Direct Addressing Direct Addressing
Operand is speciied by an 8 Operand is speciied by an 8--bit address ield in the bit address ield in the
instruction instruction
1his address mode is possible only or addressing internal 1his address mode is possible only or addressing internal
Data RAM and SlRs Data RAM and SlRs
Indirect Addressing Indirect Addressing
1he instruction speciies a register which contains the address 1he instruction speciies a register which contains the address
o the operand o the operand
1he address register or 8 1he address register or 8--bit addresses can be R0 or R1 o bit addresses can be R0 or R1 o
the selected bank, or the Stack Pointer the selected bank, or the Stack Pointer
1he address register or 16 1he address register or 16--bit addresses can only be 16 bit addresses can only be 16--bit bit
data pointer data pointer register, DP1R register, DP1R
Both internal and external RAM can be indirectly addressed Both internal and external RAM can be indirectly addressed
Addressing Modes (2/3) Addressing Modes (2/3)
Register Instructions Register Instructions
Special instructions are used or accessing our register banks Special instructions are used or accessing our register banks
,containing R0 to R, ,containing R0 to R,
1his instructions hae 3 1his instructions hae 3--bit register speciication within the bit register speciication within the
opcode opcode
1his way o accessing registers is much more eicient 1his way o accessing registers is much more eicient
because o no need or the address byte because o no need or the address byte
hen such instruction is executed one o registers in selected hen such instruction is executed one o registers in selected
ban is accessed ban is accessed
Register bank is selected by two bank select bits in PS Register bank is selected by two bank select bits in PS
Addressing Modes (3/3) Addressing Modes (3/3)
Register Register--Speciic Instructions Speciic Instructions
1hese are instructions which are speciic to a certain register 1hese are instructions which are speciic to a certain register
and they don and they don t need an address byte ,they always operate with t need an address byte ,they always operate with
the same register, the same register,
Immediate Constants Immediate Constants
1he alue o a constant ollows the opcode 1he alue o a constant ollows the opcode
MOV A, 410 MOV A, 410 loads the Accumulator with the decimal loads the Accumulator with the decimal
number 10 number 10
Indexed Addressing Indexed Addressing
Only Program Memory can be accessed and it can be a read Only Program Memory can be accessed and it can be a read
&sed or reading look &sed or reading look--up tables in Program Memory and up tables in Program Memory and
case jump case jump instruction instruction
Instr:ction 1ypes of 80SJ Instr:ction 1ypes of 80SJ
Arithmetic Instructions Arithmetic Instructions
ogical Instructions ogical Instructions
Data 1ransers Data 1ransers
ookup 1ables ookup 1ables
Boolean Instructions Boolean Instructions
Jump Instructions Jump Instructions
Arithmetic Instr:ctions Arithmetic Instr:ctions
Logical Instr:ctions Logical Instr:ctions
Data 1ransfers Data 1ransfers
Look:p 1ables Look:p 1ables
Boolean Instr:ctions Boolean Instr:ctions
J:mp Instr:ctions J:mp Instr:ctions
1imer/Co:nters 1imer/Co:nters
8051 has two 16 8051 has two 16--bit 1imer,Counter registers bit 1imer,Counter registers
1imer,Counter 0 1imer,Counter 0
1imer,Counter 1 1imer,Counter 1
1hese registers can be used as timers or as eent 1hese registers can be used as timers or as eent
counters counters
hen a register is in hen a register is in 1imer 1imer state, it is incremented state, it is incremented
eery machine cycle eery machine cycle
In In Counter Counter state, the register is incremented when state, the register is incremented when
there is a 1 there is a 1--to to--0 transition at its external input pin, pin 0 transition at its external input pin, pin
10 or 11 10 or 11
Both registers hae additional our operating modes Both registers hae additional our operating modes
1imer/Co:nter Modes 1imer/Co:nter Modes
1he selection or 1he selection or 1imer 1imer or or Counter Counter is done by is done by
control bits C,1 in the 1MOD register control bits C,1 in the 1MOD register
Both 1imer,Counters hae our operating modes, Both 1imer,Counters hae our operating modes,
which Modes 0, 1 and 2 are the same or both which Modes 0, 1 and 2 are the same or both
1imer,Counters, Mode 3 is dierent 1imer,Counters, Mode 3 is dierent
Modes are selected by bit pairs ,M1, M0, in 1MOD Modes are selected by bit pairs ,M1, M0, in 1MOD
SlR SlR
Another SlR used or work with 1imer,Counters is Another SlR used or work with 1imer,Counters is
1CON containing lag ,1lx, and control ,1Rx, bits 1CON containing lag ,1lx, and control ,1Rx, bits
Mode 0 Mode 0
Both 1imer 1 and 1imer 0 in Mode 0 operate as an 8 Both 1imer 1 and 1imer 0 in Mode 0 operate as an 8--bit bit
Counters ,with a diide Counters ,with a diide--by by--32 prescaler, 32 prescaler,
1imer register is conigured as a 13 1imer register is conigured as a 13--bit register consisting o all 8 bit register consisting o all 8
bits o 1l1 and the lower 5 bits o 11 bits o 1l1 and the lower 5 bits o 11
1he upper 3 bits o 11 are indeterminate and should be 1he upper 3 bits o 11 are indeterminate and should be
ignored ignored
Setting the run lag ,1R1, does not clear the register Setting the run lag ,1R1, does not clear the register
1imer interrupt lag 1l1 is set when the count rolls oer rom all 1imer interrupt lag 1l1 is set when the count rolls oer rom all
1s to all 0s 1s to all 0s
Mode 0 operation is the same or 1imer 0 as or 1imer 1. Just Mode 0 operation is the same or 1imer 0 as or 1imer 1. Just
substitute 1imer 0 or the corresponding 1imer 1 signals substitute 1imer 0 or the corresponding 1imer 1 signals
Mode J Mode J
Mode 1 is the same as Mode ,or both 1imers,, Mode 1 is the same as Mode ,or both 1imers,,
except that the 1imer register is conigured as except that the 1imer register is conigured as
16 16--bit register bit register
Mode 2 Mode 2
Both 1imer registers are conigured as an 8 Both 1imer registers are conigured as an 8--bit bit
Counters ,11 and 10, with automatic reload Counters ,11 and 10, with automatic reload
Oerlow rom 11 ,10, sets 1l1 ,1l0, and Oerlow rom 11 ,10, sets 1l1 ,1l0, and
also reloads 11 ,10, with the contents o 1h1 also reloads 11 ,10, with the contents o 1h1
,1l0,, which is preset by sotware ,1l0,, which is preset by sotware
1he reload leaes 1l1 ,1l0, unchanged 1he reload leaes 1l1 ,1l0, unchanged
Mode 3 Mode 3
Mode 3 is dierent or 1imer 1 and 1imer 0 Mode 3 is dierent or 1imer 1 and 1imer 0
1imer 1 just holds its count. It operates the same as when 1R1 is 1imer 1 just holds its count. It operates the same as when 1R1 is
set to 0 set to 0
lor 1imer 0 is dierent, 10 and 1l0 o 1imer 0 are lor 1imer 0 is dierent, 10 and 1l0 o 1imer 0 are
established as two separate counters established as two separate counters
10 uses 1imer 0 control bits or its work: C,1, GA1L, 1R0, 10 uses 1imer 0 control bits or its work: C,1, GA1L, 1R0,
~IN10, and 1l0 ~IN10, and 1l0
1l0 is locked into a timer unction ,counting machine cycles, 1l0 is locked into a timer unction ,counting machine cycles,
and takes oer the use o 1R1 and 1l1 rom 1imer 1. 1l0 is and takes oer the use o 1R1 and 1l1 rom 1imer 1. 1l0 is
now actually in control o now actually in control o 1imer 1 1imer 1 interrupt interrupt
Mode 3 is proided or applications that require an extra 8 Mode 3 is proided or applications that require an extra 8--bit bit
timer or counter timer or counter
ith 1imer 0, 8051 looks like it has three 1imer,Counters ith 1imer 0, 8051 looks like it has three 1imer,Counters
hen 1imer 0 in Mode 3, 1imer 1 can be turned on and o by switching hen 1imer 0 in Mode 3, 1imer 1 can be turned on and o by switching
it out o and into its own Mode 3, or can still be used in any application it out o and into its own Mode 3, or can still be used in any application
not requiring an interrupt not requiring an interrupt
Interr:pt (J/3) Interr:pt (J/3)
8051 proides 4 interrupt sources 8051 proides 4 interrupt sources
2 external interrupts 2 external interrupts
2 timer interrupts 2 timer interrupts
1hey are controlled ia two SlRs, IL and IP 1hey are controlled ia two SlRs, IL and IP
Lach interrupt source can be indiidually Lach interrupt source can be indiidually
enabled or disabled by setting or clearing a bit in enabled or disabled by setting or clearing a bit in
IL ,Interrupt Lnable,. IL also exists a global IL ,Interrupt Lnable,. IL also exists a global
disable bit, which can be cleared to disable all disable bit, which can be cleared to disable all
interrupts at once interrupts at once
Interr:pt (2/3) Interr:pt (2/3)
Lach interrupt source can also be indiidually set to Lach interrupt source can also be indiidually set to
one o two priority leels by setting or clearing a bit in one o two priority leels by setting or clearing a bit in
IP ,Interrupt Priority, IP ,Interrupt Priority,
A low A low--priority interrupt can be interrupted by high priority interrupt can be interrupted by high--
priority interrupt, but not by another low priority interrupt, but not by another low--priority one priority one
A high A high--priority interrupt can priority interrupt can t be interrupted by any t be interrupted by any
other interrupt source other interrupt source
I interrupt requests o the same priority leel are I interrupt requests o the same priority leel are
receied simultaneously, an internal polling sequence receied simultaneously, an internal polling sequence
determines which request is sericed, so within each determines which request is sericed, so within each
priority leer there is a second priority structure priority leer there is a second priority structure
Interr:pt (3/3) Interr:pt (3/3)
1his internal priority structure is determined by 1his internal priority structure is determined by
the polling sequence, shown in the ollowing the polling sequence, shown in the ollowing
table table
Lxternal Interr:pts Lxternal Interr:pts
Lxternal interrupts ~IN10 and ~IN11 hae two ways o Lxternal interrupts ~IN10 and ~IN11 hae two ways o
actiation actiation
eel eel--actiated actiated
1ransition 1ransition--actiated actiated
1his depends on bits I10 and I11 in 1CON 1his depends on bits I10 and I11 in 1CON
1he lags that actually generate these interrupts are bits IL0 and 1he lags that actually generate these interrupts are bits IL0 and
IL1 in 1CON IL1 in 1CON
On On--chip hardware clears that lag that generated an external chip hardware clears that lag that generated an external
interrupt when the serice routine is ectored to, but only i the interrupt when the serice routine is ectored to, but only i the
interrupt was transition interrupt was transition--actiated actiated
hen the interrupt is leel hen the interrupt is leel--actiated, then the external requesting actiated, then the external requesting
source is controlling the request lag, not the on source is controlling the request lag, not the on--chip hardware chip hardware
1imer 0 and 1imer J Interr:pts 1imer 0 and 1imer J Interr:pts
1imer interrupts are generated by 1l0 and 1l1 1imer interrupts are generated by 1l0 and 1l1
lags in their respectie 1imer,Counter registers lags in their respectie 1imer,Counter registers
Similarly like in the case o transition Similarly like in the case o transition--actiated actiated
external interrupts, the lag that generated an external interrupts, the lag that generated an
interrupt is cleared by the on interrupt is cleared by the on--chip hardware chip hardware
when the serice routine is ectored to when the serice routine is ectored to
andling of Interr:pts (J/S) andling of Interr:pts (J/S)
hen interrupt occurs ,or correctly, when the lag or hen interrupt occurs ,or correctly, when the lag or
an enabled interrupt is ound to be set ,1,,, the an enabled interrupt is ound to be set ,1,,, the
interrupt system generates an CA to the interrupt system generates an CA to the
appropriate location in Program Memory, unless some appropriate location in Program Memory, unless some
other conditions block the interrupt other conditions block the interrupt
Seeral conditions can block an interrupt Seeral conditions can block an interrupt
An interrupt o equal or higher priority leel is already in An interrupt o equal or higher priority leel is already in
progress progress
1he current ,polling, cycle is not the inal cycle in the 1he current ,polling, cycle is not the inal cycle in the
execution o the instruction in progress execution o the instruction in progress
1he instruction in progress is RL1I or any write to IL or IP 1he instruction in progress is RL1I or any write to IL or IP
registers registers
andling of Interr:pts (2/S) andling of Interr:pts (2/S)
I an interrupt lag is actie but not being responded to I an interrupt lag is actie but not being responded to
or one o the aboe conditions, must be still actie or one o the aboe conditions, must be still actie
when the blocking condition is remoed, or the denied when the blocking condition is remoed, or the denied
interrupt will not be sericed interrupt will not be sericed
Next step is saing the registers on stack. 1he Next step is saing the registers on stack. 1he
hardware hardware--generated CA causes only the contents o generated CA causes only the contents o
the Program Counter to be pushed onto the stack, and the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address o the reloads the PC with the beginning address o the
serice routine serice routine
In some cases it also clears the lag that generated the In some cases it also clears the lag that generated the
interrupt, and in other cases it doesn interrupt, and in other cases it doesn t. It clears an t. It clears an
external interrupt lag ,IL0 or IL1, only i it was external interrupt lag ,IL0 or IL1, only i it was
transition transition--atiated. atiated.
andling of Interr:pts (3/S) andling of Interr:pts (3/S)
laing only PC be automatically saed gies laing only PC be automatically saed gies
programmer more reedom to decide how much time programmer more reedom to decide how much time
to spend saing other registers. Programmer must also to spend saing other registers. Programmer must also
be more careul with proper selection, which register to be more careul with proper selection, which register to
sae sae
1he serice routine or each interrupt begins at a ixed 1he serice routine or each interrupt begins at a ixed
location. 1he interrupt locations are spaced at 8 location. 1he interrupt locations are spaced at 8--byte byte
interal, beginning at 0003l or Lxternal Interrupt 0, interal, beginning at 0003l or Lxternal Interrupt 0,
000Bl or 1imer 0, 0013l or Lxternal Interrupt 1 000Bl or 1imer 0, 0013l or Lxternal Interrupt 1
and 001Bl or 1imer 1, shown in the ollowing tables and 001Bl or 1imer 1, shown in the ollowing tables
andling of Interr:pts (4/S) andling of Interr:pts (4/S)
andling of Interr:pts (S/S) andling of Interr:pts (S/S)
Lxecution o serice routine continues rom that Lxecution o serice routine continues rom that
location until the end, that is until it encounters RL1I. location until the end, that is until it encounters RL1I.
RL1I instruction does two things RL1I instruction does two things
It inorms the processor that this interrupt routine is inished It inorms the processor that this interrupt routine is inished
Secondly, reloads the PC rom the top bytes rom the stack Secondly, reloads the PC rom the top bytes rom the stack
Similar result could be accomplished with RL1, with Similar result could be accomplished with RL1, with
the distinction that the interrupt control system would the distinction that the interrupt control system would
be thinking an interrupt was still in progress be thinking an interrupt was still in progress
Reset Reset
1he reset input is RS1 pin 1he reset input is RS1 pin
1o accomplish a reset the RS1 pin must be held high or at least 1o accomplish a reset the RS1 pin must be held high or at least
two machine cycles two machine cycles
In the response on the RS1 signal, CP& generates an internal In the response on the RS1 signal, CP& generates an internal
reset reset
1he external reset signal is asynchronous to the internal clock 1he external reset signal is asynchronous to the internal clock
In the internal reset algorithm, 0s are written to all the SlRs In the internal reset algorithm, 0s are written to all the SlRs
except the port latches and Stack Pointer except the port latches and Stack Pointer
1he port latches are initialized to lll and Stack Pointer to 0l 1he port latches are initialized to lll and Stack Pointer to 0l
Driing AL and PSLN pins to 0 while reset is actie could Driing AL and PSLN pins to 0 while reset is actie could
cause the deice to go into an indeterminate state cause the deice to go into an indeterminate state
1he internal RAM is not aected by reset. On power up the 1he internal RAM is not aected by reset. On power up the
RAM content is indeterminate RAM content is indeterminate
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Introduction Introduction
Architecture Architecture
Operation Operation
#egi.ter. #egi.ter.
80SJ Registers 80SJ Registers
PSW: Program Stat:s Word PSW: Program Stat:s Word
(bit addressable) (bit addressable)
1he PS register contains seeral status bits 1he PS register contains seeral status bits
that relect the current state o the CP& that relect the current state o the CP&
IL: Interr:pt Lnable Register IL: Interr:pt Lnable Register
(bit addressable) (bit addressable)
I the bit is 0, the corresponding interrupt is I the bit is 0, the corresponding interrupt is
disabled. Otherwise, the interrupt is enabled. disabled. Otherwise, the interrupt is enabled.
IP: Interr:pt Priority Register IP: Interr:pt Priority Register
(bit addressable) (bit addressable)
I the bit is 0, the corresponding interrupt has a I the bit is 0, the corresponding interrupt has a
lower priority and i the bit is 1, the interrupt has lower priority and i the bit is 1, the interrupt has
a higher priority a higher priority
1C: 1imer/Co:nter Control 1C: 1imer/Co:nter Control
Register (bit addressable) Register (bit addressable)
1MD: 1imer/Co:nter Mode 1MD: 1imer/Co:nter Mode
Control Register (not bit addressable) Control Register (not bit addressable)

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