Department of Technical Education

Andhra Pradesh
Name : K. Sri Lakshmi
Designation : Lecturer in ECE
Institute : Govt. Polytechnic for Women Kakinada
Scheme : C-05
Semester : III Semester
Branch : Computer Engineering
Sub Code & Title : CM-305, Digital Electronics
Topic : Logic families Q Flip Flops
Duration : 50 Minutes
Subtopic : RS,T and D Flip- Flops.
Teaching Aids : PPT
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Objectives

On completion of this period, the student will

be able to

• Draw the block diagrams of RS, T, and D Flips.

• Working of RS, T and D flips –flops.

• Waveforms and Truth tables of RS, T and D- flip

flops.

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Recap
1. What are the two latches you have learnt in the
last class ?
NAND latch, NOR Latch.

4. What are the two Inputs of a latch ?

Set (s) and Reset (R )

7. How many output are present for a latch ?

Two.

10. What are they ?

Q and Q

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CLOCKED R-S Flip Flop

In the latches, any change in input at R or S is

transmitted immediately to the output Q and Q

according to the truth table.

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 Adding two NAND gates at the R and S inputs as shown
below Fig(1) result in a flip flop that can be enabled or
disabled.

S R' Q

Enable Or
C LK
Q
R
S' S Q
Circuit Diagram Clk
Fig 1 R Q

Fig 2. Logic Symbol

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• When the ENABLE input is high,information at the R

and S inputs will be transmitted to outputs. The latch

is enabled.

• When the Enable input is low, the outputs will retain

the same state as previous.

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• Now there are three inputs R,S and the Enabled input or

clock input labeled as CLK.

This Enabled or Clock prevents the flip flop from changing

•

states until the right time. This is also known as triggering

the flip flop.

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Table 1 The truth table of an R-S-T flip flop is shown below.

Inputs Outputs

CLK R S Q Q
0 X X N.C NC
1 0 0 N.C N.C
1 0 1 1 0
1 1 0 0 1
1 1 1 * *

Table 1

Clocked R S Flip flop Truth Table

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• When Clock is low, the outputs are latched in its
previous state. (No change)

• When clock is high, the Flip flop will set if S is high

and R is low.

• When clock is high, the FF will reset if S is low and

R is High

• When CLK, R and S all high, is a forbidden state

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 Fig 2.Timing Diagram of Clocked R-S Flip flop

CLK

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 T-Flip Flop

• This flip flop changes state or toggles each time a

clock pulse is received on its input T.

• The logic symbol is shown in the fig(2) below.

Q
Inpu T F/F Outputs
t Q

Fig 3 Symbol of a T- Flip Flop

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• For a square wave input at T, the outputs Q and Q are
shown below.

• The output changes only when the input at T goes from

low to high .

Q
Fig 4 The output wave form of a T-Flip Flop

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 D- Flip Flop
• The D Flip-flop or data flip flop is used to store one bit of
information or data.

• Thus the output frequency is of one half its input

frequency.

• It has two inputs namely the ‘D-input’ and the ‘clock’.

• The data present on the D-input will be transferred to the

output of the flip flop on the arrival of the clock pulse.

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• The logic symbol and truth table is shown in the figure 5 and
Table
Data D Q
Inputs D-F/F Outputs
Clock CLK Q

Fig5 Logic symbol

D-F/F

Input Output
CLK D Qn+1
1
0 0

1 1
1
0 X Qn
Table 2. Truth Table of D-F/F
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• The D-F/F is also called Delay Flip Flop.

• The Data input D is delayed by one clock pulse from

getting to output Q.

• It can be observed from the truth table that the output

Q follows input D after one clock pulse.

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A D-flip flop may be formed from a clocked R-S flip

flop by adding an inverter as shown below Figure(6).

S Q
CLK

R Q

Fig 6. D Flip Flop from R-S Flip Flop

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CLK
D

Fig 7. Wave forms of a D-Flip Flop

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Summary

In this class we have discussed.

• Working of clocked Rs Flip –flop

• Working of D flip –flop

• Working of T flip – flop

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Quiz

1. The flip – flop used to provide delay is

(c) D- flip flop

(e) T – flip flop

(g) Both (a) and (b)

(i) None.

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1. The flip – flop whose output change for every for
every input clock pulse is

(c) D- flip flop

(e) T- flip flop

(g) Both (a) and (b)

(i) T- flip flop

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 Frequently asked questions

3. Explain the working working of clocked RS flip flop.

Write its truth table.

5. Explain the working of T and D flip-flops.

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