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9/22/2005
Lecture 9
Objectives
Show you whats inside the box of RAM chips Be familiar with the general design of SRAMs and DRAMs Understand the differences between these two memory technologies Understand the details of the Xilinx Block SelectRAM youll be using in the labs
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Lecture 9
Review Questions
Describe the concepts behind memory-mapped I/O How is memory-mapped I/O used in ECE 412?
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Lecture 9
Review Question
1. Describe the concepts behind Memory-Mapped I/O
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Lecture 9
Review Question
2. How is Memory mapped IO used in ECE412
The PCMCIA attribute memory and common memory is mapped into the kernel space by the meta handler invoked by the insertion of the card. The device driver uses memory mapped IO to read attribute memory for device identification, etc. Memory mapped I/O allows device drivers to be written in C and compiled by a standard C compiler
9/22/2005
Lecture 9
Whats a RAM?
Random Access Memory Two main types: Static RAM (SRAM) and Dynamic RAM (DRAM)
Differences lie in how bits are stored Other types: Flash RAM, SDRAM, Video RAM, FERAM
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Lecture 9
Address
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Word Line
!Bit
Bit
Write: Drive word line, drive new value (strongly) on bit lines
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Lecture 9
Read
Write
Note: CE signal is often active-low as opposed to how shown here. SRAMs also generally have a write enable signal
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Read: Drive word line, sense value on bit line (destroys saved value)
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Lecture 9
Dynamic RAM
Slower High density (1 transistor/bit) Unstable (needs refresh)
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Lecture 9
Speeding up RAMs
Making random accesses faster is hard
Time to charge word, bit lines significant and growing Trade-off between drive of bit cell and size
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Lecture 9
Latch
Later accesses to the RAM can eliminate the row access time, just need column access time
Most common in DRAM, pagemode SRAMs also exist
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Lecture 9
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Lecture 9
SDRAM
Uses clocked organization to pipeline for speed
Flash RAM
Non-volatile (holds data without power)
FERAM
Uses magnetic technology (similar to hard disk) to store data
Holds value when power off Capacity, access time similar to RAM (hard disks take ms)
Nanotech RAMs
Molecular electronics, carbon nanotubes Nowhere near ready for prime time
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Lecture 9
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Lecture 9
Dual ported, can be aggregated to form larger structures Parity bits, possible to pre-load with data in VHDL
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Lecture 9
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Lecture 9
Interface Signals
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Lecture 9
Supported Configurations
Your VHDL will instantiate using primitives Each reference is an individual BRAM Could form larger memory block by assembling number of primitives, routing delay would determine total access time.
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Lecture 9
Physical Location
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Lecture 9
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Lecture 9
Next Time
Interrupts
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Lecture 9