Session 1 DR

Modern VLSI Design - Challenges
Rajendra B. Datar (Ph.D.)

Director, Engineering
www.sasken.com
© Copyright 2003 Sasken Communication Technologies Limited
Key Enablers for today’s
Single Chip Designs
•400 Million+ Transistors!

•2 Million+ Lines of Software Code!
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A Glance at the Chip Fabrication Process
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Today’s Transistor Fabrication Technology
• 150, 100 Nano Meters in Production
• 90, 60 Nano Meters in Pilot Production
• 45 Nano Meters and lower at R& D
•Transistors have now been fabricated at single or

two atom dimensions
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Today’s Silicon Wafers and Production Scales
•12 Inch diameter – Today

•6, 8, 10 Inch diameter- in the past
• It is quite common to produce 1-2 million

working devices per month for a given chip
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Effect of Smaller Transistor Geometry – On Cost
0.5 Micron
0.25 Micron
0.1 Micron
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Effect of Smaller Transistor Geometry –
New Functionalities
Intel P4 – Yr 2000
Intel P2 – Yr 1997 Intel P3 – Yr 1999
42 million
7.5 million 10 million
Transistors
Transistors Transistors
0.18 Micron
0.35 Micron 0.25 Micron
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Example of very high volume needs..
•Cell phone with Multi Media
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Multi Media Applications
Home Theater
CD Player
DVD Player
MP3 Player Multi -Media

Applications
AM/FM
Radio/Clock
Game
Machine
Camcorder DTV/HDTV
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Wireless Access
Wireless
Novatel
Wireless Access
Conventional
Ovation PDA – GSM/GPRS/CD
GSM/UMTS & MA Cell phone
802.11b/g
Laptop with
Wifi/Wimax
access
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System on
Application
Chip - hardware
Sw / Fw
RTOS
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Hardware Challenges…present
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Features of Modern Designs
• Deep Sub Micron – 130, 90, 60 nanometers

geometries. GHz Clock speeds.
• 10” wafers and Mask Making
• CMOS , BiCmos, SiGe and other processes
• Testability for 250 million+ transistors
• Very High Pin Counts and Packaging
• Correct by construction design tools
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Deep Sub Micron – 130, 90, 60 nanometers
•Transistor Modeling for accurate simulation
•2 Dimension Transistor modeling is insufficient
to ensure that the circuits will function as expected
•3 Dimension models have been evolved and used
•Operating Voltage levels have been scaled down as
follows;
•5V, 3.3V, 1.8, 1.2 Volts..
•These voltage levels make the design difficult
since noise margins have decreased. Critical for
I/O and analog
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Deep Sub Micron – 130, 90, 60 nanometers
•Substrate noise is impacting the design and substrate
currents impacts the power dissipation
•Operating Speeds at GHz make the inter block and
inter module timing closures very challenging
•Multiple clock generators on the same chip
•Power dissipation due to high clock speeds is another
design issue that needs careful attention such as
• Asynchronous designs
•Dynamic scaling of current drives
•Dynamic scaling to lower frequencies
•Power Reduction sw compiler design
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Efficient and integrated design tools
•Integration
•Circuit Design, Physical Design
•Transistor Level, Block Level and Chip Level
such as Spice, NanoSim, UltraSim,
RTLSimulators
•System level simulation

•C/C++ Models, System Verilog, System C
•RTL Models – Verilog, VHDL
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10” Wafer Processing and Mask Making
•Effect of deposition/etching gradients on the wafer
•Thick oxide thickness can very over the wafer from one
end of the diameter to the other end and this alters the
transistor behavior.
•Sub micron geometries and large wafers make the masking
and transistor deposition / interconnections very demanding
for repeatability and reliability
•Metal contacts, Consistent interconnect thickness and
width may become an issue
•Very high cost of masks for sub micron process add up to
the cost of each device.
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CMOS , BiCmos, SiGe and other processes
•Designers need to have good functional understanding of
transistor performance and limitation in each process.
•Low power by CMOS and specialized RF/GHz
frequency by Bipolar/Silicon Germanium transistor
circuits
•Need to understand the limitations of the models and
ensure that the specifications are met at all extreme
conditions – Process Corners, Temp, Voltages
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Testability for 250 million+ transistors
•All Transistors work as expected and are covered for their

functionality while testing
•If this was to be implemented as stated then a single
64Kb Ram Chip will need 2 years to be checked that all
bits can be written and read successfully!!
•Several different ways that are fast and accurate has been
evolved over the years;
•Scan Test, Boundry Scan, JTAG
•Built in Self test (Bist)
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Hw / Sw Concurrent Design
Concurrent hardware and software design has become the

critical requirement. Architecture improvements possible by
early checks of application on simulator.
Simulators / Emulators give a good deal of idea of the

efficiency of the processors for a given application code
Good one to one functional correspondence exists between

hardware RTL model and Sw C/C++ model for the processor.
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Hardware – Software Partitioning
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Overview of Video Decoder
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• Differences in profiles
Simple vs Main -
• Loop Filter
• B frames,
• High BitRate, (2 Mbps vs. 384 kbps)
• U/V Q-pel resolution
• Extended MV
• Intensity Compensation / Range Reduction
Main vs Advanced
• Slice layer
• Interlaced frame / field support.
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Potential HW blocks for Video Decoder on VLIW DSP
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Example Hw / Sw partitioning
• In-Loop Filter
• Inputs:
• 8x4 pixels (4 rows of 8 pixel each) (8-bits per pixel) { @ 14.4 k-set
per sec. (QVGA-30fps) }
• 3 (1-D filters of 4 coefficient-taps (3 bits precision)) on each row.
• Non-linear decision logic on the outputs based on quantization
parameters.
• Outputs:
• Corrected 2x4 pixels (12 or 8 bit output).
• HW performance expectation @ 200 MHz: 75 cycles per output 4-pixel
edge
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MIPS Savings by using HW accelerator Blocks
Module FW MIPS FW MIPS with HWA MIPS Savings Gate count Power
Consumption
Loop Filter 40 5 35 TBF TBF
(2 HW + 3 FW MIPS)
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Advantages of partitioning
• HW acclerator blocks for a given application can help use less

complex dsp or even conventional processors such as ARM or RISC
• HW Acclerator blocks can be made generic to include all
Audio/Video or Communication applications to be developed on a
given processor. Following factors also impact the decision
• Need of additional silicon for hw accelerators and cost of that
• Power dissipation
• Tools to be enhanced for including revised instruction set
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•New Applications of high volumes
•Consumer Electronics
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New Applications
•Upto 480 Mbps air data rates

•Upto 10 meters operating
distance
•This wireless hub provides wireless

transmission of data between a PC and
existing wired USB devices – Keyboard,
Mouse, HDD, DVD, Printer, Digital Camera
and so on.
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•New initiatives
Nano Engineering
Breakthrough Equipments
•Scanning Tunneling Microsocope

•Atomic Force Microscope
•http://pubs.acs.org/cen/nanotechnology/7842/7842instrumentation.html
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Nanotechnology Examples
•After arranging a few dozen cobalt atoms as an
ellipse on a copper surface and imaging the
assembly (purple ring on orange, bottom), IBM
researchers use a complementary imaging
technique to show that when a single cobalt
atom is placed at one of the focus points of the
ellipse, certain electronic properties (such as
spin, indicated by spheres with arrows) are
detected in the vicinity of the focuspoint atom
(large peak, top curve). A lowerintensity
projection of those properties appears as a
phantom atom at the other ellipse, even
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Nanotechnology Examples
•This image of 112 carbon monoxide
molecules on a copper surface was
made at IBM's Almaden Research
Center using a scanning tunneling
microscope. Each letter is 4 nm high
by 3 nm wide. About 250 million
nanoletters of this size could be
written on a cross section of a
human hair; this corresponds to 300
300page books.
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Summary of Challenges
• Strong understanding of the transistor functionality specifically in

view of the shrinking geometry
• Transistor Modeling limitations and robust designs to take care of
those limitations
• Adaptability to learn new modeling, simulation languages
• Hardware and Software partitioning to efficiently use the hw speeds
and sw based functional enhancements features
• Impact of the overlap of fundamental sciences – chemistry, physics
in the nano scale era and its use for new engineering applications
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Modern VLSI Design - Challenges

Rajendra B. Datar (Ph.D.)

•400 Million+ Transistors!

• 150, 100 Nano Meters in Production

• 90, 60 Nano Meters in Pilot Production

• 45 Nano Meters and lower at R& D

•Transistors have now been fabricated at single or

•12 Inch diameter – Today

• It is quite common to produce 1-2 million

•Cell phone with Multi Media

MP3 Player Multi -Media

• Deep Sub Micron – 130, 90, 60 nanometers

•System level simulation

•All Transistors work as expected and are covered for their

Concurrent hardware and software design has become the

Simulators / Emulators give a good deal of idea of the

Good one to one functional correspondence exists between

• HW acclerator blocks for a given application can help use less

•Upto 480 Mbps air data rates

•This wireless hub provides wireless

•Scanning Tunneling Microsocope

• Strong understanding of the transistor functionality specifically in

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