DN2076K10 Virtex-6 based Hardware Emulation System

CONFIDENTIAL

HES Hardware Emulation System

DVM Software and HES Boards

DVM Features
Design Verification Manger Software Automatic Design Partitioning w/ LVDS Signal Multiplexing Clock Conversion and Analysis (Convert multiple clock domains to one) FPGA Synthesis and P&R Tool Flow Management HDL Co-Simulation Interface with Riviera-PRO SystemC/C/C++ Testbench Wrapper for Acceleration Prototyping API and Function Library (Interface with C++ domain) Blackbox Functionality (Excludes modules from acceleration) Memory Model Mapping (Maps user memory to on-board memory) Static Debugging Probes (Preserve internal signals for probes) Static Debugging Probes w/ Xilinx ChipScope Pro Static Debugging Probes w/ Aldec Logic Analyzer (ALA for SCE-MI) SCE-MI 2.0 Hardware/Software Infrastructure (SCE-MI C++ API) SCE-MI 2.0 Co-Simulation Interface with Riviera-PRO Dynamic Debugging for SCE-MI Emulation Hardware Debugger Memory Viewer (Read/Write access to memory instances on board) OVL Assertions Support Vector Based Emulation

Proto

Xcell

Elite
4

DN2076K10_PCIE_ABC Package
Design Verification Manager Software HDL Co-Simulation Interface with Riviera-PRO SCE-MI 2.0 Hardware/Software Infrastructure

Static and Dynamic Debugging Probes

Clock Conversion and Analysis Riviera-PRO Software Verilog/VHDL/SystemVerilog HDL Simulator Linux/Windows 32/64-bit Platform Support DN2076K10 with 2GB DDR-3 SODIMM

3 Xilinx XC6VLX760-1 for DUT (~18M ASIC gates) 1 Xilinx XC6VLX240T-1 for HES controller 1 Xilinx XC6VLX130T-2 for Dini ConfigFPGA
PCIe x8-lane host interface
5

Xilinx Virtex-6 FPGA

Source: Xilinx DS150 Virtex-6 Family Overview http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf

HES Product Selection Guide

HES Software Design Verification Manager (DVM) Elite Design Verification Manager (DVM) Xcell Part # DVMEL DVMXL Description DVM Software, Elite (EL) Bundle. Includes debugging, clock conversion, memory models, automatic partition. 1 Year Floating TBL Note Availabl e Availabl e Availabl e

DVM Software, Xcell (XL) Bundle. Includes debugging, clock conversion, memory models, automatic partition. 1 Year Floating TBL
Mixed VHDL/Verilog/EDIF and SystemVerilog (Design) simulation with waveform viewer, advanced debugging.1 Year Floating TBL Description HES Accelerator Board with PCIe interface, 1 Xilinx Virtex5 LX330 devices and 2x 1GB DDR2 memories HES Accelerator Board with PCIe interface, 2 Xilinx Virtex5 LX330 devices and 2x 1GB DDR2 memories DiniGroup DN2076K10 Board with PCIe interface, equipped with HES controller, 2 Xilinx Virtex6 LX760 devices and 3x 4GB DDR3 DiniGroup DN2076K10 Board with PCIe interface, equipped with HES controller, 4 Xilinx Virtex6 LX760 devices and 3x 4GB DDR3 7 DiniGroup DN2076K10 Board with PCIe interface, equipped

Riviera-PRO (LVT)

RLVT

HES Hardware HES5XLX330EX 1x V5LX330 HES5XLX660EX 2x V5LX330 DN2076K10-2X760 2x V6LX760 DN2076K10-4X760 4x V6LX760 DN2076K10-6X760

Est. G.C.
2MG 4MG

Availabl e Availabl e Request

12MG

24MG

Request

DN2076K10 Virtex-6 based Hardware Boards

CONFIDENTIAL

DN2076K10 Outlook

DN2076K10 Outlook
SODIMM DNMEG P203 FPGA F FPGA G SODIMM FPGA C FPGA B FPGA A (U0) FPGA E FPGA D (U3)

DNMEG P204 DNMEG P205

SODIMM

10

DN2076K10 Peripherals

11

DN2076K10_PCIE_ABC

12

DN2076K10 Host Connection

13

DN2076K10_PCIE_ABC Hardware Deliverables

Item
Main Board

Description
4-lane GEN1 PCIe (v1.1) host interface 3 (three) V6LX760 -1 for FPGA B, C and A for user design 1 (single) V6LX240T-1 for FPGA G for HES Controller 1 DDR3 SODIMM socket on FPGA B Support standard, off-the-shelf laptop DDR3 memory (SODIMM), 400 MHz, 800 Mb/s with -1 speed grade (PC3-6400) 2GB DDR2 in a 204-pin DDR3 form factor SODIMM (DNSODM204_DDR2_2GB) 400-pin FCI MEG-Array connector 2x 400-pin MEG-Array connectors on FPGA A PCIe host adapter card (DNPCIe_CBL) PCIe cable (iPASS cable, 2M) RS232 serial cable, DB9-to-IDC cable adapter USB 2.0 cable Ethernet cable (CAT6) ATX power supply
14

Memory Expansion

External I/Os

Accessories

DN2076K10 Hardware Parts

15

Software Deliverables
Item DVM-Proto software Description Design Verification Manager (DVM) software for compilation and debug on user design Host Interface Module (HIM) IPs Host C/C++ API Diagnostic testing FPGA configuration Clock settings Reference design for diagnostic testing Reference design for DDR3 Reference design for DDR2 Datasheet and user manual Schematics in pdf format Netlist in ASCII format (for FPGA connections only) Daughter card schematic and layout files for DNMEG_Intercon and DNMEG_Observation

Dini Emu software Reference design

Documentation

16

EMU Software from Dini

17

DN2076K10 Board Features

Memory Expansion
3 separate DDR3 SODIMMs
64-bit, with addressing/power to support 4GB in each socket 400 MHz, 800 Mb/s with -1 speed grade

Alternate pin compatible memory cards available

SRAM: QDR, ASYNC, STD, or PSRAM, FLASH DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2

Clocking
On-board clock synthesizer for low-skew global clock networks
G0, G1, G2 :2kHz to 700 MHz

User configurable via Marvell uP RS232, USB, PCIe, or Ethernet

Others
Status FPGA-controlled LEDs External +12V ATX power supply with a PCIe power connector Full support for embedded logic analyzers via JTAG interface
18

Prototyping FPGA Configuration

Download bit file by Dini EMU software
USB Pen drive, standalone Standard JTAG with JTAG host interface
Using JTAG cable and Xilinx programming software

USB cable with USB host interface

Drivers are provided in EMU software

Ethernet cable with 10/100/1000 Ethernet host interface

No drivers are required

Download bit file by HES-Proto

HES Prototype API
HesProtoBoardInit() : Initialize board with HIM (BWRP/FWRP) HesProtoBoardProgram() : Initialize board with no-wrapper

DVM tools
prototol
19

SODIMM (DDR3) Connectors

DDR3 SODIMM socket connectors connected to FPGA B/D/G
The sockets accept standard off-the-shelf DDR3 laptop memory These sockets can also be used for types of memory other than DDR3 DNSODM204_DDR2_2GB
2GB DDR2 in a 204-pin DDR3 form factor SODIMM 8 separate 512Mx8 DDR2 memories (MT47H256M8) arranged in a 256M x 64 configuration for a total of 2GB

20

Daughter Card Connectors

The primary means of interfacing to the FPGA with external IO are through the 400-pin MEG-Array expansion connectors.
MEG-Array is a high speed BGA mezzanine connector designed to meet the needs of up to 10 Gb/s (http://www.fciconnect.com/megarray) There are three of these high-speed, high-density connectors on the board, connected to FPGAs A and D DNMEG_EXT: 14mm Riser Card for DNMEG Expansion Cards

21

Illustrated HES Environment

Tools
Platform OS HDL Simulator

Description
Linux 2.6.18-194 x86_64 (CentOS 5.5) Riviera-PRO-2011.06 x86_64

Emulation Software
Emulation FPGA Hardware FPGA Synthesis FPGA Implementation SystemC TLM OVP C/C++ Compiler Host Workstation

DVM2011.04
DN2076K10 (2~6 Virtex-6 LX760, PCIe host interface) Xilinx ISE13.1, xst Xilinx ISE13.1 systemc-2.2.0 TLM-2009-07-15 Imperas.20110223 gcc version 4.1.2 Intel Core i5-760 / QuadCore / 2.80GHz 16GB (4x4GB) DDR3 Memory

22

Design Verification Manager

CONFIDENTIAL

DVM Design Verification Manager

Multi-HDL support (Verilog, SystemVerilog, VHDL, SystemC, C/C++)
Static and Dynamic debug options Supports excluding instances from hardware by using Black-Box Incremental and block design synthesis Automatic ASIC clock conversion to FPGA Automatic partitioning and multiplexing of interconnections FPGA implementation flow management Console mode for scripting (TCL) Seamless integration with all HDL simulators (PLI, VHPI, etc.) direct link with the Aldec simulator kernel (performance!) HES-API available for C-testbench SDRAM, DDR and other external memories support

24

DVM GUI from RTL to Binary

25

HW Debugger GUI

26

HW Debugger Memory Viewer

27

HES for Prototyping, Acceleration and Emulation

CONFIDENTIAL

HIM USER IF and HES IF

USER IF: User Interface
This interface is used to connect to user design It has to be handled by user

HES BUS IF: HES On-board Interface

This interface provides on-board HES bus connection
It will be linked with board controller automatically by DVM software It is required that this interface is connected to design top-level ports Understanding this interface function is not required
HESPrototypeTop PCIe

C/C++ Testbench

HES Controller

HES IF Config

Host Interface Module (HIM)

DUT USER IF

HES Prototype API Example

Board Control API HesProtoBoardInit () Description Initialize board

HesProtoBoardProgram ()
HesProtoBoardReset () Bus Wrapper (BWRP) API HesProtoBwrpSingleWrite32bit ()

Initialize board with no-wrapper implementation

Send soft-reset signal to board Description Write 32-bit data to board

HesProtoBwrpBlockWrite32bit ()
HesProtoBwrpSingleRead32bit () HesProtoBwrpBlockRead32bit () FIFO Wrapper (FWRP) API HesProtoFwrpSingleWrite32bit () HesProtoFwrpBlockWrite32bit () HesProtoFwrpSingleRead32bit () HesProtoFwrpBlockRead32bit ()

Write number of 32-bit data in burst mode

Read 32-bit data to board Read number of 32-bit data in burst mode Description Write 32-bit data to FWRP Write number of 32-bit data to FWRP in burst mode Read 32-bit data from FWRP Read number of 32-bit data from FWRP in burst mode
30

Transaction-Level SCE-MI Emulation

31

32

SCE-MI Macro-based Transactors

Compliant with SCE-MI 2.0 macro-based interface Messages are exchanged via SceMi Message Ports using simple TransmitReady/ReceiveReady handshake

33

DVM Supports SCE-MI Infrastructure

SCE-MI: Standard Co-Emulation Modeling Interface
The SCE-MI standards from Accellera specifies components and protocols used in transaction communication between hardware and software parts in the co-emulation system The open standard insures portability of the verification environment

DVM Supports SCE-MI Interface at software/hardware sides

Header file and link libraries for SC/C++ SCE-MI testbench Verilog/VHDL SCE-MI macros for the connections to DUT

DVM Supports SceMiSim library for HDL/C++ co-simulation

Testbench used for simulation purpose is the same as used in the real SCEMI verification

34

Transaction-Level Emulation Example MicroBlaze SoC

External Clock Clock Generator 125Mhz MicroBlaze IXCL DXCL MPMC Interface External DDR2SODIMM

Reset Generator

ILMB DLMB MUX

IPLB DPLB

BRAM Memory

IPCore xps_timer

IPCore shutdown

IPCore xps_ps2

IPCore scemi2plb

IPCore xps_uartlite

IPCore scemi_video

IPCore xps_intc

XTOR shutdown

XTOR ps2

XTOR program

35

XTOR uart

XTOR video

MicroBlaze SoC Booting Linux

36

Aldec, Cadence, Proximus Utilize OVP Fast Processor Models in System Design Solutions New Flows Address Software Development, System Design, Co-Verification
http://www.imperas.com/archives/520

OXFORD, United Kingdom, June 3, 2011 Imperas today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with Aldecs Hardware Emulation Solutions (HES), Cadence Design Systems Virtual System Platform and Proximus products. OVPs position as the de facto source of instruction accurate processor core models provides additional value in the hardware-software co-verification, SystemC simulation, software development and system design flows supported by these tools.

37

38

39

HW/SW C0-Verification with OVP

Software Development Hardware Design

OVP Processor and Peripherals Model (Instruction Accurate) SCE-MI

RTL Simulation

Simulation Acceleration ALDEC HES FPGA-based Emulator

SCE-MI Emulation

40

Illustrated HES Environment

Tools Description

Platform OS HDL Simulator

Linux 2.6.18-194 x86_64 (CentOS 5.5) Riviera-PRO-2011.06 x86_64

Emulation Software
Emulation FPGA Hardware FPGA Synthesis FPGA Implementation

DVM2011.08
DN2076K10 (2~6 Virtex-6 LX760-1_ PCIe host interface Xilinx ISE13.1, xst Xilinx ISE13.1

SystemC
TLM OVP C/C++ Compiler

systemc-2.2.0
TLM-2009-07-15 Imperas.20110223 gcc version 4.1.2

Host Workstation

Dell T7400 or HP xw8600 with 32GB+memory

41

Transaction-based SoC Verification

DUT and RTB @ Hardware Emulator
DDR DIMM Cache Memory Multi-core Processors

JTAG XTOR
HW SW

SC/C++ Testbench @ Host PC

Multi-layer Bus Fabric DDR Controller UART

SRAM

Debug XTOR HW GDR SW

UART XTOR SW HW

Flash Memory
GPU Display Controller Sensor

USB XTOR SW HW

DMA

USB

Display XTOR HW SW

GbE XTOR SW HW

Ethernet

42

SC/C++ Testbench @ Host PC

Learn more about Aldec

Product Information Active-HDL: http://www.aldec.com/products/active-hdl Riviera-PRO: http://www.aldec.com/products/rivierapro ALINT: http://www.aldec.com/products/alint HES: http://www.aldec.com/products/hes Download Evaluation Software http://www.aldec.com/downloads

43

Transaction Level Co-Emulation with Virtual Platforms Live Webinars

Presenters: Louie de Luna, Aldec Product Manager, Piotr Czak, Aldec Application Engineer, Larry Lapides, Imperas VP Sales Date: Thursday, October 13, 2011 Time: 15:00 16:00 CET (21:00-22:00 CST)

Agenda Virtual Platforms: What are the benefits? SoC Design Flow with Virtual Platforms Imperas OVP and OVPsim TLM 2.0 Interface Integration of Aldecs Emulation System with OVP and OVPsim Processor Debugging, Memory Debugging, Hardware Debugging Live Demonstration Key Benefits
44