Resolution Function

Whats the difference between std_logic and std_ulogic?

The library ieee.std_logic_1164 has two types

std_logic and std_ulogic

To understand the difference, consider this circuit

where the blue signal line has more than one driver attached to it? (eg its a bus) How do we set up our model so that the simulator knows the rules? ie which signal overrides the others or how the signals combine together

Contending drivers
Remember that VHDL knows nothing about the IEEE 1164 rules To VHDL, the only primitive operations are those of a normal programming language addition, subtraction, etc assignment It does distinguish between signal and variable assignment, but only with respect to the timing of assignment of new values! ieee.std_logic_1164 is NOT part of the VHDL standard So when two std_logic values are applied to the same signal (ie wire), a VHDL simulator has to know that 1 overrides Z, U, X, H, L, 1 and 0 lead to X etc

Unresolved signals
std_ulogic is an unresolved type It is an error to define a model in which two drivers can set the value of an unresolved signal because there is no resolution function associated with the signal that can be invoked to determine which driver overrides the other It is defined simply: TYPE std_ulogic IS (U,X,0,1,Z,W,L,H,-); ie it is an enumerated type with possible values: U, This says nothing about the behaviour of std_ulogic signals Their behaviour is encoded in the functions (and, or, ) that take std_ulogic arguments On the other hand, std_logic is an resolved type

Unresolved signals
On the other hand, std_logic is an resolved type It is defined: (see maxplus2\vhdl93\ieee\std1164.vhd) SUBTYPE std_logic IS resolved std_ulogic; Note that there is a function definition just preceding this type:

FUNCTION resolved( s: std_ulogic_vector ) RETURN std_ulogic; SUBTYPE std_logic IS resolved std_ulogic;

Thus resolved is a function that takes a vector of std_ulogic elements and returns a value of std_ulogic type This function is called a resolution function It is called whenever two or more sources (signal assignments) drive a std_logic signal

Resolution functions
Any resolved signal (ie one that may be driven by two sources) is defined by a type that has a resolution function associated with it A resolved type is a subtype It can resolve a conflict of multiple instances of the parent type The name of the resolution function immediately precedes the name of the type being resolved The resolution functions argument is a vector of elements of the type being resolved The simulator will place the actual values to be resolved in this vector and call the resolution function eg with 3 drivers for a std_logic signal, the argument to resolved might be (Z, H, 1) which should return 1 return value is the parent type It will determine which of the values of the parent type result when the vector of signal values is applied

Writing resolution functions

You may never need to! std_logic_1164 defines the most commonly needed one! But, 1. You may be using integer types instead of std_logic_vector in a model of a processor for convenience speed in simulation You will need to define a resolved integer types if your model has a bus with multiple drivers in it You will need to have a convention for disconnecting a driver, eg setting a driver to emit 0 when its not driving the bus (where you would drive a Z with std_logic) You can also explicitly disconnect a driver with VHDLs DISCONNECT statement

Resolution functions
2. You may have defined an abstract type You (correctly) dont want to be bothered with implementation details yet Your bus is a collection of signals (address, data, command, etc); you have a type for each one; so the bus itself is defined as a VHDL RECORD The synthesizer will eventually convert it to logic for you! Again you will need a resolution function 3.

Simulation speed
std_ulogic does not have a resolution function associated with it it should use less simulation time (ie run faster) than std_logic With std_logic, the simulator may end up checking for (or calling) the resolution function for every assignment std_ulogic is recommended wherever possible It may save simulation time std_logic is a subtype, so it is possible to convert between them whenever necessary res_signal <= std_logic(unres_signal);

Std_logic AND: Un-initialized value

NOT 0 1 1 0 U U

AND 0 1 U

0 0 0 0

1 0 1 U

U 0 U U

OR 0 1 U

0 0 1 U

1 1 1 1

U U 1 U

0 AND <anything> is 0 0 NAND <anything> is 1

1 OR <anything> is 1 1 NOR <anything> is 0

Std_logic AND: X Forcing Unknown Value 0 X 1 U NOT

1 X 0 U AND 0 X 1 0 0 0 0 X 0 X X 1 0 X 1 U 0 U U

OR
0 X 1

0
0 X 1

X
X X 1

1
1 1 1

U
U U 1

0 AND <anything> is 0

1 OR <anything> is 0 0 NOR <anything> is 1

0 NAND <anything> is 1

Modeling logic gate values: std_ulogic

TYPE std_ulogic IS ( -- Unresolved LOGIC Z, -- High Impedance (Tri-State) 1, H, X, W, -- Forcing 1 -- Weak 1 -- Forcing Unknown: i.e. combining 0 and 1 -- Weak Unknown: i.e. combining H and L

L,
0, U, -, );

-- Weak 0
-- Forcing 0 -- Un-initialized -- Dont care

Example: multiple drivers

0 1

1
X 0

1 1

The rising transition signal

Vcc=5.5 25C 1

> 3.85 Volts

H X W L < 1.65 Volts Unknown 2.20 Volt gap

Multiple output drivers: Resolution Function

U U X 0 L Z W H 1 U U U U X U X X X 0 U X 0 0 L U X 0 L Z U X 0 L W U X 0 W W W W 1 X H U X 0 W H W H 1 X 1 U X X 1 1 1 1 1 X U X X X X X X X X

U X 0 L Z Suppose that U X first 0 W the gate outputs a 1 W the U X second gate outputs a 0 0 W H then U X mult-driver output is X X 1 1 the X: U X forcing unknown value by X X X combining 1 and 0 together

Multiple output drivers: Resolution Function

U U X 0 L Z W H 1 H <driving> L => W Observe that 0 pulls down all weak signals to 0 U X U X 0 U X 0 L U X 0 L Z U X 0 L Z W U X 0 W W W H U X 0 W H W H 1 U X X 1 1 1 1 1 U X X X X X X X X

Note the multi-driver resolution table is symmetrical

Resolution Function: std_logic buffer gate

1
H W, Z L 0 input: U output: U
0 0 L 0 W X X X Z X std_ulogic std_logic

1 1
X 0

0
H 1 1 1 X

0 or L becomes 0 Transition zone becomes X

H or 1 becomes 1

Resolving input: std_logic AND GATE

std_ulogic W std_ulogic 1 1 std_logic std_logic

std_logic X

Process each input as an unresolved to resolved buffer.

Then process the gate as a standard logic gate { 0, X, 1, U } For example, lets transform z <= W AND 1;
z <= W AND 1; z <= X AND 1; -- convert std_ulogic W to std_logic X -- now compute the std_logic AND

z <= X;

2-to-1 Multiplexor: with-select-when

a
structural

a Y b

0 1

behavioral

Y
Only values allowed

b S S
Y <= sa OR sb;
sa <= a AND NOT s; sb <= b AND s; WITH s SELECT Y <= a WHEN 0, b WHEN 1;

or alternatively
WITH s SELECT Y <= a WHEN 0, b WHEN OTHERS;

combinatorial logic

4-to-1 Multiplexor: with-select-when

Y <= sa OR sb OR sc OR sd;
sa <= a AND ( NOT s(1) AND NOT s(0) ); sb <= b AND ( NOT s(1) AND s(0) ); sc <= c AND ( s(1) AND NOT s(0) ); sd <= d AND ( s(1) AND s(0) );
Structural Combinatorial logic As the complexity of the combinatorial logic grows, the SELECT statement, simplifies logic design but at a loss of structural information

a
b c d

00 01

10
11

S
WITH s SELECT Y <= a WHEN 00, b WHEN 01, c WHEN 10, d WHEN OTHERS;

behavioral

oe x

Tri-State buffer
y

ENTITY Buffer_Tri_State IS PORT(x: IN std_logic; y: OUT std_logic; oe: IN std_logic ); END;

ARCHITECTURE Buffer3 OF Buffer_Tri_State IS BEGIN

WITH oe SELECT y <= x WHEN 1, -- Enabled: y <= x; Z WHEN 0; -- Disabled: output a tri-state END;

Standard Libraries
Include library ieee; before entity declaration. ieee.std_logic_1164 defines a standard for designers to use in describing interconnection data types used in VHDL modeling. ieee.std_logic_arith provides a set of arithmetic, conversion, comparison functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector. Ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and comparison functions for std_logic_vector.

IEEE 1076 Types

VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type)
bit - a signal of type bit that can only take values of '0' or '1' bit_vector - a grouping of bits (each can be '0' or '1')
SIGNAL SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending range b: BIT_VECTOR(3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that:a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0'

IEEE 1076 TYPES (contd.)

INTEGER
useful as index holders for loops, constants, generics, or high-level modeling

BOOLEAN
can take values TRUE or FALSE

ENUMERATED
has user defined set of possible values, e.g., TYPE traffic_light IS (green, yellow, red);

IEEE 1164
A package created to solve the limitations of the BIT type Nine values instead of just two ('0' and '1') Allows increased flexibility in VHDL coding, synthesis, and simulation STD_LOGIC and STD_LOGIC_VECTOR are used instead of BIT and BIT_VECTOR when a multi-valued logic system is required STD_LOGIC and STD_LOGIC _VECTOR must be used when tri-state logic (Z) is required To be able to use this new type, you need to add 2 lines to your code: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

1164 Types
std_logic and std_logic_vector are the industry standard logic type for digital design Values for Simulation & Synthesis
0 1 Z L H - -- Forcing 0 -- Forcing 1 -- High Impedance -- Weak 0 -- Weak 1 -- Dont care

Values for Simulation only (std_ulogic):

U X W -- Uninitialized -- Forcing Unknown -- Weak Unknown