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and Design
n
5-1
5-1 Instruction Codes u The user of a computer can control the process by means of a program u A program is a set of instructions that specify the operations, operand, the sequence(control) u A instruction is a binary code that specifies a sequence of microoperations u Instruction codes together with data are stored in memory(=Stored Program Concept) Instruc u The computer reads each instruction from memory and places it in tion a control register. The control then interprets the binary code of Cythe instruction and proceeds to execute it by issuing a sequence of cle microoperations. u Instruction Code :
l
15 12 11 0 A group of bits that instruct the computer to perform a specific operation Format l It is usually divided into parts(refer to Fig. 5-1Op. Code instruction format) Address u Operation Code : l The most basic part of an instruction code l A group of bits that define such operations as add, subtract, multiply, shift, and Korea Univ. of Tech. & Edu. Chap. 5 Basic Computer Organization and Design Computer System complement(bit 12-15 : 24 = 16 distinct operations) Dept. of Info. & Comm.
Instruction
5-2
The operation is performed with the memory operand and the content of AC Op. Code : specify 16 possible operations(4 bit) Address : specify the address of an operand(12 bit) If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose( 16 instruction : Tab. 5-2 , 25 instruction) Store each instruction code(program) and operand (data) in 16-bit memory word
Addressing Mode l l l
the second part of an instruction code(address field) specifies an operand the second part of an instruction code specifies the address of an operand the bits in the second part of the instruction designate an address of a memory word in which the address of the operand is found (Pointer )
One bit of the instruction code is used to distinguish between a direct and an indirect address : Fig. 5-2(a)
5-3
u Effective Address
l
The operand address in computation-type instruction or the target address in a branch-type instruction
5-2 Computer Registers u List of Registers for the Basic Computer : Tab. 5-1 u Basic computer registers and memory : Fig. 5-3
l l l l l l
Data Register(DR) : hold the operand(Data) read from memory Accumulator Register(AC) : general purpose processing register Instruction Register(IR) : hold the instruction read from memory Temporary Register(TR) : hold a temporary data during processing Address Register(AR) : hold a memory address, 12 bit width Program Counter(PC) :
hold the address of the next instruction to be read from memory after the current instruction is executed Instruction words are read and executed in sequence unless a branch instruction is encountered A branch instruction calls for a transfer to a nonconsecutive instruction in the program The address part of a branch instruction is transferred to PC to become the address of the next instruction To read instruction, memory read cycle is initiated, and PC is incremented by one(next instruction fetch)
Computer System
5-4
Input Register(INPR) : receive an 8-bit character from an input device l Output Register(OUTR) : hold an 8-bit character for an output device u Common Bus System l The basic computer has eight registers, a memory unit, and a control unit(in Sec. 5-4) l Paths must be provided to transfer information from one register to another and between memory and registers l A more efficient scheme for transferring information in a system with many registers is to use a common bus(in Sec. 4-3) l The connection of the registers and memory of the basic computer to a common bus system : Fig. 5-4
l
The outputs of seven registers and memory are connected to the common bus The specific output is selected by mux(S0, S1, S2) :
n n n n
Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6) Device AC INPR OUTR mux memory register bus When LD(Load Input) is enable, the particular register receives the data from the bus
Control Input : LD, INC, CLR, Write, Read Address Register : Address bus ( Bus address data )
n n
AC DR memory read (p. 146, LDA ) Memory write AC write (p. 147, STA )
Computer System
5-5
Accumulator(AC) : 3 Path
n n
1) Register Microoperation : clear AC, shfift AC, 2) Data Register : add DR to AC, and DR to AC( AC End carry bit set/reset), memory READ(DR ) 3) INPR : Device (Adder & Logic )
s2 s1 s0 M e m o r y u n it 4 0 9 6 1 6 A d d r e s s
B 7
u s
r ite A R
L D IN R C
R e a d
1
L R
P C
L D IN R C L R
D
L D IN R
R
C L R
A C
L D IN R C L R
IN P R
I R
L D
T R
L D IN R C L R
O
L D
T R C lo c k
1 6 -
b it
c o m
o n
b u s
Computer System
5-6
Memory-reference instruction
15 14
12 11
I Opcode
Address
Register-reference instruction
15 14 12 11 0 7xxx (7800 ~ 7001) : CLA, CMA, .
0 1 1 1
Register Operation
15 14
12 11
Symbol AND ADD LDA STA BUN BSA ISZ CLA CLE CMS CMEm CIR CIL INC SPA SNA SZA SZE HLT INP OUT SKI SKO ION IOF
Hex Code I =0 I =1 0xxx 8xxx 1xxx 9xxx 2xxx Axxx 3xxx Bxxx 4xxx Cxxx 5xxx Dxxx 6xxx Exxx 7800 7400 7200 7100 e 7080 7040 7020 7010 7008 7004 7002 7001 F800 F400 F200 F100 F080 F040
Description And memory word to AC Add memory word to AC Load memory word to AC Store content of AC in memory Branch unconditionally Branch and Save return address Increment and skip if zero Clear AC Clear E Complement AC Comp Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is 0 Halt computer Input character to AC Output character from AC Skip on input flag Skip on output flag Interrup Inter
Computer System
5-7
Arithmetic, Logical, and shift : CMA, INC, .. Moving information to and from memory and AC : STA, LDA Program control : BUN, BSA, ISZ Input/Output : INP, OUT
If the computer includes a sufficient number of instructions in each of the following categories
A master clock generator controls the timing for all registers in the basic computer The clock pulses are applied to all F/Fs and registers in system The clock pulses do not change the state of a register unless the register is enabled by a control signal The control signals are generated in the control unit : Fig. 5-6
The control signals provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator Two major types of control organization l Hardwired Control : Chap. 5 The control logic is implemented with gates, F/Fs, decoders, and other digital circuits + Fast operation, - Wiring change(if the design has to be modified)
Computer System
5-8
The control information is stored in a control memory, and the control memory is programmed to initiate the required sequence of microoperations + Any required change can be done by updating the microprogram in control memory, Slow operation
In s t r u c t io n r e g is t e r ( IR )
u Control Unit : Fig. 5-6 l Control Unit = Control Logic Gate + 3 X 8 Decoder + Instruction Register + Timing Signal l Timing Signal = 4 X 16 Decoder + 4-bit Sequence Counter l Exam) Control timing : Fig. 5-7
1 5
1 4
1 3
1 2
1 1
7 I
3 8 d e c o d e r 6 5 4 3
t h e r
in p u t s
0 D0
D7 .
. .
o n t r Co ol n t r o l o u t p u t s lo g ic g a t e s
T0 1 5 1 4 4 1 6 d e c o d e r
. . . . . .
, wait cycle .
4 - b it s e q u e n c e C le a r ( C L R ) c o u n t e r ( S C )
C lo c k
In c r e m
e n t ( IN
Computer System
. . . )
T1
5-9
T0 : AR PC
5-5
u Instruction Cycle
l
1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 ) 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive transition of the clock(T0 rising edge clock) 3) SC(sequence counter) is incremented : T0 : Inac0000(T0 ) 0000(T1 ) tive Instruction Cycle T1 : Active
1) Instruction Fetch from Memory l 2) Instruction Decode l 3) Read Effective Address(if indirect addressing mode) l 4) Instruction Execution l 5) Go to step 1) : Next Instruction[PC + 1] u Instruction Fetch : T0, T1(Fig. 5-8)
T0 : AR PC l T1 : IR M [ AR ], PC PC + 1
T0 = 1
T0 : AR content of PC onto the bus by making the bus selection inputs S2S1S0=010 1) Place the PC 2) Transfer the content of the bus to AR by enabling the LD input of AR
Computer System
510
l
T1 = 1
T1 : IR M [ AR ], PC PC + 1
1) Enable the read input memory 2) Place the content of memory onto the bus by making S2S1S0= 111 3) Transfer the content of the bus to IR by enable the LD input of IR 4) Increment PC by enabling the INR input of PC
T1= 1 T0= 1 0 1 0 1 1 1
u Instruction Decode : T2
T2 : D0 ,...., D7 Decode IR (12 14), AR IR (0 11), I IR (15)
s2 s1 s0 M M ee m m oo rr yy uu nn ii tt A d d r e s s R e a d
u s
D7=1
Register(I=0) D7IT3(Execute) Read efI/O (I=1) D7IT3 (Execute) fective D7=0 : Memory Ref. Indirect(I=1) D7IT3( ) Address AR M [ AR ] Direct (I=0) nothing in T3 W Register I/O T3 Memory Ref. T3 Operand effective address W Memory Ref. T4, T5, T6 : Fig. 5-11
A R
L D
P C
I N R
IR
L D
lo c k
o m
o n
b u s
511
u Register Ref. Instruction l r = D7IT3 :
D7 : Register or I/O = 1
[ A R
] ,
P C
P C
+ 1
e c o d e A R
T2 o p e r a t io n c o d e in IR IR ( 0 - 1 1 ) , I I ( 1 5 )
( 1 2 -
1 4 )
Instruction(Tab. 5-4)
u AND to AC D0T4 : DR M [ AR ]
( I/ O ) = 1 I
e g is t e r
o r
I / O 0) I
= =
1 M (
e m
o r y -
r e f e r e n c e
( r e g is t e r ) ( in d ir e c t ) I
1 0
( d ir e c t )
D0T5 : AC AC DR, SC 0
u ADD to AC M [ AR ] D1T4 : DR
T3 E x e c u t e E i n p u t - o u t p ur et g i in s t r u c t io n in S C 0 S
T3 x e c u t e A R s t e r - r e f e r e n c e s t r u c t io n C 0
T3 M [ A R ] N
T3 o t h in g
E x e c u t e e m o r y - r e f e r e n c e in s t r u c t io n S C 0
512
u STA : memory write
Fig. 5-10 Example of BSA
BSA 135 PC = 10 0 PC = 21 next instruction
D3T4 : M [ AR ] AC , SC 0
u BUN : branch unconditionally
D4T4 : PC AR, SC 0
u BSA : branch and save return address D5T4 : M [ AR ] PC , AR AR + 1
D5T5 : PC AR, SC 0
l
Return Address : save return address ( 135 : M [135] ) 21( PC ), 136( AR ) 135 + 1 21 D5T4 l Subroutine Call : Fig. 5-10 D5T5 : 136( PC ) 136( AR ), SC 0 u ISZ : increment and skip if zero
D6T4 : DR M [ AR ] D6T5 : DR DR + 1 D6T6 : M [ AR ] DR, if ( DR = 0) then ( PC PC + 1), SC 0
u Control Flowchart : Fig. 5-11
l
Computer System
513
n
These two registers communicate with a communication interface serially and with the AC in parallel Each quantity of information has eight bits of an alphanumeric code
FGI : set when INPR is ready( ), clear when INPR is empty 1 : Ready FGO : set when operation is completed( ), clear when output device is 0 : Not in the process of printing readyu Input-Output Instruction : Tab. 5-5 l p = D7IT3 : Address l IR(i) = Bi IR(6 -11) W B6 - B11 : 6 I/O Instruction u Program Interrupt
l
1) Programmed I/O, 2) Interrupt-initiated I/O, 3) DMA, 4) IOP 2) Interrupt-initiated I/O (FGI FGO 1 Int. ) Maskable Interrupt ( ION IOF Int. mask )
Computer System
514
l
In s tru c tio n
c y c = l e0
= 1
In te rru p t
c y c le
IEN = 0 : the programmer does not want to use the interrupt, so control continues with the next instruction cycle IEN = 1 : the control circuit checks the flag bit, If either flag set to 1, R F/F is set to 1
n
F e t c h a n d d e c o d e in s tr u c t io n
S to r e r e tu r n a d d in lo c a t io n 0 M [ 0 ] P C
I E E x e c u te in s tr u c t io n
= 0
= 1 = 1 B r a n c h P C F G I = 0 to lo c a t 1
= 1
O = 0
IE N R
0 0
The memory location at address 0 as the place for storing the return address Interrupt Branch to memory location 1 Interrupt cycle IEN=0 ( ISR Interrupt ISR ION )
0 256(return address) BUN 1120 Main Program 255 256
PC = 1 0
In te rr up t H er e
1120
515
n
5-8 Complete Computer Description u The final flowchart of the instruction cycle : Fig. 5-15 u The control function and microoperation : Tab. 5-6 5-9 Design of Basic Computer u The basic computer consists of the following hardware components
l l l l
Section
1. A memory unit with 4096 words of 16bits 2. Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC(Fig. 2-11) 3. Seven F/Fs : I, S, E, R, IEN, FGI, and FGO 4. Two decoder in control unit : 3 x 8 operation decoder, 4 x 16 timing decoder(Fig. 5-6)
5. A 16-bit common bus(Fig. 5-4) l 6. Control Logic Gates : Fig. 5-6 Box Control Output l 7. Adder and Logic circuit connected to the AC input u Control Logic Gates l 1. Signals to control the inputs of the nine registers l 2. Signals to control the read and write inputs of memory l 3. Signals to set, clear, or complement the F/Fs l 4. Signals for S2 S1 S0 to select a register for the bus l 5. Signals to control the AC adder and logic circuit
l Chap. 5 Basic Computer Organization and Design
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Computer System
516
u Register Control : AR
Control inputs of AR : LD, INR, CLR l Find all the statements that change the AR AR ? 5-6 in Tab.
l l
F r o m
1 2 B u s
A R
1 2
T o C
B u
Control functions
R ' T0 : AR PC
D 7' I T3 T2 R T0 D
5
L D
IN
L R
lo c k
LD( AR ) = R' T0 + R' T1 + D7 ' IT3 D7 ' IT3 : AR M [ AR ] CLR( AR ) = RT0 RT0 : AR 0 INR ( AR ) = D5T4 D5T4 : AR AR + 1
R ' T1 : AR IR (0 11)
T4
Control inputs of Memory : READ, WRITE Find all the statements that specify a read operation in Tab. 5-6 Control function
p
M [ AR ] ?
? M [ AR ]
J K Q 1 (t+ ) 0 1 0 1 0 1
pB7 : IEN 1
Control functions
B7 C B6 R T2 lo c k
J K
S E T
Q
IE N
L R
517
u Bus Control
l
S0 = x1 + x3 + x5 + x7 S1 = x2 + x3 + x6 + x7 S0 = x4 + x5 + x5 + x7
x1 = 1 :
Bus AR = Find ? AR
D4T4 : PC AR D5T5 : PC AR
x2 = 1 : Bus PC = Find ? PC
x1 x2 x3 x4 x5 x6 x7
Encoder
S0 S1 S2
x7 = 1 :
Computer System
518
n
Fig. 2-11
A c c u m u la t o r1 6 r e g is t e r ( A C ) T o
F r o m F r o m
D
8
R P R
IN
A d d e r a n d lo g ic c ir c u it
1 6
B u s
L D
IN
L C R
lo c k
Fig. 5-20
o n t r o l g a t e s
Computer System
519
u Control of AC : Fig. 5-20 l Find the statement that change the AC : AC ?
F r o m a n d D0 1 6 a d d e r lo g ic
L D
A C
1 6
T o C
u s
lo c k
A N A D D IN
1
D D
IN
L R
D0T5 : AC AC DR D1T5 : AC AC + DR D2T5 : AC DR pB11 : AC (0 7) INPR rB9 : AC AC rB7 : AC shr AC , AC (15) E rB6 : AC shr AC , AC (0) E rB11 : AC 0 rB5 : AC AC + 1
CLR INR LD
T5 D1 D2 T5 p B1 r B B
9
R P R O M R L C L R
S H
7
S H B
6
IN B
5
C B1
1
Computer System
520
u Adder and Logic Circuit : Fig. 5-21 ( 16 bit = 16 )
D R ( Ai ) C ( i)
( O A N C
i
u t p u t
o f L D
g a t e
in
F ig .
5 -
2 0 )
D D
J K Q 1 (t+ ) 0 1 0 1 0 1
A D D R
F A C
i+ 1
Ii ( F i g . 2 -
1 1 )
A C
( i)
IN P R F r o m I N P R b i t ( i )C O M S H A C A C R
lo c k
( i+ 1 ) S H L ( i1 )
Computer System
Mano Machine
521
n n n n
Integration !
n n
Fig. 5-4 : Common Bus(p.130) Fig. 2-11 : Register(p. 59) Fig. 5-6 : Control Unit(p. 137) Fig. 5-16, 17,18 : Control Logic Gate(p.161- 163) u Fig. 5-4 Component Control Input u Register, Memory, F/Fs, Bus Selection Fig. 5-20 : AC control(p.165) Fig. 5-21 : Adder and Logic(p.166)
Due Date : 1
Computer System