Adders

Full-Adder
A Cin B Cout Full adder Sum

The Binary Adder

A Cin B Cout Full adder Sum

S = A B Ci = ABC i + ABC i + ABCi + ABCi C o = AB + BCi + ACi

3

Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B

Delete = A B

Can also derive expressions for

S and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B

Complimentary Static CMOS Full Adder

VDD VDD A B A B Ci A B VDD Ci A B

X
A

Ci

Ci A B

S
Ci

VDD
A Co B Ci A

28 Transistors
5

A Better Structure: The Mirror Adder

VDD VDD A "0"-Propagate Ci "1"-Propagate A B A Generate B A B Ci A B B B Kill A Co Ci S Ci A B VDD Ci A B

24 transistors
6

Manchester Carry element

VDD Pi Ci Gi Co

Manchester Carry Chain

VDD P0 P1 P2 P3 C3 Ci,0 G0 G1 G2 G3

C0

C1

C2

C3

Carry-Select Adder
Setup
P,G

"0"

"0" Carry Propagation

"1"

"1" Carry Propagation

Co,k-1

Multiplexer
Carry Vector

Co,k+3

Sum Generation

Carry-Select Adders
Consider the Following Partitioned Addition:

101 101 110 + 110 111 001

101 +110 1 011 0 1 100 1 101 +111 100 0 101 1 1 100 100 111 110 +001 111 0 000 1

4-Bit Carry Select

X= +Y = sum cout sum cout 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0

} }

cin = 0

cin = 1

Answer: 1110 0011

cin 1 for Least Significant Nibble Must Wait for 4 Ripples to Select Can Divide into Groups of Two

2-Bit Carry Select

X= +Y = sum cout sum cout 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1

} }

cin = 0

cin = 1

Answer: 11 10 00 11
cin 1 for Least Significant 2 Bits Must Wait for 2 Ripples to Select Can Divide into Groups of One Carry Select

1 1

1 0

0 1

1 1

1 0

0 1

1 1 0 1

1 0 1

1 1 0 0 0

1
0

 This is also called as a conditional sum adder. The adder consists of two blocks 1. With logic 0 carry in 2. Other with logic 1 carry in The sum and carry out generated are then selected by the actual carry in which comes from the carry out output of the previous block as shown in the slide Let us consider an n bit ripple carry adder. The computational time T is given by T = k1*n Where k1 is the delay through one adder cell

 If adders are divided into blocks, each with 2 parallel paths, then the computation time T becomes T= k1(n/2) + k2 Where k2 is the time needed by the multiplexer of the next block to select the actual output carry Decision has to be made on the size, in bits, of each adder block & clearly this could be 1-bit, in which the number of multiplexers is maximum, or two or more bits resulting in fewer multiplexer. If there are many mux, the ripple through effect occures in the mux chain rather than in the carry through blocks.

 An optimum value of block size must be selected. Suppose an n bit adder is divided into M-blocks, & that each block contains P adder cells in series The computational time T far overall carry output signal is composed of two parts 1. The propagation delay through first block 2. The propagation delay through multiplexers T = Pk1 + (M-1)k2 Where n=M.P the minimum value of T is reached when M = (n1*k1/k2) If the delay in the mux is equal to the cell delay, then the size P of the succeeding block should be increased by one

 If the mux delay is twice that of the cell delay, then each block must have two more adder cells than the previous one i.e., P can be increased by two from one block to the next. The actual optimum increase in P from one block to its successor depends on the ratio b/w k1 & k2. The adder block need not to be ripple carry adders but may use any of the available enhancement techniques, such as carry look ahead orcarry skip techniques.

Carry Select Adder: Critical Path

Bit 03 Setup Bit 47 Setup Bit 811 Setup Bit 1215 Setup 0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1-Carry

1-Carry

1-Carry

1-Carry

Ci,0

Multiplexer

Co,3

Multiplexer

Co,7

Multiplexer

Co,11

Multiplexer

Co,15

Sum Generation
S03

Sum Generation
S47

Sum Generation
S811

Sum Generation
S1215

18

 It can be seen that the longest chain is the second one, which takes seven cell delay(from the 4th bit to 11th bit). the addition time is determined by the longest chain, and in this case it is given by T = 7*k + k Where k is the cell delay & k is the time needed to compute the 11th bit sum using the carry in to the 11th bit.

 The carry skip adder takes the advantage of both the generation & the propagation of the carry signal. They are divided into blocks where each for block, a special circuit is used to detect the condition when A & B bits differ in all bit positions in the block(i.e., Pi=1 for all I in the block) The o/p signal from such a circuit is called block propagation signal. If the block propagation signal =1, then the carry signal entering the block can bypass it and be transmitted through a mux to the next block.

Carry skip adder

A3 B3 A2 B2 A1 B 1 A0 B0

Co,3
Co,3

FA S3

FA S2

FA S1

FA S0

Ci,0

BP = P0 P1 P2 P3 Block Propagate

If (P0 & P1 & P2 & P3 = 1) then Co,3 = Ci,0 otherwise the block itself kills or generates the carry internally
S. Reda EN160 SP07

Optimization of carry skip adder

In this case we assume equal size blocks. Let k1 denote the time needed by the carry signal to propagate through the adder cell Let k2 denote the time needed for a carry to skip over a block. Let us divide the nbit carry skip adder into M-blocks, each block containing p adder cells. The total (worst case) propagation delay time T is: T = 2(P-1)*k1 +(M -2)k2 Where P=n/M The minimum value of T is reached when

M= (2n*k1/k2)

Carry Look Ahead Adder

gg 0

The Binary Multiplication

RESULT

35

Serial parallel multiplier

This multiplier is the simplest one, the multiplication being considered as a succession of addition If A = (an an-1 an-2 ..a0) & B = (bn bn-1 bn-2 b0) The product A.B = (A.2n.bn + A.2n-1.bn-1 + A. 2n-2.bn-2.,A.20.b0) The possible form of this adder for multiplying four bit quantities, based on this expression is shown in figure. D indicates D flip-flop & FA indicates a fulladder

0 1

0 0

0 0

1 0

Braun array
A3 B3 A2 B2 A1 B1 A0 B0

A3 B3

A 3 B2 A 2 B3 P5

A3 B1 A2 B2 A1 B3

A 3 B0 A2 B0 A1 B0 A0 B0 A 2 B1 A1 B1 A0 B1 A 1 B2 A0 B2 A 0 B3

P7

P6

P4

P3

P2

P1

P0