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# Sequential Circuits

## • In a sequential circuit the current output depend

not only on current input but also previous
outputs (state).
• Y=f( Current inputs, state information)
• Combinational circuit + memory gives sequential
circuit.
• Flip-Flop is the basic element in memory. It is
capable of storing 1/ 0.
• Ex: D-FF, T-FF, SR-FF,JK-FF
• Flip-flops can be constructed with NOR gates/
NAND gates.
Flip-Flop
(NOR Latch)
• SR Flip-Flop
• The Set Reset Filp-Flop is having 2 –inputs
(Set, Reset) and one complementary output.
• S=1, R=0 the flip flop sets
• S=0, R=1 the flip-flop resets
• S=R=1 denotes race condition (invalid-
operation)
• S=R=0 the flip flops retains previous output
(latching)
SR Flip Flop
NAND Latch
NAND S-R FF S’ Q’
S=R= 0 Invalid state
S=R= 1 Retain Last output Q
R’

## • A Bubbled NOR acts as NAND Latch ( Inputs complemented )

Clocked Flip-Flops
• The Changes in the out put is purely decided by
propagation delays. Hence this Flip flop is called as
Asynchronous Flip-Flop.
• In Synchronous or Clocked Flip Flop the change in
output is synchronized by external clock.
• If the changes are taking at the EDGES then flip-flop is
called as EDGE triggered Flip-Flop.
• If the Changes are controlled by level then the Flip-Flop
becomes level Triggered one.
• EDGE triggering is preferred to level triggering as it is
more immune to noise.
Clocked Flip-Flops
Level Triggering Edge Triggering

D D
CLK CLK CLK
CLK

## Positive Negative positive Negative

SR Flip-Flop
S R Qn
S Q’
0 0 Qn-1
0 1 0
4 0 1
Q
1 1 Ø R
SR Flip-Flop
SR
S R Qn-1 Qn
0 0 0 0 Qn-1 Ø 1
0 0 1 1
1 Ø 1
0 1 0 0
0 1 1 0
6 0 0 1 CHARACTERSTIC EXPRESSION
1 0 1 1 OF S-R FLIPFLOP
8 1 0 Ø Qn = S + R’ Qn-1
1 1 1 Ø
SR FLIP FLOP
• EXCITATION TABLE: Excitation table
denotes inputs needed to provide the
desired response at output (change)
Qn Qn-1 S R In S-R FF S is changed from 01

## O 0 0 Ø While R remains at 0 what is Qn if

QN-1 is 0?
0 1 1 0 Answer: Qn = 1

1 0 0 1
1 1 Ø 0
JK- Flip Flop
• JK Flip-Flop is similar to SR the only
difference here is J = K = 1 is allowed.
• When J = k = 1 , the flip-flop
complements its state.
J K Qn J Pr Q
0 0 Qn-1 JK-FF
0 1 0 Clk
1 0 1 K Clr Q’
1 1 Q’n-1
JK Flip-Flop
J K Qn-1 Qn
0 0 0 0 JK
0 0 1 1 00 01 11 10
Qn-1
0 1 0 0 0 1 1
0 1 1 0
1 1 0 1
1 0 0 1
1 0 1 1
1 1 0 1 Qn =JQ’n-1 + K’Qn-1
1 1 1 0
JK Flip-Flop
Excitaion Table
Qn Qn-1 J K JK FF can used as 2, one inputs Flip-flops

O 0 0 Ø D FF: T FF:
JK always same JK never same
0 1 1 Ø
D Qn-1 Qn T Qn-1 Qn
1 0 Ø 1 0 0 0 0 0 0
0 1 0 0 1 1
1 1 Ø 0 1 0 1 1 0 1
• 1 1 1 1 0
Qn = D Qn = T +Q
• D-FF T-FF

D J T J

K K
Counter Design
• Counter is used to provide accurate timing clocks or
gating signals.
• It is a closed state sequential machine. The number of
states in closed loop gives the Modulas or Division
factor.
Ex: A Mod- 7 counter contains 7 states in closed loop
and divides external clock frequency by a factor 7
• When counter Mod –m and Mod –n are cascaded the
resultant Modulas of the counter is m*n
• The number of Flip-flops needed for Mod- N counter is
Log2N
Counter Design
Procedure:
2. Obtain Sate diagram of the counter
3. Get the Sate Table
4. Identify the Flip flop to be used for design
and get its excitation Table
4. Using the excitation table replace the next state
of the Sate table using the excitation table.
5. Obtain the expression for the inputs of given
Flip-flop and realize them
MOD 4 Gray counter using JK-FF
Step 2
Step 1
State Table
qa qb PS NS
Q1 Q0 Q1n Q0n
(qa)0 0 0 1
(qb)0 1 1 1
qd qc
(qc)1 1 1 0
(qd)1 0 0 0
MOD 4 Gray Counter
PS NS FF1 FF2
Step 3
Q1 Q 0 Q1n Q0n J1 K1 J2 K2
Excitation Table:
(qa)0 0 0 1 0 ø 1 ø
Qn  Qn-1 J K
0 0 0 ø (qb)0 1 1 1 1 ø ø 0

0 1 1 ø (qc)1 1 1 0 ø 0 ø 1

5 0 ø 1 (qd)1 0 0 0 ø 1 0 ø

1 1 ø 0 J1 = Q0 ,K1 = Q’0
J0=Q’1 , K0= Q1
Realization of MOD-4 Gray counter

J0 Q0 J1 Q1

K0 Q’0 K1 Q’1
• Realize Mod- 4 Gray Counter using D-Flip
Flops. ( D1 = Q1n = Q0 , D0 = Q0n = Q’1)
• Realize Mod – 4 Gray Counter using T-
Flip Flops. ( T1= Q1 + Q0 ,T0 = Q1 Q0 )

MOD – 7 counter
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