CPU-IOP Communication

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4/22/12

In most cases the memory unit acts as a message center where each processor leaves information for the other. The sequence of operations may be carried out as shown in the flow-chart. The CPU sends an instruction to test the IOP path. The IOP responds by inserting a status word in memory for the CPU to check. The bits of the status word indicate the condition of the IOP and I/O device, such as IOP overload, condition, device busy with another transfer, or device ready for I/O transfer.
4/22/12 The CPU refers to the status word in memory to

Fig: CPU-IOP Communication.

CPU Operations IOP Operations

Send instruction to test IOP path

Transfer status word to memory location

If status OK, send start I/O instruction to IOP

Access memory for IOP program Conduct I/O transfer using DMA; prepare status report I/O transfer completed; Interrupt CPU Transfer status word to memory location

CPU continues with another program

Request IOP status

Check status word for correct transfer 4/22/12

PRIORITY INTERRUPT
Priority - Determines which interrupt is to be

served first when two or more requests are made simultaneously - Also determines which interrupts are permitted to interrupt the computer while another is being serviced - Higher priority interrupts can make requests while servicing a lower priority interrupt
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Priority Interrupt by Software(Polling) Priority is established by the order of polling the devices (interrupt sources) Flexible since it is established by software Low cost since it needs a very little hardware Very slow Priority Interrupt by Hardware Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request Fast since identification of the highest priority interrupt 4/22/12 request is identified by the hardware

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN VAD 1 Device

PI 1 PO

Priority Interrupt

Processor data bus VAD 2 Device

PI 2 PO

VAD 3 Device
PO

PI 3

To devic next e IN T

Interrupt request Interrupt acknowledge

CPU

* Serial hardware priority function * Interrupt Request Line - Single common line * Interrupt Acknowledge Line - Daisy-Chain

INTACK

The hardware priority function can be established by either a serial or a parallel connection of interrupt lines. The serial connection is also known as daisy chaining method. The CPU responds to an interrupt request by enabling the interrupt acknowledge line. This signal is received by device 1 at its PI(priority in) input. The acknowledge signal passes on to the next device through the PO(priority out) output only if device 1 in not requesting an interrupt. If the device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in the PO output. It then proceeds to insert its own interrupt vector address(VAD) into the data bus for the CPU to use during the interrupt cycle.
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A device with a 0 in its PI input register generates a 0 in its PO output to inform the next-lower priority device that the acknowledge signal has been blocked. A device that is requesting an interrupt and has a 1 in its PI input will interrupt the acknowledge signal by placing a 0 in its PO output. If the device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 in its PO output.
4/22/12 Thus the device with PI=1 and PO=0 is

PARALLEL PRIORITY INTERRUPT

Interrupt register Disk Printer Reader Keyboard 0 1 2 3 I0 I1 Priority I 2 encoder I3 IE N IS T

Priority Interrupt

Bu s y x Bu 0 ffer 0
0 0 0 0

VA to CPU D

0 Mask register 1 2 3

Enable Interrupt to CPU INTAC from CPU K

IEN: Set or Clear by instructions ION or IOF IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated by the Priority Logic Interrupt Register: - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instruction Mask Register: - Mask Register is associated with Interrupt Register 4/22/12 bit can be set or cleared by an Instruction - Each