CHAPTER 1 Introduction to Interfacing Techniques & Data Transfer Schemes

DEFINITION AND COMPONENTS

OF INTERFACE CLASSIFICATION OF DATA TRANSFER SCHEMES:

PROGRAM CONTROLLED TRANSFER INTERRUPT DRIVEN TRANSFER PERIPHERAL CONTROL TRANSFER

Interfacing
Why?

microcomputer revolution will continue into the future many will be required to specify and integrate microprocessors into products or systems in their own disciplines well-designed flexible interfaces will be required to ensure compatibility with other equipments and to extend design options interfaces are the last items to be seriously considered in the race of new technology it deals with the systematic study of microprocessor interfaces and their applications in many diversified fields

In this subject students learn how to interface microprocessors, and hence microcomputers and other related equipments, to external digital or analog devices.

progress has advanced at a pace perhaps unparallel

in scientific history since its introduction in 1971 there have been four generations of microprocessors the number of devices per chip has increased by a factor of 2000, the clock frequency by a factor of 1000 the overall throughput of the microprocessor has increased by hundred or several hundreds of magnitudes

Developing a microprocessor (P)-based system represents one of the most difficult tasks that can confront an engineer. Advances in microprocessor architectures and capabilities are forcing changes in development systems and the ways in which they develop microcode instructions. Also, all P architectures are not created equal when it comes to providing designers with the tools they need for effective systems resource management.

Therefore, a well designed flexible interfaces will be required to ensure compatibility and extend design options.

Definitions:
Microprocessor - The central unit of a microcomputer that

contains logical elements for manipulating data and performing arithmetic or logical operations. A single chip may contain RAM, ROM, and PROM memories, clocks, and interfaces for memory and I/O device. Microprogramming- A method for controlling the operation of the CPU in which each complete instruction starts the execution of a sequence of instructions, called microinstructions, which are at a more elementary level. Multiprocessor- As defined by ANSI, it is a computer employing two or more processing units under integrated control. Although this definition may be correct, it is not complete enough to be too helpful. There are other important features that include both hardware and software. A multiprocessor will be defined as a system with: a) two , or more processing units, b)shared memory, and c) shared I/0.

Interface Definitions
Interface a shared boundary between system elements defined by common physical interconnection characteristics, signal characteristics, and meanings of interchanged signals. is a tool and concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software. allows a component to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol.

Cont

Interface Device

A device that meets the interface specifications on one side of an interface. The term is usually applied to a device through which a system or equipment works to meet interface specifications.

 Interface Specification

a set of technical requirements that must be met at an interface.

Direct Memory Access

A technique that permits a peripheral device to enter or extract blocks of data from the memory without involving the central processing unit. In some cases, the CPU can perform other functions while the data transfers occur.

Components of Interface
Interfacing Standards & Converters

Interfacing Device
(ID 1)

Interface Signals

Interface Signals

Interfacing Device
(ID 2)

The interfacing devices should make use of standard data transfer schemes for the efficient exchange of data.

Data Transfer Schemes

refers to the method of data transfer between the

processor and peripheral devices: microprocessor and memory microprocessor and I/O devices memory and I/O devices
For effective data transfer between these devices, the timing parameters of the devices should be matched. But most of the incompatible timings. devices have

Two Categories:

1. Programmed data transfer. 2. Direct memory access data transfer.

Programmed Data Transfer

a memory resident routine

(subroutine) requests the device for data transfer to or from one of the processor register scheme is used when a relatively small amount data are to be transferred usually one byte or word of data is transferred at a time

Examples of devices using parallel data transfer are ADC,DAC, Hex-keyboard, 7segment LED's, etc.

3 Types of Programmed Data Transfer

The scheme can be further classified into the following: 1. Synchronous data transfer scheme. 2. Asynchronous data transfer scheme. 3. Interrupt driven data transfer scheme.

Direct Memory Access (DMA) Data Transfer

the processor is forced to hold

state by an I/O device until the data transfer between the device and the memory is completed the processor does not execute any instructions during the hold period is used for large block of data transfer between I/O device and memory

Typical examples of devices using DMA are CRT controller, floppy disk, hard disk, high speed line printer, etc

3 Types of DMA Data Transfer

The schemes are: 1. Cycle stealing DMA. 2. Block or Burst mode DMA. 3. Demand transfer mode DMA.

Types of Data Transfer Schemes

PROGRAM CONTROLLED TRANSFER

the transfer of data is completely under the control of

the microprocessor program

an i/o operation takes place only when an i/o instruction is encountered in the execution of the program

data transfers can take place synchronously or

asynchronously
asynchronous transfers mean transfers taking place at irregular intervals synchronous transfers mean transfers occurring at the same time

Data transfers between the microprocessor and the peripherals are primarily asynchronous

Program controlled data transfers can take place under several conditions
Unconditional
assumes that a peripheral is always available

Polling
kept in a loop to check whether data are available

Interrupt

interrupted from its normal execution of program by an I/O device, when the latter is ready

With ready signal With handshake signals

when peripheral response time is slower than the microprocessor execution time, READY signal is used

handshake signals are signals exchanged prior to data transfer

Synchronous data transfer scheme

is the simplest of all data

transfer schemes
the processor does not

check the readiness of the device

I/O device or peripheral

should have matched timing parameters

the mode-O input or output in 8155 or 8255 is an example of synchronous data transfer

Asynchronous Data Transfer Schemes

is employed when the speed

of processor and I/O device does not match the processor ends a request to the device for read/write operation

then the processor keeps on polling the status of the device once the device is ready, the processor executes a data transfer instruction to complete the process to implement this scheme, the device should provide a signal which may be tested by the processor to ascertain whether it is ready or not

handshake data transfer without interrupt (mode-l and mode-2) of8155 or 8255 is an example

Interrupt Driven Data Transfer Scheme

is the best method of data f

transfer for effectively utilizing the processor time

the processor first initiates the I/O device for data transfer. After initiating the device, the processor will continue the execution of instructions in the program. Also at the end of an instruction the processor will check for a valid interrupt signal. If there is no interrupt then the processor will continue the execution. When the IO device is ready, it will interrupt the processor. On receiving an interrupt signal, the processor will complete the current instruction execution and saves the processor status in stack. Then the processor call an interrupt service routine (ISR) to service the interrupted device.

when the processor call an interrupt service routine (ISR) to service the interrupted device. At the end of ISR the processor status is retrieved from stack and the processor starts executing its main program.

PROGRAM CONTROLLED DMA TRANSFERS

In programmed data transfer, a memory resident routine requests the device for data transfer to and from one of the microprocessor registers

In DMA transfer, the microprocessor is forced to hold on by an I/O device until the data transfer is complete
Programmed data are used when relatively small amounts of data are transferred using relatively slow I/O devices such AID, D/A converters, and peripheral floating point arithmetic unit.

DMA is preferred when a large block of data is to be transferred. This scheme is generally employed for transferring data between the microprocessor and peripheral mass storage devices like hard disk or a highspeed line printer.

Interrupt
An interrupt is a condition that causes the

microprocessor to temporarily work on a different task, and then later return to its previous task. Interrupts can be internal or external. Internal interrupts, or "software interrupts," are triggered by a software instruction and operate similarly to a jump or branch instruction. An external interrupt, or a "hardware interrupt," is caused by an external hardware module.

As an example, many computer systems use interrupt driven I/O, a process where pressing a key on the keyboard or clicking a button on the mouse triggers an interrupt. The processor stops what it is doing, it reads the input from the keyboard or mouse, and then it returns to the current program.

The image below shows conceptually how an interrupt happens:

The grey bars represent the control flow. The top line is the program that is currently running, and the bottom bar is the interrupt service routine (ISR). Notice that when the interrupt (Int) occurs, the program stops executing and the microcontroller begins to execute the ISR. Once the ISR is complete, the microcontroller returns to processing the program where it left off.

INTERRUPT PROCESS IN MICROCOMPUTERS

8085 FIVE pins on the chip for implementing the interrupt process PIN NO 6 7 8 9 10 Name TRAP RST 7.5 RST 6.5 RST 5.5 INTR.

On these five lines, 8085 can receive signals from the peripheral devices, requesting the microprocessor to attend to data transfers from them or send data to them. These are called HARDWARE INTERRUPTS. Pin No 11 on the chip is an active low signal, sent by the microprocessor, to acknowledge the receipt of the interrupt signal. In addition 8085 has an internal flip-flop called INTERRUPT ENABLE flip flop, This should be set, in order for the ~p to be interrupted. 8085 has the following instructions the set or reset this flip -flop.

8085 has the following instructions the set or reset this flip flop:

EI : (Enable Interrupt):

This is a one byte instruction

-This sets the IE flip -flop and enables the interrupt process. -System reset or an interrupt disables the interrupt process

 DI : (Disable Interrupt):

This is also one byte instruction.

-This resets the IE flip -flop and disables the interrupt process. -It should be included in a program segment where an interrupt from an external source can nut be tolerated.

 These Interrupts are called VECTORED

INTERRUPTS. What it means is that each of the interrupts except INTR is associated with a branch address on page OOH in ROM.
an interrupt vector is the memory address of

an interrupt handler, or an index into an array called an interrupt vector table or dispatch table containing the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt vector.

 On occurrence of an interrupt, the processor's control

is automatically transferred to the respective location.

This is achieved by internal hardware. This way of

automatically transferring control in response to an interrupt is called VECTORING.

In case of INTR, the lNTA signal issued in response to

the signal on INTR lines is used to insert a RST instruction lone byte CALL) on the data bus. The branch addresses is determined by the RST instruction.

I/O devices can interrupt the ~p on any of the 5 pins. The nature of the interrupt signals, their characteristics and their branch addresses are as follows:

Name of the Interrupt TRAP RST 7.5 RST 6.5 RST 5.5 INTR

Triggering Level and Edge Edge Level Level Level

Branch Priority Location (ISR) 0024H 1 003CH 2 0034H 3 002CH 4 Enable/Disable under Program

A technique of suppressing certain interrupts and allowing the control program to handle these masked interrupts at a later time.

SIM : Set Interrupt Mask. This is a 1 -byte instruction, used to mask or unmask the interrupts RST 7.5, 6.5 & 5.5. To use this instruction, the accumulator is to be loaded with a data byte whose bits have the purposes shown in figure below: D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R 7.5 MSE M 7.5 M 6.5 M 5.5

Interpretation of Accumulator bits for SIM

 D7 (SOD): Serial output Data -If D6 == 0, D7 is

ignored D6 (SDE): Serial Data enable -If 1, D7 is output serially. M7.5, 6.5, 5.5, Mask -set: 0: available 1: masked. MSE Mask set enable: IfO, bits Do, Dl, D2 are ignored; R 7.5 : RESET RST 7.5 If 1, RST 7.5 is reset.

 RIM : (READ INTERRUPT MASK)

This is also 1 -byte instruction; this instruction is used to identify finding interrupts, when multiple devices interrupt the processor. When this instruction is written in a program and is executed by the microprocessor, the accumulator is loaded with a byte, whose bits indicate the information shown in figure below.