Combinational Circuits

Combinational Components

A combinational circuit is a logic circuit whose outputs at any time are determined directly and only from the present input combination. It performs a specific information-processing operation fully specified logically by a set of Boolean functions

Combinational Circuits

Block diagram of a combinational circuit

Designing Combinational Circuits

In general we have to do following steps: 1. Problem description 2. Input/output of the circuit 3. Define truth table 4. Simplification for each output 5. Draw the circuit

Sample Circuit

Logic Diagram for Circuit Analysis

Half-Adder (HA)

Most basic arithmetic operation is the addition of 2 bits. A combinational circuit that performs addition of 2 bits.

Half-Adder

Implementation of Half Adder

Full-Adder

A combinational circuit that performs the addition of 3 bits is called a full adder (FA), which can be implemented by 2 half-adders and an Or gate.

Full-Adder

Derivation of Carry
C xy xz yz C xy z(x y) C xy z(x x y) C xy xz x yz C x(y z) x yz C x(y y z) x yz C xy x y z x yz C xy z(x y x y) C xy z(x y) xy z(x y)

Binary Parallel Adder

For example to add A= 1011 and B= 0011 subscript i: 3 2 1 0 Input carry: 0 1 1 0 Ci Augend: 1 0 1 1 Ai Addend: 0 0 1 1 Bi -------------------------------Sum: 1 1 1 0 Si Output carry: 0 0 1 1 Ci+1

Binary Parallel Adder

Binary adder that produces the arithmetic sum of binary numbers can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain

Binary Parallel Adder

Note that the input carry C0 in the least significant position must be 0.

Binary Subtractor

The subtraction A B can be done by:

Designing a Half subtractors, and Full-subtractors; or Taking the 2s complement of B and adding it to A because A- B = A + (-B)

Design of Half and Full subtractors

Binary Subtractor (2s complement)

The subtraction A B can be done by taking the 2s complement of B and adding it to A because A- B = A + (-B)

It means if we use the inventers to make 1s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.

4 bit - 2s complement Subtractor

=1

Adder/Subtractor Circuit
Can be combined into one circuit with one common binary adder. Mode M controls the operation. When M=0 the circuit is an adder when M=1 the circuit is subtractor. It can be done by using exclusiveOR for each Bi and M. Note: 1 x = x (subtract) and 0 x = x (add)

Note: S input is the M mode controller

Magnitude Comparator

It is a combinational circuit that compares two numbers and determines their relative magnitude The output of comparator is usually 3 binary variables indicating: A>B A=B A<B For example to design a comparator for 2 bit binary numbers A (A1A0) and B (B1B0) we do the following steps:

Comparators

For a 2-bit comparator we have four inputs A1A0 and B1B0 and three outputs E =1 if two numbers are equal, G = 1 when A > B, and L = 1 when A < B). If we use truth table and KMAP the result is:

E=(( A0 B0) + ( A1 B1)) G = A1B1 + A0B1B0 + A1A0B0 L= A1B1 + A1A0B0 + A0B1B0

A0

E
A1 B0 B1 Comparator G L

Magnitude Comparator (A=B)

Here we use simpler method to find E (called X) and G (called Y) and L (called Z) A = B, if all Ai= Bi Ai Bi Xi X1 X0 -----------0 0 1 A= A1 A0 0 1 0 B= B1 B0 1 0 0 1 1 1 It means X0 = A0B0 + A0B0 and X1= A1B1 + A1B1 If X0 = 1 and X1 = 1 then A0 = B0 and A1=B1

Thus, if A = B then X0X1 = 1 it means X= (A0B0 + A0B0)(A1B1 + A1B1) Since (x y) = (xy +xy) Then, X= ( A0 B0) ( A1 B1) = (( A0 B0) + ( A1 B1))

Magnitude Comparator (A > B)

A > B if

Ai Bi Xi -----------0 0 0 0 1 0 1 0 1 1 1 0

Ai>Bi or A1 = B1 and A0 >B0 Therefore: For A> B: A1 > B1 or A1=B1 and A0 > B0

Means: Y= A1B1 + X1A0B0 should be 1

Magnitude Comparator (A < B)

For A<B:

A1 < B1 or A1=B1 and A0 < B0

z = A1B1 + X1A0B0

The procedure for binary numbers with more than 2 bits can also be found in the similar way. For example next slide shows the 4-bit magnitude comparator, in which

4-bit Magnitude Comparator

Sample Problem #1

Design a combinatorial circuit that converts the 4-bit BCD code to Excess-3 code.
Input BCD A B C D
0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1

Output Excess-3 w x y z
0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0

Note: The other input combinations have dont care states.

Z 1 0 1 0 1 0 1 0 1 0

CD 00 01 AB 00 1 01 11 10

11

10

1 1 1 X X X X 1 X X
z = D

CD 00 01 AB 00 1 01 11 10

11

10

1 1 1 X X X X 1 X X

y = CD + CD
W CD 00 01 11 10 0 0 AB 00 0 0 1 1 1 01 0 11 X X X X 1 1 1 X x 10 1 1 1 w = A + BC + BD 1

X CD 00 01 11 10 0 AB 1 1 1 1 00 1 1 01 1 1 X X X X 11 0 0 1 X X 10 0 x = BC + BD + BCD 0 1

Y 1 0 0 1 1 0 0 1 1 0

Draw the circuit

Sample Problem #2

A combinational circuit has four inputs and one output. The output is equal to 1 when (a) all the inputs are equal to 1 or (b) none of the inputs are equal to 1 or (c) an odd number of inputs are equal to 1.

Obtain the truth table Find the simplified output function Draw the logic diagram

Sample Problem #3

Design a combinational circuit whose output is HIGH only when a majority of inputs A, B, and C are LOW.

Seven segment decoder

Generates the outputs for selection of segments in a display indicator used for displaying the decimal digit Has seven inputs as shown.

BCD-to-7 segment decoder

Combinational circuit that accepts a decimal digit in BCD and generates the appropriate outputs for selection of segments in a display indicator used for displaying the decimal digit. The numeric designation chosen to represent the decimal digit is shown. Design the BCDto-seven segment decoder circuit.

7-segment decoder
w 0 0 0 0 0 0 0 0 1 1 x 0 0 0 0 1 1 1 1 0 0 y 0 0 1 1 0 0 1 1 0 0 z 0 1 0 1 0 1 0 1 0 1 a 0 0 1 1 0 1 0 1 1 1 b 0 1 1 1 1 0 0 1 1 1 c 0 1 0 1 1 1 1 1 1 1 d 0 0 1 1 0 1 1 0 1 0 e 0 0 1 0 0 0 1 0 1 0 f 0 0 0 0 1 1 1 0 1 1 g Number 0 0 1 1 1 1 1 0 1 1
a

f
e g d

b
c

Exercises
1.

Design a combinational circuit that accepts a three-bit number and generates a binary number output equal to the square of the input number. Design a combinational circuit whose input is a three-bit number and whose output is the 2s complement of the input number.

2.

Combinational Logic with MSI and LSI

Decoder

A combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. Can be implemented with And gates. For example if the number of input is n = 3 the number of output lines can be m = 23 . It is also known as 1 of 8 because one output line is selected out of 8 available lines:

Z Y X enable 3 to 8 decoder

D0 D1 D2 D3 D4 D5 D6 D7

Decoder

With 4 input lines, there are 24 =16 outputs. With 5 input lines, there are 25 =32 outputs. With 9 input lines, there are 29 =512 outputs. With 10 input lines, there are 210 =1024 outputs.

X0 : : : X8 enable

: : :

9 to 512 decoder

: : : :

D0 : : : : D511

3 to 8 Line decoder (Truth Table)

X Y Z D7 D6 D5 D4 D3 D2 D1 D0 ------------------------------------------------------0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

Decoder with Enable Line

Decoders usually have an enable line, If enable=0 , decoder is off. It means all output lines are zero If enable=1, decoder is on and depending on input, the corresponding output line is 1, all other lines are 0

Truth table for 3 x 8 decoder w/ Enable

E X Y Z D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------0 x x x 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 1 . 1 ..... 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0

Major application of Decoder

Decoder is used to implement any combinational circuits ( fn ) For example the truth table for full adder is S(x,y,z) = (1,2,4,7) and C(x,y,z)= (3,5,6,7). The implementation with decoder is:

Sample Problem #1
1. A combinational circuit is defined by the ff. two functions: F1(x,y) = (0,3) F2(x,y) = (1,2,3) Implement the combinational circuit by means of the decoder.

Sample Problem #2
2. A combinational circuit is defined by the ff. three functions: F1 = xy + xyz F2 = x + y F3 = xy + xy Design the circuit with a decoder and external gates.

Encoder

Encoder is a digital circuit that performs the reverse operation of a decoder Generates a unique binary code from several input lines. Generally encoders produce 2-bit, 3-bit or 4-bit code. n bit encoder has 2n input lines

2 bit encoder

2-bit Encoder (Truth Table)

D3 D2 D1 D0 X Y ---------------------------------0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1

X = D2 + D3 Y = D1 + D3

2-bit Encoder Circuit

2-bit Encoder

If one of the four input lines is active encoder produces the binary code corresponding to that line If more than one of the input lines will be activated or all the output is undefined. We can consider dont care for these situations but in general we can solve this problem by using priority encoder.

Multiplexer

A combinational circuit that selects binary information from one of the input lines and directs it to a single output line. Also called Selector. (MUX) There are 2n input lines and n selection lines whose bit combinations determine which input line is selected For example: 2-to-1 MUX. If selection S =0 then I0 has the path to output and if S =1 then I1 has the path to output.

2-to-1 multiplexer

4x1 MUX

Boolean function Implementation

Another method for implementing Boolean function is by using MUX. For doing that assume Boolean function has n variables. We have to use multiplexer with n-1 selection lines and 1- first n-1 variables of function is used for data input 2- the remaining single variable ( named z )is used for data input. Each data input can be z, z, 1 or 0. From truth table we have to find the relation of F and z to be able to design input lines. For example : f(x,y,z) = (1,2,6,7)

MUX Problem #1

Given the ff. Boolean function F, construct a combinational circuit that uses MUX. F(A,B,C) = (1,3,5,6)
A B C F -------------------0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 F=C F=C F=C F = C

MUX Problem #2
F (A,B,C,D) = (1,3,4,11,12,13,14,15)

Usage:MULTIPLEXER

Helps share a single communication line among a number of devices. At anytime, only one source and one destination can use the communication line.

LARGE MULTIPLEXER

Large multiplexer can be built from smaller multiplexer 8:1 multiplexer can be built from smaller multiplexer like this:

LARGE MULTIPLEXER

Other example the building of 8:1 multiplexer from smaller multiplexer

Demultiplexers

A decoder with an enable (E) input is also called a demultiplexer (DMUX or DEMUX). A circuit that receives information on a single line and transmits this to one of the 2n possible output lines. The selection of the output line is controlled by the bit values of n selection lines.

2 to 4 Decoder with Enable (E)

Comparison

Decoder with Enable

Demultiplexer

Decoder/deMUX

Circuits can be connected together to form a larger decoder circuit. Example: Construct a 4 x 16 decoder out of 3 x 8 decoders with enable inputs. Inputs : 3 + 1 (add one 3 x 8 decoder) Outputs: 8 x 2 ( 2 decoders needed) = 16

4 x 16 Decoder
When E = 0, the top decoder is enabled and the other is disabled. When E = 1, the bottom decoder is enabled and the other is disabled.

Decoder Construction Problem

Construct a 5 x 32 decoder with four 3 x 8 decoder/deMUX and a 2 x 4 decoder.

Thri-State Gates

Thri-state gates exhibit three states instead of two states. The three states are: High : 1 Low : 0 High impedance n High impedance that state the output is disconnected which is equal to open circuit. In other words the circuit has no logic significance. We can have AND or NAND tree-state gates but the most common is thri-state buffer gate

Thri-State Gates

We may use conventional gates such as AND or NAND as tri-state gates but the most common is thri-state buffer gate. Note that buffer produces transfer function and can be used for power amplification. Thri state buffer has extra input control line entering the bottom of the gate symbol (see next slide)

Three-state buffer
C A Y ---------------------0 0 z 0 1 z 1 0 0 1 1 1

Three-state buffers can be used to implement multiplexer