Memory Management

C R Sarma
Associate Professor, Dept of ECE
G.Narayanamma Institute of Technology and Science

10/15/98 1
MEMORY MANAGEMENT
– Memory Management earlier responsibility
of the Operating System
– Microprocessors now support part of these
functions
– efficient usage main memory
– Protecting processes address space
– logical or virtual address space address
– Hides low level details

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Two types of Address Space
1 Physical store (space): the hardware memory on
the machine
2 Virtual (or logical) address space: the
memory perceived by a process. Each process has its
own virtual space.

Logical space Address Physical space

mapping

• Three possiblities to map logical

references to physical references:
1 Direct: logical to physical at compile-time.
2 Static Relocation: physical addresses computed at
load-time.
3 Dynamic Relocation: physical addresses computed3
Purposes
1 independent eventual memory
location.
2 Inactive processes removed
3 Use available memory fully.
4 Simulate larger or smaller address
space.
5 Protect from unwanted foreign access.
6 Restricted sharing among concurrent
processes.
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Storage Hierarchy
CPU ----------------------------------------->
| | | |
| | | |
Instruction Main Disk Ethernet
Cache Memory Controller Controller
| |
Disks |____...
to File
servers
Most frequently accessed data - lower (closest to
CPU) levels
Less frequently accessed data - less expensive
(but bigger) devices.
Higher levels needed brought into lower levels.
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Storage Hierarchy (cont.)
• Typical system:
– Instruction cache
– Main memory
– Disk
– File servers
– Virtual memory an example of Storage
hierarchies:
– Price/performance increased by:
– levels of storage- Few high-speed
registers
- large inexpensive Slow devices 6
Memory Management
Strategies
1 Fetch Strategy:
E.g., demand fetching, anticipated
fetching (pre-fetching).
2 Placement (or allocation) Strategy:
Information to be placed.
E.g., Best-Fit, First-Fit, Buddy-
System.
3 Replacement Strategy:
Avoid contention E.g., LRU, FIFO.
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Memory Management
Evolution
• Variations
1 Fixed Partitions
2 Variable Partitions
3 Segmentation
4 Paging

• Criteria
1 How efficiently can it be implemented?
2 How effectively can the physical memory
be utilized?

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Fixed Partitions-1
1 Divide all physical memory into a fixed set
of contiguous partitions.
E.g., early IBM 360 models.
+---------+
| monitor |Queue for waiting processes
+---------+
| 2K | ....
+---------+
| 6K | ....
+---------+
| 12K | ....
+---------+

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Fixed Partitions-2
2 Place only one process at a time
3 Bind physical to virtual address during
loading, not during execution.
4 Partition boundaries limit the length of
virtual memory for each process.
5 A process entirely in main memory or
entirely on backing store (i.e., swapped in
or swapped out).

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 Fixed Partitions-3

6 A process many only swapped into the

same partition from which it was
swapped out.
7 It can only simulate smaller, not larger,
virtual space than physical space.
8 No sharing between processes.
9 Memory space wasted:
• Internal fragmentation: memory which is
internal to a partition, but not used.
• External fragmentation: a partition is unused
and available, but too small for any waiting
job. 11
Variable Partitions

• Allocation Strategy in Non-paged

System:
1 First-Fit
2 Best-Fit
3 Worst-Fit

• Two operations:
• RequestMemory (size, baseAddr)
• ReleaseMemory (size, baseAddr) 12
Allocation strategies
Let {Hi | i = 1,…,n} be a set of unused
holds and k be the size of a
requested block.
• First-Fit :Select the first Hi such that
size (Hi) ≥ k.

• Best-Fit: Select Hi such that size (Hi) ≥ k

• Worst-Fit: Select Hi such that size (Hi) ≥
k-
-produces the largest left-over block
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Properties
Both could leave many small and useless holes.
Best-Fit performs better:
Memory Req F-F B-F
20K,15K 20K,15K
12K 8K,15K 20K, 3K
16K blocked 4K, 3K
First-Fit performs better:
Memory Req F-F B-F
20K,15K 20K,15K
12K 8K,15K 20K, 3K
14K 8K, 1K 6K, 3K
7K 1K, 1K blocked

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Segmentations

Virtual Space = segments - each is a contiguous

region
Intel 80x86 family has separate register
CS reg for segment IP reg offset each 16
bits in size
• logical address: in general
+----------+----------+
| seg # | offset |
+----------+----------+
• 80x86 family only cs:ipregisters
68000- 24-bit address 15
Segmentation - Microprocessor support
D L16-L19
BASE(B24-B31) G 0 AVL

ACCESS RIGHTS BASE(B23-B16)

BASE(B15-B8) BASE(B7-B0)

LIMIT(L15-L8) LIMIT(L7-L0)

Selector 13 bits TL 1 bit RPL 2

bits

16
Segmentation - Microprocessor
support

Selector Offset

Memory
+ operand

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Paging
Paging solves placement problem -uses equal
size blocks of physical memory - page frames
Page fault i- referencing a page - not loaded -
page frame.
Replacement strategies needed- some pages
must be swapped out
Goal: minimize the number of page faults.
Demand paging: bring in a page when it is
needed (detected by a page fault).
Prefetching: bring in a set of pages before
starting or restarting after a long I/O or
scheduling block.
Clustering: bring in several pages at a time
(demand paging).
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Paging Hardware

• One-level Paging: PDP-11

• Two-level Paging: VAX
• Three-level Paging: SPARC
• Four-level Paging: 68030
• Inverted Page Tables

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Page Fault Handling

1. Hardware traps and saves PC.

2. Trap handler saves registers.
3. OS discovers a page fault.
4. OS looks a free page frame. If none, find a
victim and swap it out.
5. Start I/O for the missing page.
6. When the disk interrupt handler notifies its
arrival, the faulting process is scheduled (i.e., it is
moved from wait queue to ready queue).

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