Digital Systems and VLSI Design

Sayandeep Nag
sayandeep.nag@gmail.com Lecture 5

Session 1

Review of Digital Logic Circuits Design Combinational circuits - Design steps Arithmetic Circuits - Full adder, Serial Adder, Adder/Subtractor, Ripple Carry Chain, Carry Look-Ahead adder, Carry Select Adder, ALU, Parity Generator, Comparator, Multiplier. Generalization of these Principles.

Course Organization
Session 7
Circuit characterization Resistance estimation Capacitance estimation Switching characteristics

Session 2
PLA, PAL, PLD, CPLD, ROM, FPGA introduction Sequential circuits - Design steps Flip-flops, registers, counters

Session 8
CMOS gate transistor sizing Power dissipation Scaling principles

Session 3

Finite State Machines , Mealy and Moore machines Introduction to FSMs,

Session 9
CMOS circuit and layout design

Session 4
FSM capabilities minimization and transformation of sequential machines. Synchronous and asynchronous FSMs State assignment of synchronous sequential machines Structure of sequential machines Verification and testing of sequential circuits

Session 10
Basic physical design of simple gates CMOS logic gate design CMOS logic structures Clocking strategies

Session 5
Review of logic families Different logic families and their comparison Logic levels & Noise margin features Fan-in, Fan-out, Active load, Sinking & Sourcing currents Propagation delay MOS technology and VLSI

Session 11
Memory, registers & System timing aspects 3 transistor memory cell nMOS pseudo static memory cell, Two 4-bit words of RAM array

Session 6
MOS transistor theory Introduction MOS device design equations CMOS inverter DC characteristics Static load MOS inverters Pass transistor, Transmission gate, tristate inverter

Session 12
Practical realities and ground rules Performance, Floor plan & Layout I/O pad layout System delays

Course Organization

Textbook: Principles of CMOS VLSI Design By Neil H. E. Weste, Kamran Eshraghian

Please Be Regular to the Class its Important!!!

Logic Signals and Gates

Digital logic values : 0 & 1 Called binary digit or bit Mapping the infinite set of real analog values for a physical quantity into the finite abstract logic values 0 & 1 Electronic logic circuits (CMOS, TTL) LOW : 0 & HIGH : 1 positive logic LOW : 1 & HIGH : 0 negative logic

Logic Signals and Gates

Logic Circuits and Truth Tables

Combinational circuits

An output only depends on the present input An output depends on the present state (memory) and input

Sequential circuits

Basic Logic Gates (Functions)

Real Logic Circuits Timing Behavior

lag (delay)

Logic Families History

First logic circuits based on relays Developed at Bell Lab. in 1930s ENIAC (1940s) First electronic digital computer 18,000 vacuum tubes, 140,000W, 100 X 10 X 3 ft Late 1950 Semiconductor diode and bipolar junction transistor IC : 1960s :TTL (transistor-transistor logic) & MOS CMOS (Complementary Metal-Oxide Semiconductor) MOSs principles : patented ten years before the bipolar junction tr. Mid-1980s, high speed & lower power consumption Vast majority of the worldwide IC market (microprocessor & memory)

CMOS Logic

CMOS logic levels driven by 5.0 volt power supply

During signal transition Interpreted as either 0 or 1

MOS Transistors

MOS transistors The basic building blocks in CMOS logic circuits NMOS (n-channel MOS) & PMOS (p-channel)

Voltage-controlled resistance (~10 Ohm & 1 Mega Ohm ~)

[ NMOS]

[ PMOS]

leakage current : gate source : A

Basic CMOS Inverter Circuit

[ functional behavior]

[ logic symbol] [ circuit diagram]

Basic CMOS Inverter Circuit

[ switch model for CMOS inverter]

[ CMOS inverter logical operation]

CMOS NAND Gates

CMOS NAND Gates (Switch Model)

3-Input CMOS NAND Gates

CMOS NOR Gates

n-channel ON resistance < p-channel ON resistance If consider k-input gates, series of n in NAND < series of p in NOR NAND is faster than NOR

Fan-In

Fan-in The number of inputs that a gate can have in a particular logic family The series transistors limits the fan-in of CMOS gates (switching delay) Typically to 4 for NOR gates and 6 for NAND gates For large number of gates, cascade gates with fewer inputs

The total delay is typically less than the delay of a one-level 8-input NAND gates

Non-Inverting Gates

It is typically not possible to design a noninverting gate with a smaller number of transistors than an inverting one

[Inverter-to-inverter]

AND Gates

[NAND]

[Inverter]

CMOS AND-OR-INVERT (AOI) Gates

A B C D
L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
off off off off off off off off on on on on on on on on on on on on on on on on off off off off off off off off off off off off on on on on off off off off on on on on on on on on off off off off on on on on off off off off off off on on off off on on off off on on off off on on on on off off on on off off on on off off on on off off off on off on off on off on off on off on off on off on on off on off on off on off on off on off on off on off

Z
H H H L H H H L H H H L L L L L

Two level logic (AND OR), one level of delay

Electrical Behavior of CMOS Circuits

Electrical aspects of CMOS circuit operation Logic voltage levels, DC noise margin, fanout, speed, power consumption, noise, electronic discharge, open-drain outputs, three-state outputs Data sheet Specifying the devices logical and electrical characteristics Different manufactures typically specify additional parameters Varying in how they specify the parameters Usually showing the test circuits and waveforms

Data Sheet

Electrical Behavior of CMOS Circuits

Steady-behavior Inputs and outputs are not changing Logic levels and noise margin Circuit behavior with resistive loads Circuit behavior with non-ideal inputs Fanout Effects of loading Unused inputs and else Dynamic-behavior : speed and power consumption Transition time Propagation delay Power consumption

Logic Levels and Noise Margins

It varies under different conditions of powersupply voltage, temperature, and output loading

VIN : 2.4 V ~ 2.6 V VOUT : 1.5 V ~ 3.5 V

[Typical I/O transfer characteristic of a CMOS inverter]

Logic Levels and Noise Margins

VOHmin : The minimum output voltage in the HIGH state VOLmax : The maximum output voltage in the LOW state VIHmin : The minimum input voltage guaranteed to be recognized as a HIGH VILmax : The minimum input voltage guaranteed to be recognized as a LOW DC noise margin A measure of how much noise it takes to corrupt a worst-case voltage into a value that may not be recognized properly by an input

Logic Levels and Noise Margins

[Logic levels and noise margins for the HC-series CMOS family]

VOHmin = (VCC -10%) - 0.1V VOLmax = ground + 0.1V DC noise margin in HC-series = 1.35-0.1 = 1.25 V IIH, IIL = 1 A very little power in CMOS input

Logic Levels and Noise Margins

Resistive Loads (DC Load)

Connected to a CMOS output Requiring nontrivial amounts of current Some examples of resistive loads Transmission-line termination One or more TTL or other non-CMOS inputs Current-consuming devices such as LED (light-emitting diode) When the output of a CMOS circuit is connected to a resistive load, the output behavior is not ideal

Circuit Behavior with Resistive Loads

Rn, Rp on state : about 100 (n-channel), 200 (p-channel) off state : about above 1 M

Circuit Behavior with Resistive Loads

Vout =

100 100 + 667

X 3.33V = 0.43V

Circuit Behavior with Resistive Loads

Vout =

3.33V + (5 3.33) = 4.61 V

667 200 + 667

Circuit Behavior with Resistive Loads

IC manufactures usually dont specify the resistance of the on transistors Instead, IOLmax and IOHmax

Circuit Behavior with Resistive Loads

on resistance from table 3-4 with a worst-case resistive load Rp (ON) = ( VDD VOH minT ) / IOH maxT = 165

Rn (ON) = VOL maxT / IOL maxT = 82.5

Circuit Behavior with Nonideal Inputs

If the input voltage is not close to the power-supply rail on transistor may not be fully on on resistance may increase off transistor may not be fully off off resistance may decrease

Circuit Behavior with Nonideal Inputs

The slight degradation of output voltage is generally tolerable Whats worse is that the output structure is now consuming a nontrivial amount of power Pwasted = 5.0V Iwasted = 8.62 mW (for VIN = 1.5V) More serious in TTL loads rather than CMOS loads

Circuit Behavior with Nonideal Inputs

The output voltage of a CMOS inverter deteriorates further with a resistive load

Fanout

The fanout of a logic gate The number of inputs that the gate can drive without exceeding its worst-case loading specifications (Table 3-4) IOLmaxC (Table 3-4) 20 A for a HC-series CMOS gate driving CMOS inputs IImax 1 A : The maximum input current for a HC-series CMOS input Low-state fanout = 20

Fanout

IOHmaxC - 20 A for a HC-series CMOS gate driving CMOS inputs IImax 1 A : The maximum input current for a HC-series CMOS input HIGH-state fanout = 20 Overall fanout of a gate The minimum of its High-state and Low-state fanouts DC fanout

Etc.

Effects of loading beyond the fanout LOW/HIGH state level changes Propagation delay, output rise & fall time may increase beyond spec. Operating temperature may increase

Etc.

Unused Inputs In high-speed circuit design, its usually better to use (b), (c) rather than (a) since (a) increase the capacity load on the driving signal Unused CMOS inputs should never be left unconnected Floating input 0 V (logic 0)

Transition Time

The amount of time that the output of a logic circuit takes to change from one state to another

tr = rise time tf = fall time (a) Ideal case (tr = tf = 0) (b) A more realistic approx. (c) Actual timing

Logic levels of inputs

Transition Time

The transition times of a CMOS output depend mainly on on transistor resistance & the load capacitance (stray capacitance) A large capacitance increases transition times Sources of stray capacitance (capacitive load or AC load) Output circuits A gates output transistors, internal wiring, and packaging 2~10 pF The wiring that connects an output to other inputs About 1 pF per inch or more Input circuits Transistors, internal wiring, and packaging 2~15 pF per input

Transition Time
Stray capacitance ) output circuit : 2~10 pF ) wiring : 1pF / inch ) Input circuit : 2 ~ 15 pF/inch

DC load : RL & VL AC load : CL (transition time : slow )

When a CMOS output drives only CMOS inputs DC load is negligible RL = & VL = 0

Fall Time (tf) Calculation

Vcc = 5V

Vin

Vout

- Rp (On resistance)=200 , Rn (On resistance)=100 , CL = 100pF

a) Fall time (tf) : Vin high

t < 0 , Vout = 5.0 V t > 0 , Vout = VDD e -t/(Rn CL) -12 = 5.0 X e -t/(100X100X10 )
= 5.0 X e for Vout = 3.5 , t = 3.57 nsec Vout = 1.5 , t = 12.04 nsec tf = t1.5 t3.5 = 8.5 nsec
-t/(10X10-19)

3.5V 1.5V

Rise Time (tr) Calculation

b) Rise time (tr) : Vin low

Vout = VDD (1 e -t/(Rp CL)) = 5.0 (1 e -t/(20X10-12) )

for Vout = 3.5 V , t = 24.08 nsec Vout = 1.5 V , t = 7.13 nsec tr = t3.5 t1.5 = 17 nsec

- tr > tf (twice)
If R & C smaller, transition times improve

Propagation Delay tp

The amount of time that it takes for a change in the input signal to produce a change in the output signal

Vcc = 5V
Vin Vout

tPW(min) tPHL

mid point of transition

tPLH
[ Propagation delays for a CMOS inverter]

tPW(min) minimum input pulse width (specified storage time) Z > tPHL + tPLH

Power Consumption (Dissipation)

Very low static power dissipation Static : when output is not changing Significant dynamic power dissipation Dynamic : when transitions occur Overall dynamic power consumption : PD = PT + PL PT : internal power dissipation (during transition, both n- and p- channels partially on) Current flows through the transistors from VCC to ground PL : Charging and discharging CL PD = (CPD + CL) VCC2 f CPD : Power-dissipation capacitance (20~40 pF) Vcc = 5V CL : Capacitive load on the output f : transition frequency of the output signal (# of transitions = 2f) Vin Vout CL

Other CMOS Input and Output Structures

Transmission gates Connection of p-channel and n-channel transistors Logic-controlled switch

EN: High & EN_L: Low A-B connecting (2~5 Ohm)

EN: Low & EN_L: high A-B disconnecting

Transmission Gates

2-inputs multiplexer Z = SX + SY Inputs = X & Y, output = Z, S = Selection For a change in the select input to affect the input-output path Several nanoseconds Propagation delay from input to output is at most 0.25 nsec

3-States Output

[ CMOS three state buffer ]

EN= control (output enable)

If EN = High , A = Low , A

OUT OUT

High impedance state (Hi-Z) Or floating state

Open-Drain Outputs

open = HIGH

[ Open-drain CMOS NAND gate ]

Open-Drain Outputs

Slow rise times Why use open-drain outputs? Useful in at least 3 applications Driving light-emitting diodes (LEDs) Driving multisource buses Performing wired logic

Driving LEDs
LED 10mA for brightness Normal CMOS (HC- and HCT-series) 4 mA sink / source current Not proper for driving LED 74AC and 74ACT series Sinking 24 mA Proper for driving LED

VOL + VLED + ILED R = VDD R= VDD VOL VLED ILED =

5 - 0.37 - 1.6 10mA

= 303

Multisource Buses

bus

DATAOUT

At most one control bit (Enablei) is HIGH at any time When Enablei is HIGH and all Enablej (ij) are LOW Datai = HIGH (logic 1) DATAOUT = LOW (0) Datai = LOW (logic 0) DATAOUT = HIGH (1)

Wired Logic

Wired-AND function

HC and HCT Families

HCT (High-speed CMOS, TTL Compatible)

Using power-supply voltage of 5 V Can be intermixed with TTL (transistor-transistor logic) devices

HC (High-speed CMOS)

Optimized for use in systems that use CMOS logic exclusively Using any power-supply voltage 2 ~ 6 V Higher voltage Higher speed Lower voltage Lower power consumption (CV2f) Not quite compatible with TTL identifying CMOS logic levels

HC and HCT Families Logic Levels

[HC]
Identical in output spec. Only input levels differ TTL LOW : 0 ~ 0.8 V HIGH : 2.0 ~ 5.0 V

[HCT]

VHC and VHCT

VHC (Very High-speed CMOS) VHCT (Very High-speed CMOS, TTL compatible) About twice as fast as HC/HCT Differing only in the input levels Output characteristics are the same

CMOS Logic Families

HC (High-speed CMOS) HCT (High-speed CMOS, TTL compatible) AHC (Advanced High-speed CMOS) AHC (Advanced High-speed CMOS, TTL compatible) FCT (Fast CMOS, TTL Compatible) FCT-T (Fast CMOS, TTL Compatible with TTL) FCT positions between HC and AHC in term of electric characteristics

Bipolar Logic
Basic building blocks of bipolar logic circuits Semiconductor diodes Semiconductor bipolar junction transistors Bipolar logic circuits have been replaced with CMOS Still useful to study TTL operation for the occasional applications requiring TTL/CMOS interfacing

Diodes
Fabricated from two types of semiconductor material p-type and n-type

[ pn junction]

[ forward-biased junction]

[ reverse-biased junction]

leakage current

[ symbol] [ transfer char. of an ideal diode ]

breakdown [ transfer char. of a real diode ]

Real Diode Behavior

[ reverse-biased] [ forward-biased] [ transfer char. of forward-biased diode]

Vd (diode drop) : Typically about 0.6 V Rf (forward resistance) : Typically about 25 Ohm forward-biased diode may be considered to have a fixed drop of 0.6 V

Diode Logic : Diode AND Gate

Diode Logic : Diode AND Gate

Bipolar Junction Transistors

Three-terminal device that acts like a current-controlled switch

currents

[ npn transistor ]
[ back-to-back diode ]

[ pnp transistor ]

Transistor Logic Inverter

cut-off region active operating region saturation region

[ switch model ]

npn

Transistor-Transistor Logic (TTL)

Most commonly used bipolar logic family There are many different TTL families With a range of speed, power consumption, and other characteristics. Logic levels LOW : 0 ~ 0.8 V HIGH : 2.0 ~ 5.0 V

Logic Levels and Noise Margins

[ Noise margin for popular TTL logic families (74LS, 74S, 74ALS, 74AS, 74F) ]

TTL Families

74S (Schottky) 74LS (Low-power Schottky) 74AS (Advanced Schottky) 74ALS (Advanced Low-power Schottky) 74F (Fast TTL)
Table 3-10

TTL Families

Fanout
Fanout : # of gate inputs that connected to a single gate output 74LS00 74LS00 ( ref . Fig 3-77 & Fig 3-78 ) ) low state : IILmax = -0.4 mA, IOLmax (for VOLmax) = 8 mA - low state fanout = 20 ) high state : IIHmax = 20 uA, IOHmax (for VOHmin) = -400 uA - high state fanout = 20 ) fanout = lesser of low/high state fanout = 20

IILmax : The maximum current that an input requires to pull it LOW IIHmax : The maximum current that an input requires to pull it HIGH IOLmax : The maximum current an output can sink in the LOW state while maintaining an output voltage no more than VOLmax IOHmax : The maximum current an output can source in the HIGH state while maintaining an output voltage no more than VOHmin

Fanout

Noise margin Driving HC/VHC with TTL does not work due to minus noise margin of H (2.7-3.85=-1.15) HCT, VHCT or FCT are proper CMOS for TTL to drive How about CMOS to drive TTL ? Fanout Driving CMOS with TTL is not a problem since CMOS requires almost no current

CMOS/TTL Interfacing
VILmax

Properly operating for HCT, VHCT, and FCT rather than HC, VHC

CMOS can drive TTL but TTL cannot drive HC, VHC CMOS Fig 3-84 Output and input levels for interfacing TTL and CMOS families ex) Low state DC noise margin = VIL max VOL max = 1.35 ( CMOS ) 0.5 ( TTL ) = 0.85 High state DC noise margin = VOH min VIH min = 2.7 ( TTL ) 3.85 ( HC ) = -1.15 => out of noise margin

CMOS/TTL Interfacing