INTRODUCTION

 Founded in November 1990 y Spun out of Acorn Computers  Designs the ARM range of RISC processor cores  Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. y ARM does not fabricate silicon itself  Also develop technologies to assist with the design-in of the ARM architecture y Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

ARM Partnership Model

ARM Processor Family

Processor family ARM6 ARM7 ARM8 ARM9 ARM10 StrongARM ARM11 # of pipeline stages 3 3 5 5 6 5 8 Memory organization Von Neumann Von Neumann Von Neumann Harvard Harvard Harvard Clock Rate MIPS/MHz 25 MHz 66 MHz 72 MHz 200 MHz 400 MHz 233 MHz 0.9 1.2 1.1 1.25 1.15 1.2

Von Neumann/ 550 MHz Harvard

Nomenclature

ARM Architecture
y 32- it RI y y y y y y y y

- r cess r c re (32- it i structi s) 37 ieces f 32- it i te er re isters (16 availa le) i eli e (ARM7: 3 sta es) ache ( e e i the i le e tati ) V eu a -ty e us structure (ARM7), Harvar (ARM ) 8 / 16 / 32 - it ata ty es 7 es f erati (usr, fiq, irq, svc, a t, sys, u ) i le structure -> reas a ly s ee / er c su ti rati

Data Sizes and Instruction Sets

y The ARM is a 32-bit architecture. y When used in relation to the ARM: y Byte means bits y Halfword means 1 bits (two bytes) y Word means 32 bits (four bytes) y Most ARM s implement two instruction sets y 32-bit ARM Instruction Set y 1 -bit Thumb Instruction Set y Jazelle cores can also execute Java bytecode

Pr c ss r

y The ARM has seven basic operating modes:

y User : unprivileged mode under which most tasks run y FIQ : entered when a high priority (fast) interrupt is raised y IRQ : entered when a low priority (normal) interrupt is raised y Supervisor : entered on reset and when a Software Interrupt

instruction is executed
y Abort : used to handle memory access violations y Undef : used to handle undefined instructions y System : privileged mode using the same registers as user mode

The ARM Register Set

Current Visible Registers Current Visible Registers
SVC Mode Undef Mode User Mode IRQ Mode FIQ Mode Abort
r0 r0 r1 r1 r2 r2 r3 r3 r4 r4 r5 r5 r r r7 r7 r r

Banked out Registers

User
r9

r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr

r10 r11 r12 r13 (sp) r14 (lr)

r12 r13 (sp) r14 (lr)

spsr

FIQ
r r r9 r10 r11

IRQ

SVC

Undef

Abort

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

Register Organization Summary

User
r0 r1 r2 r3 r4 r5 User mode r0-r7, r15, and cpsr

FIQ

IRQ

SVC

Undef

Abort

r9

r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr

r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

spsr

Note: System mode uses the User mode register set

r r7

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

Thumb state High registers

spsr

spsr

spsr

spsr

The Registers
y ARM as 37 re isters all f ic are 32- its l y 1 e icate r ra c ter y 1 e icate c rre t r ra stat s re ister y 5 e icate save r ra stat s re isters y 3 e eral r se re isters y T e c rre t r cess r

accessi le. Eac

e ver s e ca access

ic

f several a

s is

y a artic lar set f r -r12 re isters y a artic lar r13 (t e stac i ter, s ) a y t e r ra c ter, r15 ( c) y t e c rre t r ra stat s re ister, c sr

r1 (t e li

re ister, lr)

rivile e
y

es (exce t yste ) ca als access

r ra stat s re ister)

a artic lar s sr (save

Program Status Registers

31 28 27 24 23 16 15 8 7 6 5 4 0

NZCVQ f

U n d e f i n e d s x

I F T mode c

y Condition code flags

y

y Interrupt Disable bits.

y I = 1: Disables the IRQ. N = Negative result from ALU y F = 1: Disables the FIQ. y Z = Zero result from ALU y C = ALU operation Carried out y V = ALU operation oVerflowed y T Bit y Architecture xT only y Sticky Overflow flag - Q flag y T = 0: Processor in ARM state y Architecture 5TE/J only y T = 1: Processor in Thumb state y Indicates if saturation has occurred y J bit y Mode bits y Architecture 5TEJ only y Specify the processor mode y J = 1: Processor in Jazelle state

Program Counter (r15)

y When the processor is executing in ARM state:
y y y

All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).

y When the processor is executing in Thumb state:

y y y

All instructions are 1 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).

y When the processor is executing in Jazelle state:

y y

All instructions are bits wide Processor performs a word access to read 4 instructions at once

ARM7 FAMILY
y Current low-end ARM core for applications like digital

mobile phones y 32 bit RISC processor. y Uses Von Neumann architecture y as 3-stage pipeline

15

ARM7TDMI Block Diagram

ARM7TDMI Core Diagram

17

ARM INTERFACE SIGNALS

clock control configuration interrupts initialization
mclk wait eclk bigend irq q isync reset enin enout enouti abe ale ape dbe tbe busen highz busdis ecapclk dbgrq breakpt dbgack exec extern1 extern0 dbgen rangeout0 rangeout1 dbgrqi commrx commtx opc cpi cpa cpb Vdd Vss A[31:0] Din[31:0] Dout[31:0] D[31:0] bl[3:0] r/w mas[1:0] mreq seq lock trans mode[4:0] abort Tbit

memory interface

bus control

MMU interface state

ARM7TDMI core

tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs TRST TCK TMS TDI TDO

TAP information

debug

boundary scan extension

coprocessor interface power

JTAG controls

ARM7TDMI Interface Signals

y Clock control
All state change within the processor are controlled by mclk, the memory clock y Internal clock = mclk AND \wait y eclk clock output reflects the clock used by the core
y

y Memory interface
32-bit address A[31:0], bidirectional data bus D[31:0], separate data out Dout[31:0], data in Din[31:0] y seq indicates that the memory address will be se uential to that used in the previous cycle
y

mre q 0 0 1 1

s eq 0 1 0 1

Cy c l e N S I C

Us e Non-sequential memory access Sequential memory access Internal cycle bus and memory inactive Coprocessor register transfer memory inactive
19

Contd .
Lock indicates that the processor should keep the bus to ensure the atomicity of the read and write phase of a SWAP instruction y \r/w, read or write y mas[1:0], encode memory access size byte, half-word or word y bl[3:0], externally controlled enables on latches on each of the 4 bytes on the data input bus
y

y MMU interface
\trans (translation control), 0: user mode, 1: privileged mode y \mode[4:0], bottom 5 bits of the CPSR (inverted) y Abort, disallow access
y

y State
y

T bit, whether the processor is currently executing ARM or Thumb instructions Bigend, big-endian or little-endian
20

y Configuration
y

Contd .
y Interrupt
\fi , fast interrupt re uest, higher priority y \ir , normal interrupt re uest y isync, allow the interrupt synchronizer to be passed
y

y Initialization
y

\reset, starts the processor from a known state, executing from address 000000001

y ARM7TDMI characteristics
Process Metal layers Vdd
0.35 um 3 3.3 V

Transistors Core area Clock

74,209 2 2.1 mm 0 to 66 MHz

MIPS Power MIPS/W

60 87 mW 690

21

Processor Core Vs CPU Core

Processor Core
The engine that fetches instructions and execute them E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S
virtua l ad dress

CPU Core
Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966ES
MMU in structio n & d ata ca che AR M 7T D M I
Em b edd ed IC E & JTAG

p hysica l a ddre ss

in struct io ns & da ta

w rite b uffer A M B A in terfa ce

CP 1 5

A MB A AM BA a dd re ss d ata

ARM710T
22

Memory Access
y The ARM7 is a Von Neumann, load/store architecture, i.e.,
Only 32 bit data bus for both inst. And data. y Only the load/store inst. (and SWP) access memory.
y

y Memory is addressed as a 32 bit address space y Data type can be bit bytes, 1 bit halfwords or 32 bit words, and may be seen as a byte line folded into 4-byte words y Words must be aligned to 4 byte boundaries, and half-words to 2 byte boundaries. y Always ensure that memory controller supports all three access sizes
23

ARM Memory Interface

y Se uential (S cycle)
y (nMREQ, SEQ) = (0, 1) y The ARM core re uests a transfer to or from an address which is either the same,

or one word or one-half-word greater than the preceding address.

y Non-se uential (N cycle)

y (nMREQ, SEQ) = (0, 0) y The ARM core re uests a transfer to or from an address which is unrelated to the

address used in the preceding address.

y Internal (I cycle)
y (nMREQ, SEQ) = (1, 0) y The ARM core does not re uire a transfer, as it performing an internal function,

and no useful prefetching can be performed at the same time

y Coprocessor register transfer (C cycle)

y (nMREQ, SEQ) = (1, 1) y The ARM core wished to use the data bus to communicate with a coprocessor,

but does not re uire any action by the memory system.

24

Cached ARM7TDMI Macrocells

EmbeddedICE & JTAG CP15

ARM Core Physical Address AMBA Interface

MMU

Virtual Address Inst. & data

AMBA Address AMBA Data

Inst. & data cache

Write Buffer

y ARM71 T
8K ifie rite t r cac e y ll e ry a a e e t it s rti virt al e ry y rite ffer
y

ARM72 T
As ARM 71 T s rt

t it

ARM 7

T
cac e it
25

8K ifie rite t r Me ry r tecti rite ffer

ARM7 Register Set

y Register structure depends on mode of operation y 1 pieces of 32-bit integer registers R0 - R15 are available in y y y y y y y

ARM-mode (usr, user) R0 - R12 are general purpose registers R13 is Stack Pointer (SP) R14 is subroutine Link Register olds the value of R15 when BL-instruction is executed R15 is Program Counter (PC) Bits 1 and 0 are zeroes in ARM-state (32-bit addressing) R1 is state register (CPSR,Current Program Status Register

ARM9 Family Technical Features

y Based on ARMv5TE architecture y Efficient 5-stage pipeline for faster clocking and system

performance y Supports both ARM and Thumb instruction sets y Harvard architecture - Separate Instruction & Data memory interfaces
y Increased available memory bandwidth y Simultaneous access to I & D memory y Improved performance

y 31 x 32-bit registers y 32-bit ALU & barrel shifter

PIPELINE OPERATIONS

ARM9 family processor naming - ARM9xxE(J)-S

y E - DSP extensions y Enhanced instructions for efficient fractional saturating arithmetic y Single cycle 32x16 multiplier implementation y 32x16 and 16x16 multiply instructions y Count leading zeros instruction y J - Java acceleration through Jazelle y Reduced complexity & power consumption over a typical Java hardware coprocessor solution y Available on the ARM926EJ-S processor only y S - Fully synthesizable

The ARM9 family

y ARM968E-S: Smallest footprint ARM9 processor with DSP

enhancements, for low power, data intensive, embedded real-time applications y ARM946E-S: DSP enhanced cached processor with an MPU for real-time applications running an RTOS y ARM926EJ-S: Application processor with Java acceleration, DSP extensions and an MMU, for OS based applications

ARM 9 Application
y Consumer: Smartphones, PDA, Set top box, PMP,

y y y y

Electronic toys, Digital still cameras, Digital video cameras etc Networking: Wireless LAN, 802.11, Bluetooth, Firewire, SCSI, 2.5G/3G Baseband etc Automotive : Power train, ABS, Body systems, Navigation, Infotainment etc Embedded : USB controllers,bluetooth controllers, medical scanners etc Storage: DD controllers, solid state drives etc

ARM10 FAMILY
y 32-bit RISC processor with ARM, Thumb and DSP

instruction sets. y Supports six-stage Pipelines for fixed point instructions

Fetch Issue Decode Execute Memory Write

y Instruction set expanded to version 5 (V5te) y Improved instruction execution y Uses Harvard Architecture y Widely used in videophone, PDAs, set-top boxes, game

console, digital video cameras,automotive and industrial control systems

ARM 11
y The ARM11 Family y 32-bit RISC processor with ARM, Thumb and DSP y y y y

instruction sets. Uses Harvard Architecture. Supports eight-stage Pipelines except ARM1156T2 uses nine-stage pipeline. Widely used in automotive and industrial control systems, 3D graphics, security critical applications. introduces 32-bit SIMD for media processing

ARM11 Processor Family Features

y Powerful ARMv6 instruction set architecture y ARM Thumb instruction set y ARM Jazelle technology for efficient embedded Java execution y ARM DSP extensions y SIMD media processing extensions deliver up to 2x performance for video processing y ARM TrustZone technology for on-chip security foundation y Thumb-2 technology for enhanced performance, energy efficiency and code density y Low power consumption y High performance integer processor

ARM Cortex Embedded Processors

y Cortex-M series: developed primarily for fast, highly

deterministic, interrupt management - low gate count low power consumption. y Cortex-R series: for deeply embedded real-time applications - low power and good interrupt behaviour are balanced with exceptional performance and strong compatibility with existing platforms.

Cortex Processors Features

y Greater performance efficiency: allowing more work

to be done without increasing the frequency or power requirements y Low power consumption: enabling longer battery life, especially critical in portable products including wireless networking applications y Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as quickly as possible and in a known number of cycles y Improved code density: ensuring that code fits in even the smallest memory footprints

y Ease of use: providing easier programmability and

debugging for the growing number of 8-bit and 16-bit users migrating to 32 bits y Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than US$1 for the first time y Wide choice of development tools: from low-cost or free compilers to full-featured development suites from many development tool vendors

Cortex-M3 Processor Applications

y Low-cost microcontrollers:for low-cost

microcontrollers,which are commonly used in consumer products - lower power, high performance, and ease-ofuse enables embedded developers to migrate to 32-bit systems y Automotive: very high-performance efficiency and low interrupt latency, allowing it to be used in real-time systems. - supports up to 240 external vectored interrupts, with a built-in interrupt controller with nested interrupt supports , making it ideal for highly integrated and cost-sensitive automotive applications.

Continued ..
y Data communications: low power and high efficiency,

coupled with instructions in Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for many communications applications, such as Bluetooth and ZigBee. y Industrial control: In industrial control applications, simplicity, fast response, and reliability are key factors. y Consumer products: being a small processor, is highly efficient and low in power and supports an MPU enabling complex software to execute while providing robust memory protection.

CONCLUSION
y Continuous evolution of the ARM processors. y Use of various design techniques such as RISC architectures, pipelines, DSP extension and Jazelle technology. y High performance, lower power consumption and system cost, low silicon area and time-to-market. y Provide benefits in the wide area of technology design and developments such as embedded real time applications, automotive control systems, portable applications and secure applications.

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