03 Wafer Prep

Chapter 3
Silicon and Wafer Preparation
Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda
2001 by Prentice Hall
Objectives
After studying the material in this chapter, you will be able to: 1. Describe how raw silicon is refined into semiconductor grade silicon. 2. Explain the crystal structure and growth method for producing monocrystal silicon. 3. Discuss the major defects in silicon crystal. 4. Outline and describe the basic process steps for wafer preparation, starting from a silicon ingot and finishing with a wafer. 5. State and discuss seven quality measures for wafer suppliers. 6. Explain what is epitaxy and why it is important for wafers.
Semiconductor-Grade Silicon
Steps to Obtaining Semiconductor Grade Silicon (SGS) Step
1
Description of Process
Produce metallurgical grade silicon (MGS) by heating silica with carbon Purify MG silicon through a chemical reaction to produce a silicon-bearing gas of trichlorosilane (SiHCl3) SiHCl3 and hydrogen react in a process called Siemens to obtain pure semiconductorgrade silicon (SGS) SiC (s) + SiO2 (s)
Reaction
Si (l) + SiO(g) + CO (g)
Si (s) + 3HCl (g)
SiHCl3 (g) + H 2 (g) + heat
2SiHCl3 (g) + 2H 2 (g)
2Si (s) + 6HCl (g)

Table 4.1
Crystal Structure
Amorphous Materials Unit Cells Polycrystal and Monocrystal Structures Crystal Orientation

Siemens Reactor for SG Silicon
SiHCl3
Polycrystalline silicon rod

Figure 4.1
Atomic Order of a Crystal Structure

Figure 4.2
Amorphous Atomic Structure

Figure 4.3
Unit Cell in 3-D Structure
Unit cell

Figure 4.4
Faced-centered Cubic (FCC) Unit Cell

Figure 4.5
Silicon Unit Cell: FCC Diamond Structure

Figure 4.6
Polycrystalline and Monocrystalline Structures
Polycrystalline structure
Monocrystalline structure

Figure 4.7
Axes of Orientation for Unit Cells

Z
1
X
1
Figure 4.8 2001 by Prentice Hall
Miller Indices of Crystal Planes
Y X (100) X (110)
Y X (111)

Figure 4.9
Monocrystal Silicon Growth

CZ Method
CZ Crystal Puller Doping Impurity Control
Float-Zone Method Reasons for Larger Ingot Diameters

CZ Crystal Puller
Crystal puller and rotation mechanism
Crystal seed
Single crystal silicon Quartz crucible Carbon heating element

Molten polysilicon Heat shield Water jacket

Silicon Ingot Grown by CZ Method
Photograph courtesy of Kayex Corp., 300 mm Si ingot

Photo 4.1
CZ Crystal Puller
Photograph courtesy of Kayex Corp., 300 mm Si crystal puller

Photo 4.2
Dopant Concentration Nomenclature
Concentration (Atoms/cm3) Dopant Pentavalent Trivalent Material Type n p < 1014

(Very Lightly Doped)
1014 to 1016
(Lightly Doped)
1016 to 1019
(Doped)
>1019
(Heavily Doped)
n-p--
np-
n p
n+ p+

Table 4.2
Float Zone Crystal Growth

Gas inlet (inert) Chuck Polycrystalline rod (silicon) Molten zone Traveling RF coil
RF
Seed crystal Chuck Inert gas out

Figure 4.11
Wafer Diameter Trends
300 mm
200 mm 150 mm 125 mm 100 mm 75 mm
3t
4t
5t
6t
8t
Figure 4.12
12t

Wafer Dimensions & Attributes
iameter (mm) 150 200 300 400
Thickness (Qm) 675 s 20 725 s 20 775 s 20 825 s 20
Area (cm2) 176.71 314.16 706.86 1256.64
Weight (grams/lbs) 28 / 0.06 53.08 / 0.12 127.64 / 0.28 241.56 / 0.53
Weight/25 Wafers (lbs) 1.5 3 7 13

Table 4.3
Increase in Number of Chips on Larger Wafer Diameter
88 die 200-mm wafer 232 die 300-mm wafer

Figure 4.13
Developmental Specifications for 300-mm Wafer Dimensions and Orientation

Parameter Units Nominal Some Typical Tolerances
Diameter Thickness (center point) Warp (max) Nine-Point Thickness Variation (max) Notch Depth Notch Angle Back Surface Finish Edge Profile Surface Finish FQA (Fixed Quality Area radius permitted on the wafer surface)
mm Qm Qm Qm mm Degree
300.00 775 100 10 1.00 90 Bright Etched/Polished Polished
s 0.20 s 25
+ 0.25, -0.00 +5, -1
mm
147
From H. Huff, R. Foodall, R. Nilson, and S. Griffiths, Thermal Processing Issues for 300-mm Silicon Wafers: Challenges and Opportunities, ULSI Science and Technology (New Jersey: The Electrochemical Society, 1997), p. 139.

Table 4.4
Crystal Defects in Silicon

A crystal defect (microdefect) is any interruption in the repetitive nature of the unit cell crystal structure. Three general types of crystal defects in silicon: 1. Point defects - Localized crystal defect at the atomic level 2. Dislocations - Displaced unit cells 3. Gross defects - Defects in crystal structure

Yield of a Wafer
Yield =
66 good die = 75% 88 total die
Reduction in defect density is a critical aspect for increasing wafer yield.

Figure 4.14

Point Defects
(a) Vacancy defect
(b) Interstitial defect
(c) Frenkel defect
Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 23 Semiconductor Manufacturing Technology
Figure 4.15
Dislocations in Unit Cells

Figure 4.16
Crystal Slip (Gross Defects)
(a)
(b)
(c)
Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 49

Figure 4.17
Crystal Twin Planes (Gross Defects)
Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 55

Figure 4.18
Basic Process Steps for Wafer Preparation
Crystal Growth
Wafer Lapping and Edge Grind
Cleaning
Shaping
Etching
Inspection
Wafer Slicing
Polishing
Packaging

Figure 4.19
Ingot Diameter Grind

Preparing crystal ingot for grinding
Diameter grind
Flat grind

Figure 4.20
Wafer Identifying Flats
P-type (111)
P-type (100)
N-type (111)
N-type (100)
Wafer Notch and Laser Scribe
Notch
Scribed identification number

Figure 4.22
Internal Diameter Saw

Internal diameter wafer saw

Figure 4.23
Polished Wafer Edge

Figure 4.24
Chemical Etch of Wafer Surface to Remove Damage

Figure 4.25
Double-Sided Wafer Polish
Upper polishing pad
Wafer Slurry Lower polishing pad

Figure 4.26
Quality Measures
Physical dimensions Flatness Microroughness Oxygen content Crystal defects Particles Bulk resistivity

Improving Silicon Wafer Requirements

1995 (0.35 Qm)
Wafer diameter (mm) ite flatnessA (Qm) ite size (mm x mm) icroroughness of front surface (R ) (nm) xygen content (ppm) ulk microdefects (defects/cm2) articles per unit area (#/cm2) pilayer F thickness (s uniformity) (Qm)
Adapted from K.
Year (Critical ime sio ) 1998 2000 (0.25 Qm) (0.18 Qm)
200 0.17 (26 x 32) 0.15 300 0.12 26 x 32 0.1
2004 (0.13 Qm)

300 0.08 26 x 36 0.1
200 0.23 (22 x 22) 0.2
e 24 s 2 e 5000
0.17 3.0 (s 5 )
e 23 s 2 e 1000
0.13 2.0 (s 3 )
e 23 s 1.5 e 500
0.075 1.4 (s 2 )
e 22 s 1.5 e 100
0.055 1.0 (s 2 )
. Kim, igger and etter Z ilicon rystals, Solid State Technology (November 1996), p. 71.

Improving Silicon Wafer Requirements

Notes: A. Flatness is the linear thickness variation across the wafer or a site on a wafer (see below). B. See below for a description of microroughness. C. RMS is a method for determining the best estimate of group of measurements in this case, the surface finish measurements (see below). It is calculated by taking the root-mean-square (square root of the average of all measurements squared). Surface finish measurements are obtained by measuring the highest point relative to the lowest point on a surface. D. ppm is part per million. E. Bulk microdefects represents all defects within a square centimeter. F. See below to define epilayer.

Wafer Deformation
Positive deviation
Wafer
Negative deviation Reference plane
Vacuum chuck

Figure 4.27
Flatness of Wafer Front Surface
Silicon wafer surface

Figure 4.28
Formation of Epitaxial Silicon Layers
Epitaxial layer
Silicon wafer Monocrystalline layers

Figure 4.29
Chapter 4 Review
Summary Key Terms Review Questions Selected Industry Web Sites References 88 88 89 90 90


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Chapter 3

Silicon and Wafer Preparation

Semiconductor Manufacturing Technology

2001 by Prentice Hall

2001 by Prentice Hall

Si (s) + 3HCl (g)

SiHCl3 (g) + H 2 (g) + heat

2SiHCl3 (g) + 2H 2 (g)

2Si (s) + 6HCl (g)

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Siemens Reactor for SG Silicon

Polycrystalline silicon rod

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Atomic Order of a Crystal Structure

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Amorphous Atomic Structure

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Unit Cell in 3-D Structure

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Faced-centered Cubic (FCC) Unit Cell

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Silicon Unit Cell: FCC Diamond Structure

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Polycrystalline and Monocrystalline Structures

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Axes of Orientation for Unit Cells

Miller Indices of Crystal Planes

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Monocrystal Silicon Growth

Float-Zone Method Reasons for Larger Ingot Diameters

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Single crystal silicon Quartz crucible Carbon heating element

Molten polysilicon Heat shield Water jacket

Silicon Ingot Grown by CZ Method

Photograph courtesy of Kayex Corp., 300 mm Si ingot

2001 by Prentice Hall

Photograph courtesy of Kayex Corp., 300 mm Si crystal puller

2001 by Prentice Hall

Dopant Concentration Nomenclature

Concentration (Atoms/cm3) Dopant Pentavalent Trivalent Material Type n p < 1014

Semiconductor Manufacturing Technology

2001 by Prentice Hall

Float Zone Crystal Growth

Seed crystal Chuck Inert gas out

2001 by Prentice Hall

Wafer Diameter Trends

200 mm 150 mm 125 mm 100 mm 75 mm

Semiconductor Manufacturing Technology

Wafer Dimensions & Attributes

iameter (mm) 150 200 300 400

Thickness (Qm) 675 s 20 725 s 20 775 s 20 825 s 20